CN103311107B - Make the method for metal silicide and apply its semiconductor structure - Google Patents
Make the method for metal silicide and apply its semiconductor structure Download PDFInfo
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- CN103311107B CN103311107B CN201210061510.0A CN201210061510A CN103311107B CN 103311107 B CN103311107 B CN 103311107B CN 201210061510 A CN201210061510 A CN 201210061510A CN 103311107 B CN103311107 B CN 103311107B
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Abstract
The invention discloses and a kind ofly make the method for metal silicide and apply its semiconductor structure.The method of this making metal silicide, comprises the following steps: to provide a substrate, and substrate has a first area and a second area; Form a silicon layer on substrate; Carry out a flatening process, to make silicon layer, there is a flat surfaces; Remove part silicon layer, to form multiple first grid in first area and to form multiple second grid at second area, the height of the plurality of first grid is greater than the height of the plurality of second grid, and the plurality of first grid and the plurality of second grid have the consistent upper surface of elevation of water; Form a dielectric layer on substrate, dielectric layer covers the plurality of first grid and the plurality of second grid, and manifests the upper surface of the plurality of first grid and the plurality of second grid; Form a metal silicide in the upper surface of the plurality of first grid and the plurality of second grid.
Description
Technical field
The invention relates to a kind of semiconductor technology and structure, and relate to especially and a kind ofly make the method for metal silicide and apply its semiconductor structure.
Background technology
Along with the increase of semiconductor element integrated level, pattern in element and live width also reduce gradually, thus cause the contact resistance of the grid in element and wire to increase, produce larger Resistance-Capacitance delay (RCDelay), and then affect element operation speed.Due to the resistance of metal silicide, comparatively polysilicon (Polysilicon) is low, and its thermal stability is also high than general interconnect material, thus on grid, forms metal silicide, to reducing the resistance value between grid and metal interconnect.
Tradition is formed in the process of metal silicide, after grid (such as polysilicon layer) is formed on a semiconductor wafer, the silicification technics of grid comprises formation one metal level on polysilicon layer, then carries out annealing process, to form metal silicide on grid.
On the fabrication of current peripheral circuit area, also need to use metal silicide to reduce the resistance between wire and grid.But, in traditional self-aligning metal silicide technology, to form metal silicide on certain media, then have to pass through quite complicated program, metal silicide could be formed on required region, especially, when memory cell array region is different from the elevation of water of peripheral circuit area, the difficulty that technique performs more is improved.Stressing in the high efficiency epoch at present, certainly will will improve traditional way, to improve the efficiency of semiconductor technology.
Summary of the invention
The invention relates to and a kind ofly make the method for metal silicide and apply its semiconductor structure, being the grid consistent with peripheral circuit area being formed elevation of water in memory cell array region, metal silicide cannot being formed smoothly to avoid the grid being positioned at lower region because dielectric layer covers.
According to an aspect of the present invention, propose a kind of method making metal silicide, comprise the following steps.There is provided a substrate, substrate has a first area and a second area.Form a silicon layer on substrate.Carry out a flatening process, to make silicon layer, there is a flat surfaces.Remove part silicon layer, to form multiple first grid in first area and to form multiple second grid at second area, the height of the plurality of first grid is greater than the height of the plurality of second grid, and the plurality of first grid and the plurality of second grid have the consistent upper surface of elevation of water.Form a dielectric layer on substrate, dielectric layer covers the plurality of first grid and the plurality of second grid, and manifests the upper surface of the plurality of first grid and the plurality of second grid.Form a metal silicide in the upper surface of the plurality of first grid and the plurality of second grid.
According to a further aspect in the invention, propose a kind of semiconductor structure, comprise a substrate, a silicon layer, a dielectric layer and a metal silicide.Substrate has a first area and a second area.Silicon layer has the multiple first grid being positioned at first area and the multiple second grids being positioned at second area, wherein the height of the plurality of first grid is greater than the height of the plurality of second grid, and the plurality of first grid and the plurality of second grid have the consistent upper surface of elevation of water.Dielectric layer is formed on substrate, and dielectric layer manifests the upper surface of the plurality of first grid and the plurality of second grid.Metal silicide is formed at the upper surface of the plurality of first grid and the plurality of second grid respectively.
In order to have better understanding, special embodiment below to above-mentioned and other aspect of the present invention, and coordinating institute's accompanying drawings, being described in detail below:
Accompanying drawing explanation
Figure 1A ~ Fig. 1 F illustrate according to the making metal silicide of one embodiment of the invention method and apply its schematic diagram of semiconductor structure.
Fig. 2 A ~ Fig. 2 F illustrate according to the making metal silicide of one embodiment of the invention method and apply its schematic diagram of semiconductor structure.
[main element symbol description]
100,200: substrate
101,201: first area
102,202: second area
103,203: join domain in local
104: inclined surface
110,110a, 210,210a: silicon layer
111,211: flat surfaces
120,220: upper surface
121,221: first grid
122,222: second grid
123,223: the three grids
130,230: dielectric layer
140,240: metal silicide
W, X, X1, Y: highly
212: polysilicon layer
214,214a: amorphous silicon layer
Embodiment
The method of making metal silicide of the present invention and apply its semiconductor structure, be the silicon layer increased at deposited on substrates thickness, recycling flatening process carries out thinning, has the consistent flat surfaces of elevation of water to make silicon layer.After this silicon layer is patterned, form the consistent first grid of elevation of water and second grid.Therefore, the grid on memory cell array region and peripheral circuit area, in follow-up thermal process, all can form metal silicide smoothly, to reduce the sheet resistance values of grid.
Be below propose various embodiment to be described in detail, embodiment only in order to illustrate as example, and is not used to the scope of limit the present invention for protection.
First embodiment
Please refer to Figure 1A ~ Fig. 1 F, its illustrate according to the making metal silicide of one embodiment of the invention method and apply its schematic diagram of semiconductor structure.The method at least comprises the following steps.There is provided a substrate 100, substrate 100 has first area 101 and a second area 102.Form a silicon layer 110 on substrate 100.Carry out a flatening process, to make silicon layer 110, there is a flat surfaces 111.Remove part silicon layer 110, to form multiple first grid 121 in first area 101 and to form multiple second grid 122 at second area 102.The height X+Y of first grid 121 is greater than the height Y of second grid 122, and first grid 121 and second grid 122 have the consistent upper surface of elevation of water 120.Form a dielectric layer 130 on substrate 100, dielectric layer 130 covers the plurality of first grid 121 and second grid 122, and manifests the upper surface 120 of the plurality of first grid 121 and second grid 122.Form a metal silicide 140 in the upper surface 120 of the plurality of first grid 121 with second grid 122.
In figure ia, substrate 100 has first area 101 and a second area 102.Silicon layer 110 is formed on substrate 100, and equal thickness ground covers first area 101 and second area 102.The first area 101 of substrate 100 has different height from second area 102 relative to the bottom surface of substrate 100, makes obviously to have a difference in height X between first area 101 and second area 102.In addition, substrate 100 such as has an inclined surface 104 and is arranged in a local join domain 103, and join domain 103 in local is favoured between first area 101 and second area 102.
In the present embodiment, substrate 100 is for being rich in the Semiconductor substrate of silicon, silicon layer 110 is such as the polysilicon layer formed with chemical vapour deposition technique, it has the height W being greater than predetermined height of deposition X+Y, wherein X is the difference in height of first area 101 and second area 102, and Y is the ideal height of second grid 122.First area 101 is such as memory cell array region, and second area 102 is such as peripheral circuit area.In another embodiment, first area 101 is such as peripheral circuit area, and second area 102 is such as memory cell array region.In memory cell array region, there is active element (such as Memory Storage Unit), in order to storage data.There is logical block (such as transistor switch) in peripheral circuit area, in order to read and the data stored in computing store memory cell.In follow-up technique, the silicon layer 110 after flatening process and Patternized technique can respectively as the grid of the grid of Memory Storage Unit and logical block.
Please refer to Figure 1B, carry out the flatening process such as chemico-mechanical polishing, to make silicon layer 110a, there is flat surfaces 111.Now, the silicon layer 110a after thinning is X+Y relative to the height of first area 101, and is Y relative to the height of second area 102.Then, please refer to Fig. 1 C, remove part silicon layer 110a, to form multiple first grid 121 in first area 101 and to form multiple second grid 122 at second area 102 by techniques such as photoetching and anisotropic etchings.The height of first grid 121 is X+Y, and the height of second grid 122 is Y, therefore the height of first grid 121 is greater than the height of second grid 122, and first grid 121 and second grid 122 have the consistent upper surface of elevation of water 120.In the technique of Fig. 1 C, more can form one the 3rd grid 123 in local on join domain 103, and first grid 121, second grid 122 has the consistent upper surface of elevation of water 120 with the 3rd grid 123.In the present embodiment, first grid 121, second grid 122 and the 3rd grid 123 are such as the grid of the transistor (such as N-type metal oxide semiconductor transistor) that polarity is identical, or with the grid of the opposite polarity P-type mos transistor of N-type metal oxide semiconductor transistor.In one embodiment, the 3rd grid 123 also can replace by the local connection wire between first grid 121 and second grid 122, be not defined as the grid of transistor.
Please refer to Fig. 1 D and Fig. 1 E, form a dielectric layer 130 on substrate 100, in the space that dielectric layer 130 is filled between adjacent two grids, and cover the upper surface 120 of first grid 121, second grid 122 and the 3rd grid 123.In fig. ie, dielectric layer 130 carries out thinning by flatening process such as chemico-mechanical polishings, makes dielectric layer 130 consistent with the elevation of water of grid 121-123, and manifests the upper surface 120 of first grid 121, second grid 122 and the 3rd grid 123.
Then, please refer to Fig. 1 F, form a metal silicide 140 respectively in the upper surface 120 of first grid 121, second grid 122 and the 3rd grid 123.Metal silicide 140 is in the process of carrying out thermal process, such as 960 degree Celsius, metal level and the silicon layer 110a high temperature hot melt of contiguous thinning and metallic and silicon wafer are rearranged formed.The step forming self-aligned metal silicate 140 is in figure 1f as follows.First, a metal level (not illustrating) is formed on the silicon layer 110a and dielectric layer 130 of thinning with chemical vapour deposition technique or physical vaporous deposition.Carry out a thermal process, such as annealing process, to make metal level and silicon layer 110a cross reaction and to form metal silicide 140.Then, the partial metal layers do not reacted with silicon layer 110a is removed.Metal silicide 140 is such as tungsten silicide (tungstensilicide), molybdenum silicide (molybdenumsilicide), cobalt silicide (cobaltsilicide), titanium silicide (titaniumsilicide), nickle silicide (nickelsilicide) or other refractory metal silicides (refractorymetalsilicde), to reduce the sheet resistance values of first grid 121, second grid 122 and the 3rd grid 123.
Second embodiment
Please refer to Fig. 2 A ~ Fig. 2 F, its illustrate according to the making metal silicide of one embodiment of the invention method and apply its schematic diagram of semiconductor structure.The present embodiment and the first embodiment difference are: the step forming planarization silicon layer 210 in silicon layer 210 and Fig. 2 B in Fig. 2 A.As for the patterning silicon layer 210a in Fig. 2 C ~ Fig. 2 F, form dielectric layer 230 and the technique such as planarized dielectric layer 230, formation metal silicide 240, all identical with the technique of above-mentioned first embodiment, do not repeat them here.
Please refer to Fig. 2 A, silicon layer 210 comprises the amorphous silicon layer 214 with the polysilicon layer 212 of chemical vapour deposition technique formation first height Y and the second height X1, wherein the second height X1 is greater than the difference in height X of (or equaling) first area 201 and second area 202, and the first height Y is the ideal height of second grid 222, therefore silicon layer 210 has the total height W being greater than predetermined height of deposition X+Y.
Please refer to Fig. 2 B, carry out the flatening process such as chemico-mechanical polishing, to make silicon layer 210, there is flat surfaces 211.Now, the silicon layer 210a after thinning is X+Y relative to the height of first area 201, and is Y relative to the height of second area 202.In the present embodiment, the amorphous silicon layer 214 being positioned at second area 202 is removed and manifests the polysilicon layer 212 of below, make the amorphous silicon layer 214a be not removed in Fig. 2 B trim polysilicon layer 212, and with polysilicon layer 212, there is the consistent flat surfaces of elevation of water 211.Because the polysilicon layer 212 be positioned at below amorphous silicon layer 214 can be used as the suspension layer of etching or chemico-mechanical polishing silicon layer 210, therefore accurately can control the degree of depth of silicon layer 210 etching.
In follow-up Fig. 2 B, before formation metal silicide 240, amorphous silicon layer 214a, by heating, such as about 600 degree Celsius, makes its recrystallization and converts another polysilicon layer to.Because polysilicon layer has preferably electron mobility relative to amorphous silicon layer 214a, therefore the switching capability of Memory Storage Unit and the driving force of logical block can be improved.
In the present embodiment, after silicon layer 210a patterned (with reference to Fig. 2 C), first grid 221, second grid 222 form the consistent upper surface of elevation of water 220 with the 3rd grid 223.Therefore, grid in first area 201 (such as memory cell array region), second area 202 (such as peripheral circuit area) and local on join domain 203, in follow-up thermal process, all can form metal silicide 240 smoothly, to reduce the sheet resistance values of grid.
In sum, although the present invention with preferred embodiment disclose as above, so itself and be not used to limit the present invention.Persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is when being as the criterion of defining depending on the right of enclosing.
Claims (10)
1. make a method for metal silicide, comprising:
There is provided a substrate, this substrate has a first area and a second area;
Form a silicon layer on this substrate;
Carry out a flatening process, to make this silicon layer, there is a flat surfaces;
Remove this silicon layer of part, to form multiple first grid in this first area and to form multiple second grid at this second area, the height of the plurality of first grid is greater than the height of the plurality of second grid, and the plurality of first grid and the plurality of second grid have the consistent upper surface of elevation of water;
Form a dielectric layer on this substrate, wherein this dielectric layer fills in the space between adjacent the plurality of first grid and between the plurality of second grid, and this dielectric layer is consistent with the elevation of water of the plurality of first grid and the plurality of second grid, and manifest the upper surface of the plurality of first grid and the plurality of second grid; And
Form a metal silicide in the upper surface of the plurality of first grid and the plurality of second grid.
2. the method for making metal silicide according to claim 1, wherein this first area and this second area are respectively memory cell array region and peripheral circuit area.
3. the method for making metal silicide according to claim 1, wherein this substrate have an inclined surface be arranged in one local join domain, in this local, join domain is between this first area and this second area, this first area of this substrate has a difference in height relative to this second area, and the plurality of first grid is formed on this highly lower first area, the plurality of second grid is formed on this highly higher second area.
4. the method for making metal silicide according to claim 1, the step wherein forming this silicon layer and this silicon layer of planarization comprises:
Form a polysilicon layer on this substrate;
Form an amorphous silicon layer on this polysilicon layer; And
This amorphous silicon layer of planarization, to make this amorphous silicon layer trim this polysilicon layer, and has a flat surfaces with this polysilicon layer.
5. the method for making metal silicide according to claim 4, wherein after this amorphous silicon layer of planarization, more comprises this amorphous silicon layer of heating to recrystallization temperature to form another polysilicon layer.
6. the method for making metal silicide according to claim 1, after wherein forming this dielectric layer, more comprises this dielectric layer of planarization.
7. the method for making metal silicide according to claim 1, the step wherein forming this metal silicide comprises:
Form a metal level on this silicon layer and this dielectric layer;
Carry out a thermal process, react to make this metal level and this silicon layer and form this metal silicide; And
Remove this metal level of part do not reacted with this silicon layer.
8. a semiconductor structure, comprising:
One substrate, this substrate has a first area and a second area;
One silicon layer, there are the multiple first grid being positioned at this first area and the multiple second grids being positioned at this second area, wherein the height of the plurality of first grid is greater than the height of the plurality of second grid, and the plurality of first grid and the plurality of second grid have the consistent upper surface of elevation of water;
One dielectric layer, be formed on this substrate, wherein this dielectric layer fills in the space between adjacent the plurality of first grid and between the plurality of second grid, and this dielectric layer is consistent with the elevation of water of the plurality of first grid and the plurality of second grid, and manifest the upper surface of the plurality of first grid and the plurality of second grid; And
One metal silicide, is formed at the upper surface of the plurality of first grid and the plurality of second grid respectively.
9. semiconductor structure according to claim 8, wherein this first area and this second area are respectively memory cell array region and peripheral circuit area, this silicon layer is at least one polysilicon layer or is combined by a polysilicon layer and an amorphous silicon layer, and the plurality of first grid and the plurality of second grid are respectively the grid of Memory Storage Unit and the grid of logical block.
10. semiconductor structure according to claim 8, wherein this substrate have an inclined surface be arranged in one local join domain, in this local, join domain is between this first area and this second area, this silicon layer more comprises one the 3rd grid, be arranged in this local join domain, this first area of this substrate has a difference in height relative to this second area, and the plurality of first grid is formed on this highly lower first area, the plurality of second grid is formed on this highly higher second area.
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| US5828120A (en) * | 1996-02-23 | 1998-10-27 | Nippon Steel Corporation | Semiconductor device and production method thereof |
| TW424303B (en) * | 1999-06-17 | 2001-03-01 | United Microelectronics Corp | Manufacturing method for dual-gate CMOS device |
| US6541357B1 (en) * | 2001-12-04 | 2003-04-01 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
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| JPH02172253A (en) * | 1988-12-24 | 1990-07-03 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
| KR20100079960A (en) * | 2008-12-31 | 2010-07-08 | 삼성전자주식회사 | Method for formation of flash memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5828120A (en) * | 1996-02-23 | 1998-10-27 | Nippon Steel Corporation | Semiconductor device and production method thereof |
| TW424303B (en) * | 1999-06-17 | 2001-03-01 | United Microelectronics Corp | Manufacturing method for dual-gate CMOS device |
| US6541357B1 (en) * | 2001-12-04 | 2003-04-01 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
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