CN103311107A - Metal silicide production method, and semiconductor structure with application of metal silicide - Google Patents
Metal silicide production method, and semiconductor structure with application of metal silicide Download PDFInfo
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- CN103311107A CN103311107A CN2012100615100A CN201210061510A CN103311107A CN 103311107 A CN103311107 A CN 103311107A CN 2012100615100 A CN2012100615100 A CN 2012100615100A CN 201210061510 A CN201210061510 A CN 201210061510A CN 103311107 A CN103311107 A CN 103311107A
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Abstract
The invention discloses a metal silicide production method, and a semiconductor structure with application of the metal silicide. The metal silicide production method comprises the following steps: a substrate is provided, wherein the substrate includes a first area and a second area; a silicon layer is formed on the substrate; a planarization process is carried out so that the silicon layer is provided with a flat surface; a portion of the silicon layer is removed so that a plurality of first grids are formed in the first area and a plurality of second grids are formed in the second area, wherein height of the plurality of first grids is bigger than that of the plurality of second grids, and an upper surface of the plurality of first grids and an upper surface of the plurality of second grids are consistent in the height of the horizontal plane; a dielectric layer is formed on the substrate, wherein the dielectric layer covers the plurality of first grids and the plurality of second grids and exposes the upper surface of the plurality of first grids and the upper surface of the plurality of second grids; and the metal silicide is formed on the upper surface of the plurality of first grids and the upper surface of the plurality of second grids.
Description
Technical field
The invention relates to a kind of semiconductor technology and structure, and particularly relevant for a kind of semiconductor structure of making the method for metal silicide and using it.
Background technology
Along with the increase of semiconductor element integrated level, pattern and live width in the element are also dwindled gradually, thereby cause grid in the element and the contact resistance of wire to increase, and produce larger resistance-capacitance and postpone (RC Delay), and then affect element operation speed.Because the resistance of metal silicide is low than polysilicon (Polysilicon), and its thermal stability is also high than general interconnect material, thereby forms metal silicide at grid, to reducing the resistance value between grid and the metal interconnect.
Tradition forms in the process of metal silicide, after grid (for example polysilicon layer) is formed on the semiconductor crystal wafer, the silicification technics of grid comprises that formation one metal level on polysilicon layer, then carries out annealing process, to form metal silicide on grid.
On the fabrication of present peripheral circuit area, also need to reduce resistance between wire and the grid with metal silicide.Yet, in traditional self-aligning metal silicide technology, if will form metal silicide at the part medium, then must be through the program of very complex, could form metal silicide in required zone, especially work as the elevation of water of memory cell array zone and peripheral circuit area not simultaneously, more improve the difficulty that technique is carried out.Stressing at present in the high efficiency epoch, certainly will will improve traditional way, to improve the efficient of semiconductor technology.
Summary of the invention
The invention relates to a kind of semiconductor structure of making the method for metal silicide and using it, be to form the consistent grid of elevation of water in the memory cell array zone with peripheral circuit area, can't form smoothly metal silicide with the grid of avoiding being positioned at the lower region because dielectric layer covers.
According to an aspect of the present invention, propose a kind of method of making metal silicide, comprise the following steps.One substrate is provided, and substrate has a first area and a second area.Form a silicon layer on substrate.Carry out a flatening process, so that silicon layer has a flat surfaces.Remove the part silicon layer, to form a plurality of first grids in the first area and to form a plurality of second grids at second area, the height of these a plurality of first grids is greater than the height of these a plurality of second grids, and these a plurality of first grids have the consistent upper surface of elevation of water with these a plurality of second grids.Form a dielectric layer on substrate, dielectric layer covers these a plurality of first grids and these a plurality of second grids, and manifests the upper surface of these a plurality of first grids and these a plurality of second grids.Form a metal silicide in the upper surface of these a plurality of first grids with these a plurality of second grids.
According to a further aspect in the invention, propose a kind of semiconductor structure, comprise a substrate, a silicon layer, a dielectric layer and a metal silicide.Substrate has a first area and a second area.Silicon layer has a plurality of first grids that are positioned at the first area and a plurality of second grids that are positioned at second area, wherein the height of these a plurality of first grids is greater than the height of these a plurality of second grids, and these a plurality of first grids have the consistent upper surface of elevation of water with these a plurality of second grids.Dielectric layer is formed on the substrate, and dielectric layer manifests the upper surface of these a plurality of first grids and these a plurality of second grids.Metal silicide is formed at respectively the upper surface of these a plurality of first grids and these a plurality of second grids.
For there is better understanding above-mentioned and other aspect of the present invention, embodiment cited below particularly, and cooperate appended graphicly, be described in detail below:
Description of drawings
Figure 1A～Fig. 1 F illustrates according to the method for the making metal silicide of one embodiment of the invention and uses the schematic diagram of its semiconductor structure.
Fig. 2 A～Fig. 2 F illustrates according to the method for the making metal silicide of one embodiment of the invention and uses the schematic diagram of its semiconductor structure.
[main element symbol description]
100,200: substrate
101,201: the first area
102,202: second area
103,203: join domain in local
104: inclined surface
110,110a, 210,210a: silicon layer
111,211: flat surfaces
120,220: upper surface
121,221: first grid
122,222: second grid
123,223: the three grids
130,230: dielectric layer
140,240: metal silicide
W, X, X1, Y: highly
212: polysilicon layer
214,214a: amorphous silicon layer
Embodiment
The method of making metal silicide of the present invention and use its semiconductor structure is the silicon layer that deposit thickness is increased on substrate, and the recycling flatening process carries out thinning, so that silicon layer has the consistent flat surfaces of elevation of water.After this silicon layer is patterned, form consistent first grid and the second grid of elevation of water.Therefore, the grid on memory cell array zone and peripheral circuit area in follow-up thermal process, all can form metal silicide smoothly, to reduce the sheet resistor value of grid.
Below be to propose various embodiment to be elaborated, embodiment in order to as the example explanation, is not the scope in order to limit wish protection of the present invention only.
The first embodiment
Please refer to Figure 1A～Fig. 1 F, it illustrates according to the method for the making metal silicide of one embodiment of the invention and uses the schematic diagram of its semiconductor structure.The method comprises the following steps at least.One substrate 100 is provided, and substrate 100 has a first area 101 and a second area 102.Form a silicon layer 110 on substrate 100.Carry out a flatening process, so that silicon layer 110 has a flat surfaces 111.Remove part silicon layer 110,101 to form a plurality of first grids 121 and to form a plurality of second grids 122 at second area 102 in the first area.The height X+Y of first grid 121 is greater than the height Y of second grid 122, and first grid 121 has the consistent upper surface of elevation of water 120 with second grid 122.Form a dielectric layer 130 on substrate 100, dielectric layer 130 covers this a plurality of first grids 121 and second grid 122, and manifests the upper surface 120 of these a plurality of first grids 121 and second grid 122.Form a metal silicide 140 in the upper surface 120 of these a plurality of first grids 121 with second grid 122.
In Figure 1A, substrate 100 has a first area 101 and a second area 102.Silicon layer 110 is formed on the substrate 100, and equal thickness ground covers first area 101 and second area 102.The first area 101 of substrate 100 and second area 102 have different height with respect to the bottom surface of substrate 100, so that obviously have a difference in height X between first area 101 and the second area 102.In addition, substrate 100 for example has an inclined surface 104 and is arranged in a local join domain 103, so that join domain 103 favours between first area 101 and the second area 102 in local.
In the present embodiment, substrate 100 is for being rich in the Semiconductor substrate of silicon, silicon layer 110 for example is with the formed polysilicon layer of chemical vapour deposition technique, it has the height W greater than predetermined height of deposition X+Y, wherein X is the difference in height of first area 101 and second area 102, and Y is the ideal height of second grid 122.First area 101 for example is the memory cell array zone, and second area 102 for example is peripheral circuit area.In another embodiment, first area 101 for example is peripheral circuit area, and second area 102 for example is the memory cell array zone.In the memory cell array zone, has active element (for example Memory Storage Unit), in order to storage data.In peripheral circuit area, have logical block (for example transistor switch), in order to read and the computing store memory cell in the data that store.In follow-up technique, can be respectively as the grid of Memory Storage Unit and the grid of logical block through the silicon layer 110 after flatening process and the Patternized technique.
Please refer to Figure 1B, carry out the flatening process such as chemico-mechanical polishing, so that silicon layer 110a has flat surfaces 111.At this moment, the silicon layer 110a after the thinning is X+Y with respect to the height of first area 101, and is Y with respect to the height of second area 102.Then, please refer to Fig. 1 C, remove part silicon layer 110a by techniques such as photoetching and anisotropic etchings, 101 to form a plurality of first grids 121 and to form a plurality of second grids 122 at second area 102 in the first area.The height of first grid 121 is X+Y, and the height of second grid 122 is Y, thus the height of first grid 121 greater than the height of second grid 122, and first grid 121 has the consistent upper surface of elevation of water 120 with second grid 122.In the technique of Fig. 1 C, more can form one the 3rd grid 123 in local on the join domain 103, and first grid 121, second grid 122 has the consistent upper surface of elevation of water 120 with the 3rd grid 123.In the present embodiment, first grid 121, second grid 122 for example are the grid of the identical transistor of polarity (for example N-type metal oxide semiconductor transistor) with the 3rd grid 123, or with the transistorized grid of the opposite polarity P-type mos of N-type metal oxide semiconductor transistor.In one embodiment, the local connection wire that the 3rd grid 123 also can be positioned between first grid 121 and the second grid 122 replaces, and is not defined as transistorized grid.
Please refer to Fig. 1 D and Fig. 1 E, form a dielectric layer 130 on substrate 100, dielectric layer 130 is filled in the space between adjacent two grids, and cover the upper surface 120 of first grid 121, second grid 122 and the 3rd grid 123.In Fig. 1 E, dielectric layer 130 can carry out thinning by flatening process such as chemico-mechanical polishings, so that dielectric layer 130 is consistent with the elevation of water of grid 121-123, and manifests the upper surface 120 of first grid 121, second grid 122 and the 3rd grid 123.
Then, please refer to Fig. 1 F, form respectively a metal silicide 140 in the upper surface 120 of first grid 121, second grid 122 and the 3rd grid 123.Metal silicide 140 is in the process of carrying out thermal process, and for example Celsius 960 spend, and metal level rearranges metallic and silicon wafer with the silicon layer 110a high temperature hot melt of the thinning of vicinity and forms.The step that forms self-aligned metal silicate 140 in Fig. 1 F is as follows.At first, form a metal level (not illustrating) on the silicon layer 110a and dielectric layer 130 of thinning with chemical vapour deposition technique or physical vaporous deposition.Carry out a thermal process, annealing process for example is so that metal level and silicon layer 110a cross reaction and form metal silicide 140.Then, remove not part metals layer with silicon layer 110a reaction.Metal silicide 140 for example is tungsten silicide (tungsten silicide), molybdenum silicide (molybdenum silicide), cobalt silicide (cobalt silicide), titanium silicide (titanium silicide), nickle silicide (nickel silicide) or other fire resistance metal silicides (refractory metal silicde), to reduce the sheet resistor value of first grid 121, second grid 122 and the 3rd grid 123.
The second embodiment
Please refer to Fig. 2 A～Fig. 2 F, it illustrates according to the method for the making metal silicide of one embodiment of the invention and uses the schematic diagram of its semiconductor structure.The present embodiment and the first embodiment difference are: the step that forms planarization silicon layer 210 among silicon layer 210 and Fig. 2 B among Fig. 2 A.As for techniques such as the patterning silicon layer 210a among Fig. 2 C～Fig. 2 F, formation dielectric layer 230 and planarization dielectric layer 230, formation metal silicides 240, all the technique with above-mentioned the first embodiment is identical, does not repeat them here.
Please refer to Fig. 2 A, silicon layer 210 comprises with the polysilicon layer 212 of chemical vapour deposition technique formation the first height Y and the amorphous silicon layer 214 of the second height X1, wherein the second height X1 is greater than the difference in height X of (or equaling) first area 201 with second area 202, and the first height Y is the ideal height of second grid 222, so silicon layer 210 has the total height W greater than predetermined height of deposition X+Y.
Please refer to Fig. 2 B, carry out the flatening process such as chemico-mechanical polishing, so that silicon layer 210 has flat surfaces 211.At this moment, the silicon layer 210a after the thinning is X+Y with respect to the height of first area 201, and is Y with respect to the height of second area 202.In the present embodiment, the amorphous silicon layer 214 that is positioned at second area 202 is removed and manifests the polysilicon layer 212 of below, so that the amorphous silicon layer 214a that is not removed among Fig. 2 B trims polysilicon layer 212, and has the consistent flat surfaces of elevation of water 211 with polysilicon layer 212.Can be used as the suspension layer of etching or chemico-mechanical polishing silicon layer 210 owing to being positioned at the polysilicon layer 212 of amorphous silicon layer 214 belows, therefore can accurately control the degree of depth of silicon layer 210 etchings.
In follow-up Fig. 2 B, before forming metal silicide 240, amorphous silicon layer 214a can be by heating, for example about 600 degree Celsius, makes its recrystallization and converts another polysilicon layer to.Because polysilicon layer has better electron mobility with respect to amorphous silicon layer 214a, therefore can improve the switching capability of Memory Storage Unit and the driving force of logical block.
In the present embodiment, because silicon layer 210a patterned (with reference to Fig. 2 C) afterwards, first grid 221, second grid 222 form the consistent upper surface 220 of elevation of water with the 3rd grid 223.Therefore, grid in first area 201 (for example memory cell array zone), second area 202 (for example peripheral circuit area) and part on the join domain 203, in follow-up thermal process, all can form smoothly metal silicide 240, to reduce the sheet resistor value of grid.
In sum, although the present invention discloses as above with preferred embodiment, so it is not to limit the present invention.The persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is when looking being as the criterion that the claim scope of enclosing defines.
Claims (10)
1. method of making metal silicide comprises:
One substrate is provided, and this substrate has a first area and a second area;
Form a silicon layer on this substrate;
Carry out a flatening process, so that this silicon layer has a flat surfaces;
Remove this silicon layer of part, to form a plurality of first grids in this first area and to form a plurality of second grids at this second area, the height of these a plurality of first grids is greater than the height of these a plurality of second grids, and these a plurality of first grids have the consistent upper surface of elevation of water with these a plurality of second grids;
Form a dielectric layer on this substrate, this dielectric layer covers these a plurality of first grids and these a plurality of second grids, and manifests the upper surface of these a plurality of first grids and these a plurality of second grids; And
Form a metal silicide in the upper surface of these a plurality of first grids with these a plurality of second grids.
2. the method for making metal silicide according to claim 1, wherein this first area and this second area are respectively memory cell array zone and peripheral circuit area.
3. the method for making metal silicide according to claim 1, wherein this substrate has an inclined surface and is arranged in a local join domain, join domain is between this first area and this second area in this part, this first area of this substrate has a difference in height with respect to this second area, and these a plurality of first grids are formed on this highly lower first area, and these a plurality of second grids are formed on this highly higher second area.
4. the method for making metal silicide according to claim 1, the step that wherein forms this silicon layer and this silicon layer of planarization comprises:
Form a polysilicon layer on this substrate;
Form an amorphous silicon layer on this polysilicon layer; And
This amorphous silicon layer of planarization so that this amorphous silicon layer trims this polysilicon layer, and has a flat surfaces with this polysilicon layer.
5. the method for making metal silicide according to claim 4, wherein after this amorphous silicon layer of planarization, more comprise this amorphous silicon layer of heating to recrystallization temperature to form another polysilicon layer.
6. the method for making metal silicide according to claim 1 wherein forms after this dielectric layer, more comprises this dielectric layer of planarization.
7. the method for making metal silicide according to claim 1, the step that wherein forms this metal silicide comprises:
Form a metal level on this silicon layer and this dielectric layer;
Carry out a thermal process, form this metal silicide so that this metal level and this silicon layer react; And
Remove not this metal level of part with this silicon layer reaction.
8. semiconductor structure comprises:
One substrate, this substrate have a first area and a second area;
One silicon layer, have a plurality of first grids that are positioned at this first area and a plurality of second grids that are positioned at this second area, wherein the height of these a plurality of first grids is greater than the height of these a plurality of second grids, and these a plurality of first grids have the consistent upper surface of elevation of water with these a plurality of second grids;
One dielectric layer is formed on this substrate, and this dielectric layer manifests the upper surface of these a plurality of first grids and these a plurality of second grids; And
One metal silicide is formed at respectively the upper surface of these a plurality of first grids and these a plurality of second grids.
9. semiconductor structure according to claim 8, wherein this first area and this second area are respectively memory cell array zone and peripheral circuit area, this silicon layer is at least one polysilicon layer or is combined by a polysilicon layer and an amorphous silicon layer, and these a plurality of first grids are respectively the grid of Memory Storage Unit and the grid of logical block with these a plurality of second grids.
10. semiconductor structure according to claim 8, wherein this substrate has an inclined surface and is arranged in a local join domain, join domain is between this first area and this second area in this part, this silicon layer more comprises one the 3rd grid, be arranged in this part join domain, this first area of this substrate has a difference in height with respect to this second area, and these a plurality of first grids are formed on this highly lower first area, and these a plurality of second grids are formed on this highly higher second area.
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| JPH02172253A (en) * | 1988-12-24 | 1990-07-03 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
| US5828120A (en) * | 1996-02-23 | 1998-10-27 | Nippon Steel Corporation | Semiconductor device and production method thereof |
| TW424303B (en) * | 1999-06-17 | 2001-03-01 | United Microelectronics Corp | Manufacturing method for dual-gate CMOS device |
| US6541357B1 (en) * | 2001-12-04 | 2003-04-01 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| US20100167490A1 (en) * | 2008-12-31 | 2010-07-01 | Jong-Wan Choi | Method of Fabricating Flash Memory Device |
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- 2012-03-09 CN CN201210061510.0A patent/CN103311107B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02172253A (en) * | 1988-12-24 | 1990-07-03 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
| US5828120A (en) * | 1996-02-23 | 1998-10-27 | Nippon Steel Corporation | Semiconductor device and production method thereof |
| TW424303B (en) * | 1999-06-17 | 2001-03-01 | United Microelectronics Corp | Manufacturing method for dual-gate CMOS device |
| US6541357B1 (en) * | 2001-12-04 | 2003-04-01 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| US20100167490A1 (en) * | 2008-12-31 | 2010-07-01 | Jong-Wan Choi | Method of Fabricating Flash Memory Device |
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