TWI463567B - Method for producing metal telluride and semiconductor structure using same - Google Patents

Description

Method for producing metal telluride and semiconductor structure using same

The present invention relates to a semiconductor process and structure, and more particularly to a method of fabricating a metal telluride and a semiconductor structure using the same.

As the degree of integration of semiconductor components increases, the pattern and linewidth in the device also shrinks, resulting in increased contact resistance between the gate and the conductor in the device, resulting in a large resistance-capacitance delay (RC Delay), which in turn affects Component operating speed. Since the metal halide has a lower resistance than polysilicon and its thermal stability is higher than that of a general interconnect material, a metal telluride is formed on the gate to reduce the resistance between the gate and the metal interconnect. value.

In the conventional process of forming a metal telluride, after a gate (for example, a polysilicon layer) is formed on a semiconductor wafer, the gate deuteration process includes forming a metal layer on the polysilicon layer, followed by an annealing process to form a metal telluride. On the gate.

In the current gate fabrication of peripheral circuit regions, metal telluride is also required to reduce the resistance between the wires and the gate. However, in the conventional self-aligned metal telluride process, if a metal halide is formed on a part of the medium, a relatively complicated procedure must be performed to form a metal halide on the desired region, especially when the cell array region is formed. When the height of the horizontal plane is different from that of the peripheral circuit area, the difficulty of the process execution is further improved. In the current era of high efficiency, it is necessary to improve the traditional practices to improve the efficiency of semiconductor manufacturing.

The invention relates to a method for fabricating a metal telluride and a semiconductor structure using the same, which form a gate with a uniform horizontal level on a cell array region and a peripheral circuit region, so as to prevent the gate in the lower region from being dielectrically insulated. The layer is shielded and the metal halide cannot be formed smoothly.

According to one aspect of the invention, a method of making a metal telluride is provided, comprising the following steps. A substrate is provided, the substrate having a first region and a second region. A layer of germanium is formed on the substrate. A planarization process is performed to provide a flat surface to the tantalum layer. Removing a portion of the germanium layer to form a plurality of first gates in the first region and a plurality of second gates in the second region, the heights of the first gates being greater than the heights of the second gates, and The first gates and the second gates have an upper surface having a horizontal height. Forming a dielectric layer on the substrate, the dielectric layer covering the first gates and the second gates, and revealing the first gates and the upper surfaces of the second gates. A metal germanide is formed on the upper surface of the first gate and the second gates.

In accordance with another aspect of the invention, a semiconductor structure is provided comprising a substrate, a germanium layer, a dielectric layer, and a metal germanide. The substrate has a first area and a second area. The 矽 layer has a plurality of first gates located in the first region and a plurality of second gates located in the second region, wherein the heights of the first gates are greater than the heights of the second gates, and the The first gates and the second gates have an upper surface having a horizontal height. The dielectric layer is formed on the substrate, and the dielectric layer exposes the first gate and the upper surfaces of the second gates. Metal halides are formed on the upper surfaces of the first gates and the second gates, respectively.

In order to provide a better understanding of the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings

The method for fabricating a metal telluride according to the present invention and the semiconductor structure using the same are to deposit a germanium layer having a higher thickness on a substrate, and then thinning it by a planarization process so that the germanium layer has a flat surface with a uniform horizontal height. After the germanium layer is patterned, a first gate and a second gate having a uniform height in the horizontal plane are formed. Therefore, in the gate array region and the gate electrode region, the metal germanide can be smoothly formed in the subsequent thermal process to reduce the sheet resistance of the gate.

The following is a detailed description of various embodiments, which are intended to be illustrative only and not to limit the scope of the invention.

First embodiment

Please refer to FIGS. 1A-1F for a schematic diagram of a method for fabricating a metal telluride and a semiconductor structure using the same according to an embodiment of the invention. This method includes at least the following steps. A substrate 100 is provided. The substrate 100 has a first region 101 and a second region 102. A layer of germanium 110 is formed on the substrate 100. A planarization process is performed to provide the germanium layer 110 with a flat surface 111. A portion of the germanium layer 110 is removed to form a plurality of first gate electrodes 121 in the first region 101 and a plurality of second gate electrodes 122 in the second region 102. The height X+Y of the first gate 121 is greater than the height Y of the second gate 122, and the first gate 121 and the second gate 122 have an upper surface 120 with a horizontal height. Forming a dielectric layer 130 on the substrate 100, the dielectric layer 130 The first gate 121 and the second gate 122 are covered, and the first surface 121 of the first gate 121 and the second gate 122 are exposed. A metal germanide 140 is formed on the upper surface 120 of the first gate 121 and the second gate 122.

In FIG. 1A, the substrate 100 has a first region 101 and a second region 102. The germanium layer 110 is formed on the substrate 100 and covers the first region 101 and the second region 102 in equal thickness. The first region 101 and the second region 102 of the substrate 100 have different heights with respect to the bottom surface of the substrate 100 such that there is a significant height difference X between the first region 101 and the second region 102. Further, the substrate 100 has, for example, an inclined surface 104 located in a partial inner connecting region 103 such that the partial inner connecting region 103 is inclined between the first region 101 and the second region 102.

In the present embodiment, the substrate 100 is a germanium-rich semiconductor substrate, and the germanium layer 110 is, for example, a polycrystalline germanium layer formed by chemical vapor deposition, having a height W greater than a predetermined deposition height X+Y, where X is The height difference between the first region 101 and the second region 102, and Y is the ideal height of the second gate 122. The first region 101 is, for example, a cell array region, and the second region 102 is, for example, a peripheral circuit region. In another embodiment, the first region 101 is, for example, a peripheral circuit region, and the second region 102 is, for example, a cell array region. In the cell array region, there are active components (such as memory cells) for storing data. A logic unit (such as a transistor switch) is provided in the peripheral circuit area for reading and calculating data stored in the memory unit cell. In the subsequent process, the germanium layer 110 after the planarization process and the patterning process can be used as the gate of the memory cell and the gate of the logic cell, respectively.

Please refer to Figure 1B for a flattening process such as chemical mechanical polishing. The crucible layer 110a has a flat surface 111. At this time, the height of the thinned layer 110a with respect to the first region 101 is X+Y, and the height with respect to the second region 102 is Y. Next, referring to FIG. 1C, a portion of the germanium layer 110a is removed by a process such as lithography and anisotropic etching to form a plurality of first gates 121 in the first region 101 and a plurality of regions in the second region 102. The second gate 122. The height of the first gate 121 is X+Y, and the height of the second gate 122 is Y, so the height of the first gate 121 is greater than the height of the second gate 122, and the first gate 121 and the second gate The pole 122 has an upper surface 120 that is uniform in height. In the process of FIG. 1C, a third gate 123 is formed on the local interconnect region 103, and the first gate 121, the second gate 122, and the third gate 123 have an upper surface having a uniform horizontal height. 120. In this embodiment, the first gate 121, the second gate 122, and the third gate 123 are, for example, gates of transistors of the same polarity (for example, N-type MOS transistors), or N-type gold. The gate of a P-type MOS transistor having the opposite polarity of the oxygen semiconductor. In one embodiment, the third gate 123 can also be replaced by a local inner connecting line between the first gate 121 and the second gate 122, and is not limited to the gate of the transistor.

Referring to FIGS. 1D and 1E, a dielectric layer 130 is formed on the substrate 100 such that the dielectric layer 130 is filled in the gap between the adjacent two gates and covers the first gate 121 and the second gate. 122 and the upper surface 123 of the third gate 123. In FIG. 1E, the dielectric layer 130 can be thinned by a planarization process such as chemical mechanical polishing, so that the dielectric layer 130 and the gates 121-123 have the same height level, and the first gate 121 is exposed. The second gate 122 and the upper surface 123 of the third gate 123.

Next, please refer to FIG. 1F to form a metal telluride 140, respectively. The first gate 121, the second gate 122 and the third gate 123 are on the upper surface 120. The metal telluride 140 is formed during the thermal process, for example, 960 degrees Celsius, and the metal layer is thermally fused with the adjacent thinned ruthenium layer 110a to realign the metal particles and the twins. The steps of forming the self-aligned metal telluride 140 in FIG. 1F are as follows. First, a metal layer (not shown) is formed on the thinned germanium layer 110a and the dielectric layer 130 by chemical vapor deposition or physical vapor deposition. A thermal process, such as an annealing process, is performed to cause the metal layer to interact with the germanium layer 110a to form the metal germanide 140. Next, a portion of the metal layer that does not react with the ruthenium layer 110a is removed. The metal telluride 140 is, for example, tungsten silicide, molybdenum silicide, cobalt silicide, titanium silicide, nickel silicide or other refractory metal. The chip resistance value of the first gate 121, the second gate 122, and the third gate 123 is reduced.

Second embodiment

Please refer to FIGS. 2A-2F for a schematic diagram of a method of fabricating a metal telluride and a semiconductor structure using the same according to an embodiment of the invention. This embodiment differs from the first embodiment in the steps of forming the germanium layer 210 and the planarizing germanium layer 210 in FIG. 2B in FIG. 2A. The process of patterning the germanium layer 210a, forming the dielectric layer 230, the planarizing dielectric layer 230, and forming the metal germanide 240 in the 2C~2F drawings are the same as those in the first embodiment described above, and are no longer Narration.

Referring to FIG. 2A, the ruthenium layer 210 includes a chemical vapor deposition method. a polycrystalline germanium layer 212 of a first height Y and an amorphous germanium layer 214 of a second height X1, wherein the second height X1 is greater than (or equal to) a height difference X between the first region 201 and the second region 202, and the first height Y It is the ideal height of the second gate 222, and thus the ruthenium layer 210 has a total height W greater than the predetermined deposition height X+Y.

Referring to FIG. 2B, a planarization process such as chemical mechanical polishing is performed so that the germanium layer 210 has a flat surface 211. At this time, the height of the thinned layer 210a with respect to the first region 201 is X+Y, and the height with respect to the second region 202 is Y. In the present embodiment, the amorphous germanium layer 214 located in the second region 202 is removed to expose the underlying polysilicon layer 212, such that the amorphous germanium layer 214a not removed in FIG. 2B is aligned with the poly germanium layer 212. And the polycrystalline germanium layer 212 has a flat surface 211 with a horizontal height. Since the polysilicon layer 212 under the amorphous germanium layer 214 can serve as a stop layer for etching or chemical mechanical polishing of the germanium layer 210, the depth of etching of the germanium layer 210 can be precisely controlled.

In the subsequent FIG. 2B, before the formation of the metal telluride 240, the amorphous germanium layer 214a can be converted into another polysilicon layer by heating, for example, about 600 degrees Celsius. Since the polysilicon layer has a better electron mobility than the amorphous germanium layer 214a, the switching ability of the memory cell and the driving ability of the logic cell can be improved.

In the present embodiment, after the germanium layer 210a is patterned (refer to FIG. 2C), the first gate 221, the second gate 222, and the third gate 223 form an upper surface 220 having a horizontal height. Therefore, the gates on the first region 201 (eg, the cell array region), the second region 202 (eg, the peripheral circuit region), and the local interconnect region 203 can be used in subsequent thermal processes. The metal halide 240 is formed smoothly to reduce the sheet resistance of the gate.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100, 200‧‧‧ base

101, 201‧‧‧ first area

102, 202‧‧‧ Second area

103, 203‧‧‧Local connection area

104‧‧‧Sloping surface

110, 110a, 210, 210a‧‧‧ layers

111, 211‧‧‧ flat surface

120, 220‧‧‧ upper surface

121, 221‧‧‧ first gate

122, 222‧‧‧ second gate

123, 223‧‧‧ third gate

130, 230‧‧‧ dielectric layer

140, 240‧‧‧Metal Telluride

W, X, X1, Y‧‧‧ height

212‧‧‧Polysilicon layer

214, 214a‧‧‧ amorphous layer

1A to 1F are schematic views showing a method of fabricating a metal telluride and a semiconductor structure using the same according to an embodiment of the present invention.

2A-2F are schematic views showing a method of fabricating a metal telluride and a semiconductor structure using the same according to an embodiment of the invention.

100‧‧‧Base

120‧‧‧ upper surface

121‧‧‧First Gate

122‧‧‧second gate

123‧‧‧third gate

130‧‧‧Dielectric layer

140‧‧‧Metal Telluride

X, Y‧‧‧ height

Claims (8)

A method of fabricating a metal telluride, comprising: providing a substrate having a first region and a second region; forming a polysilicon layer on the substrate; forming an amorphous germanium layer on the polysilicon layer; planarizing The amorphous germanium layer is such that the amorphous germanium layer is aligned with the polysilicon layer and has a flat surface with the polysilicon layer, wherein the polycrystalline germanium layer and the amorphous germanium layer are formed on the first region of the substrate; The polysilicon layer and a portion of the amorphous germanium layer to form a plurality of first gates in the first region and a plurality of second gates in the second region, the first gates having a height greater than the plurality a height of the second gate, and the first gates and the second gates have an upper surface having a horizontal height, wherein the first gates are composed of the polysilicon layer and the amorphous layer; a dielectric layer is disposed on the substrate, the dielectric layer covers the first gates and the second gates, and exposes the first gates and the upper surfaces of the second gates; a metal telluride to the first gates The plurality of second gate over the surface. The method of claim 1, wherein the first region and the second region are a cell array region and a peripheral circuit region, respectively. The method of claim 1, wherein the substrate has an inclined surface located in a partial inner connecting region, the partial inner connecting region being located between the first region and the second region, the base of the substrate A region has a height difference with respect to the second region, and the first gates are formed on the first region having a lower height, and the second gates are formed on the second region having a higher height. The method of claim 1, wherein after planarizing the amorphous germanium layer, further comprising heating the amorphous germanium layer to a recrystallization temperature to form another polysilicon layer. The method of claim 1, wherein after forming the dielectric layer, further comprising planarizing the dielectric layer. The method of claim 1, wherein the step of forming the metal halide comprises: forming a metal layer on the germanium layer and the dielectric layer; performing a thermal process to cause the metal layer and the germanium The layer reacts to form the metal halide; and removes a portion of the metal layer that does not react with the layer. A semiconductor structure comprising: a substrate having a first region and a second region, wherein the substrate has an inclined surface in a partial inner connection region, the local inner connection region being located in the first region and the first Between the two regions; a layer having a plurality of first gates, a plurality of second gates, and a third gate, wherein the first gates are located in the first region and the second gates Positioned in the second region, the third gate is in the local interconnect region and has a horizontal height with the first gates and the second gates a uniform upper surface, the height of the first gates is greater than the height of the second gates, the first region of the substrate has a height difference with respect to the second region, and the first gates are formed at The second gate is formed on the second region having a higher height, and the bottom portion of the third gate is the inclined surface; a dielectric layer is formed on the substrate And the dielectric layer exposes the first gate and the upper surfaces of the second gates; and a metal halide is formed on the first gates and the second gates respectively surface. The semiconductor structure of claim 7, wherein the first region and the second region are a cell array region and a peripheral circuit region, respectively, the germanium layer is at least one polysilicon layer or a polysilicon layer and a non- The germanium layers are combined, and the first gates and the second gates are respectively a gate of the memory cell and a gate of the logic unit.