4 2185 2 A7 _B7 五、發明説明（） 5-1發明領域： (請先閲讀背面之注意事項再填寫本頁) 本發明是有關一種積體電路之金屬連線的製造方法，特別 是有關形成深接觸孔之内連線的方法。 心5-2發明背景： 積體電路的製造程序，是先形成元件在矽晶圓之上，然後， 沉積數層的介電層在元件之上，於介電層之中製造元件的金屬 接觸與元件之間的金屬連線，完成積體電路的製造。 通常積體電路的金屬化製程包括形成元件主動區的金屬接 觸與積體電路的金屬連線，其中金屬連線的製作是屬於較後 端的製程，以下將說明積體電路之金屬連線的習知方法，並 參閱第一圖至第六圖。 經濟部智慧財產局員工消費合作杜印製 請參閱第一圖，在基板100之上製造積體電路或者是半導 體元件，然後沉積第一介電層110覆蓋在基板100上，在第 一介電層110之中形成兩個接觸孔，暴露出基板100的表面。 若第一介電層110是積體電路的内介電層（interlayer dielectric layer，ILD)，第一介電層110的接觸孔是作為元件的金屬接觸 窗；若第一介電層110是積體電路的金屬間介電層（intermetal die丨ectric layer，IMD)，則接觸孔是作為金屬線的接觸窗、 請參閱第二圖，沉積一第一阻障層115覆蓋在第一介電層 110之接觸孔的表面，然後沈積鎢金屬層120覆蓋在第一阻障 層115之上，填入第一介電層110的接觸孔中，並覆蓋在第4 2185 2 A7 _B7 V. Description of the invention () 5-1 Field of invention: (Please read the precautions on the back before filling out this page) The present invention relates to a method for manufacturing metal wiring of integrated circuits, especially related to the formation of Method for deep contact hole interconnection. Heart 5-2 Background of the Invention: The manufacturing process of an integrated circuit is to first form an element on a silicon wafer, and then deposit several layers of dielectric layer on the element, and make metal contacts of the element in the dielectric layer. The metal connection with the component completes the manufacture of the integrated circuit. Generally, the metallization process of an integrated circuit includes forming a metal contact of the active area of the component and a metal connection of the integrated circuit. The production of the metal connection is a relatively backward process. The following describes the practice of the metal connection of the integrated circuit. Know the method, and refer to the first to sixth figures. Please refer to the first figure for the consumer cooperation of the Intellectual Property Bureau of the Ministry of Economic Affairs. Please refer to the first figure to fabricate integrated circuits or semiconductor components on the substrate 100, and then deposit a first dielectric layer 110 on the substrate 100 to cover the first dielectric layer. Two contact holes are formed in the layer 110 to expose the surface of the substrate 100. If the first dielectric layer 110 is an interlayer dielectric layer (ILD) of an integrated circuit, the contact hole of the first dielectric layer 110 is a metal contact window as an element; if the first dielectric layer 110 is an integrated circuit Intermetal die layer (IMD) of the bulk circuit, the contact hole is used as a contact window for the metal line. Please refer to the second figure, a first barrier layer 115 is deposited to cover the first dielectric layer. The surface of the contact hole of 110 is then deposited with a tungsten metal layer 120 overlying the first barrier layer 115, filled in the contact hole of the first dielectric layer 110, and overlying the first dielectric layer 110.
本紙張尺度適用中國國家標隼（CNS) A4規格（210X297公釐J 421852 A7 -^--- 咖ί月7 / B7 五、發明説明（） 經濟部智慧財產局員工消費合作社印製 -介電層11G的表面，通常是利用化學氣相沉㈣程沉積鶴 金屬材料。在-較佳實施例之中’第一阻障層115的組成材 料為鈦金屬層與氮化鈦層，在第一阻障層115中的鈦金屬層 厚度係介於2GG到15GG埃之間，氮化鈦層的厚度係介於3〇〇 到2000埃之間。填入接觸孔的鎢金屬材料，成為金屬插塞(』 plug)，然後進行回姓刻處理(etch_back)，對鎢金屬層i2〇進行 蚀刻製程，去除在第一介電層110表面之上的鎢金屬層12〇, 在第-介電層110之上預留第-阻障層115，作為金屬線與第 一介電層110之間的黏著層。在触刻製程之後，形成與第— 介電層110同樣平坦高度的金屬插塞，如第三圖所示。 請參閱第四圖，於第一介電層11〇與鎮金屬層12〇所形成 金屬插塞的表面’定義金屬線125連接金屬插塞，金屬線125 通常是積趙電路的内連線(interconnect line)，於形成金屬插塞 之後須另外形成内連線。在金屬線125之後形成抗反射層126， 組成材料為氮化鈦材料，其厚度為1〇〇到1〇〇〇埃之間。金屬 線125的組成材料是在鋁金屬，並於鋁金屬中加入少量的矽 與銅材料’形成鋁矽銅金屬線(metal Al-Si-Cu line)。 請參閲第五圖，均勻的沉積第二介電層130在第一介電層 110之上’並覆蓋住抗反射層126。在第一介電層110中所形 成金屬插塞的其中之一，是預備作深接觸孔的金屬接觸，在 此金厲插塞之上，第二介電層13〇中形成一接觸孔，暴露出 金屬插塞的頂面。在抗反射層126之上的第二介電層130之 中形成接觸孔，作為金屬線125的金屬接觸孔。 請參閱第六圖，沈積第二阻障層135覆蓋在第二介電層13〇 本紙張从i4财關轉牟（CNS )八4祕（21QX297公羡） ----------^---^----tr------0 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 A7 __— —-__B7 五、發明説明（） 的表面’並覆蓋在金屬線125與鎮金屬f 12〇之上。在一較 佳實施例之中’第—阻障層135的組成材料為鈦金屬層與氮 化欽層’第二阻障層135的厚度相同於第一阻㈣ιι5的厚 度，第二介電層13〇的接觸孔中覆蓋形成鎢金屬插塞⑽， 連接第一介電層110中的鎢金屬層12〇。 以上所敘述的製程，為在積體電路之深接觸孔中的金屬連 線製造方法，於基板上沉積第一介電層，並具有兩個接觸孔， 然後形成金属插塞填人接觸孔中，再於其中—個金層插塞上 形成㈣銅金屬線，當作積體電路的内連線，職沉積第二 介電層在第一介電層之上，並形成一個接觸孔位於另外—個 金屬插塞之上，填入鎢金屬材料於第二介電層的接觸孔中， 連接第一介電層的金屬插塞，完成積體電路深接觸孔的製造 過程。 可是，在上述的製程中，形成深接觸孔必須分為兩個階段 來進行，於形成第一介電層的金屬插塞之後，必須形成積體 電路的内連線，再形成第二介電層的金屬插塞’於是在形成 積體電路之内連線的過程，需要再一次沉積鋁金屬材料’然 後利用微影與蝕刻技術，在鋁金屬層上定義金屬線圖案。所 以，定義金屬線的過程相當複雜’需要利用微影製程，將金 屬線對準金屬插塞的頂面，以形成良好的金屬接觸。而且， 於形成第二介電層的接觸孔時，也需要使用微影製程，將接 觸孔對準第一介電層的金屬插塞，才能形成具有良好金屬接 觸的深接觸孔。這些利用微影製程對準金屬插塞的過程是相 當複雜’若於微影製程中有若干誤差，便會發生對準偏移 本紙張尺度通用中國國家榇準（CNS ) Α4ίΙ格（210X297公釐） ..----^------ΐτ------Κ (請先聞讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 4 2185 2 at B7 五、發明説明（） (misalign)，使得金屬連線不能良好連結。 因此，需要一種簡單的深接觸孔的内連線製程，能夠避免 於形成積體電路之内連線的複雜製程，並且能夠輕易形成深 接觸孔的金屬接觸。 c 5-3發明目的及概述： 本發明係揭露一種積體電路之深接觸孔的製造方法，提供 一基板，在基板上製造積體電路或者是半導體元件，然後沉積 第一介電層覆蓋在基板的表面，於第一介電層之中形成兩個接 觸孔，作為積體電路之接觸窗。 然後，沉積鎢金屬層填入接觸孔，以及覆蓋在第一介電層 的表面。形成鎢金屬層之後，進行蝕刻製程，蝕刻鎢金屬層， 以形成接觸孔的金屬插塞，在金屬插塞的頂端形成鎢金屬島或 者是鎢金屬線，其中鎢金屬線是積體電路的内連線，鎢金屬島 是預留深接觸孔的接觸部份。 然後，沉積第二介電層覆蓋在第一介電層與鎢金屬層的表 面，在鎢金屬島的上方，形成一接觸孔，最後形成金屬插塞於 第二介電層的接觸孔中，完成積體電路之深接觸孔的金屬接 觸。 5-4圖式簡單說明： 本發明的許多發明目的與優點，將會因為參考下列的詳細 說明，變得更容易被鑑賞與瞭解，同時參酌下列的圖式加以說 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部智慧財產局員工消費合作社印製 42185 2 A7 B7五、發明説明（） 明，其中： 第一圊係顯示習知技術之中基板的剖面示意圖，在基板的表 面覆蓋一層積體電路之介電層，在介電層中形成兩個 接觸孔； 第二圖係顯示習知技術之中基板的剖面示意圖，在介電層之 上覆蓋鎢金屬層，並填入接觸孔中； 第三圖係顯示習知技術之中基板的剖面示意圖，對鎢金屬層 進行回蝕刻處理，去除在介電層頂面的鎢金屬層； 第四圖係顯示習知技術之中基板的剖面示意圖，形成金屬線 連接鎢金屬栓塞，形成積體電路的内連線； 第五圖係顯示習知技術之中基板的剖面示意圖，沉積一層介 電層覆蓋在表面，並定義一接觸孔，在基板上形成一 深接觸孔； 第六圖係顯示習知技術之中基板的剖面示意圖，在深接觸孔 中填入鎢金屬材料，形成積體電路的金屬接觸； 第七圖係顯示本發明之中基板的剖面示意圖，在基板的表面 覆蓋一層介電材料，並於介電材料之中形成積體電路 的接觸孔； 第八圖係顯示本發明之中基板的剖面示意圖，沉積鎢金屬層 覆蓋在介電層之上，並填滿接觸孔； 第九圖係顯示本發明之中基板的剖面示意圖，對鎢金屬層進 行回蝕刻處理，於接觸孔中形成插塞，而且在接觸孔 上方形成鎢金屬島與鎢金屬線，其中鎢金屬線是作為 積體電路的内連線； ----^-------------訂------广 一 I (請先閱讀背面之注意事項再填寫本頁) 本紙朵尺度適用中國國家標準（CNS > A4規格（210X297公釐）This paper size applies to China National Standards (CNS) A4 specifications (210X297 mm J 421852 A7-^ --- Coffee 7 / B7 V. Description of the invention () Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs-Dielectric The surface of the layer 11G is usually deposited by a chemical vapor deposition process. In the preferred embodiment, the material of the first barrier layer 115 is a titanium metal layer and a titanium nitride layer. The thickness of the titanium metal layer in the barrier layer 115 is between 2GG and 15GG angstroms, and the thickness of the titanium nitride layer is between 300 and 2000 angstroms. The tungsten metal material filled in the contact hole becomes a metal plug. Plug, and then perform the etch back process (etch_back) to perform an etching process on the tungsten metal layer i2〇 to remove the tungsten metal layer 12 above the surface of the first dielectric layer 110, in the -dielectric layer A first-barrier layer 115 is reserved on 110 as an adhesion layer between the metal line and the first dielectric layer 110. After the touch-etching process, a metal plug having the same flat height as the first dielectric layer 110 is formed. As shown in the third figure, please refer to the fourth figure, which is formed on the first dielectric layer 11 and the town metal layer 12. The surface of the metal plug defines the metal line 125 connected to the metal plug. The metal line 125 is usually an interconnect line of a product circuit. After the metal plug is formed, an additional interconnect must be formed. After the metal line 125 An anti-reflection layer 126 is formed, and the constituent material is a titanium nitride material with a thickness of 100 to 1000 angstroms. The constituent material of the metal wire 125 is aluminum metal, and a small amount of silicon and aluminum are added to the aluminum metal. The copper material 'forms an aluminum-silicon-copper metal line (metal Al-Si-Cu line). Referring to the fifth figure, the second dielectric layer 130 is uniformly deposited on the first dielectric layer 110 and covers the anti-reflection Layer 126. One of the metal plugs formed in the first dielectric layer 110 is a metal contact prepared as a deep contact hole. On top of the gold plug, a second dielectric layer 13 is formed. The contact hole exposes the top surface of the metal plug. A contact hole is formed in the second dielectric layer 130 on the anti-reflection layer 126 as a metal contact hole for the metal line 125. See FIG. 6 and deposit a second The barrier layer 135 covers the second dielectric layer. 13 paper is transferred from i4 S) Eight secrets (21QX297 public envy) ---------- ^ --- ^ ---- tr ------ 0 (Please read the precautions on the back before filling this page) The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs prints A7 __ — —-__ B7 5. The surface of the invention description () is covered by the metal wire 125 and the town metal f 120. In a preferred embodiment, the first —The barrier layer 135 is composed of a titanium metal layer and a nitride layer. The thickness of the second barrier layer 135 is the same as the thickness of the first barrier layer 5. The contact hole of the second dielectric layer 130 is covered with tungsten. The plug ⑽ is connected to the tungsten metal layer 120 in the first dielectric layer 110. The process described above is a method for manufacturing a metal connection in a deep contact hole of an integrated circuit. A first dielectric layer is deposited on a substrate and has two contact holes, and then a metal plug is formed to fill the contact hole. Then, a copper copper wire is formed on one of the gold layer plugs, which is used as the interconnect of the integrated circuit. A second dielectric layer is deposited on the first dielectric layer, and a contact hole is formed on the other. On top of one metal plug, a tungsten metal material is filled in the contact hole of the second dielectric layer, and the metal plug of the first dielectric layer is connected to complete the manufacturing process of the integrated circuit deep contact hole. However, in the above process, the formation of deep contact holes must be performed in two stages. After the metal plugs of the first dielectric layer are formed, the interconnects of the integrated circuit must be formed before the second dielectric is formed. The metal plugs of the layer 'then in the process of forming the interconnections of the integrated circuit, it is necessary to deposit an aluminum metal material' again, and then use lithography and etching techniques to define the metal line pattern on the aluminum metal layer. Therefore, the process of defining a metal wire is quite complicated ', which requires a lithographic process to align the metal wire with the top surface of the metal plug to form a good metal contact. Moreover, when forming the contact hole of the second dielectric layer, it is also necessary to use a lithography process to align the contact hole with the metal plug of the first dielectric layer in order to form a deep contact hole with good metal contact. These processes of aligning metal plugs using the lithography process are quite complicated. 'If there are some errors in the lithography process, the alignment offset will occur. This paper size is generally China National Standard (CNS) Α4ίΙ grid (210X297 mm) ) ..---- ^ ------ ΐτ ------ Κ (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 2185 2 at B7 V. Explanation of the invention () (misalign), making the metal connection not well connected. Therefore, there is a need for a simple interconnection process for deep contact holes, which can avoid the complicated process of forming interconnections in integrated circuits, and can easily form metal contacts for deep contact holes. c 5-3 Purpose and summary of the invention: The present invention discloses a method for manufacturing a deep contact hole of an integrated circuit, providing a substrate, manufacturing an integrated circuit or a semiconductor element on the substrate, and depositing a first dielectric layer on the substrate. On the surface of the substrate, two contact holes are formed in the first dielectric layer to serve as contact windows of the integrated circuit. Then, a tungsten metal layer is deposited to fill the contact holes and cover the surface of the first dielectric layer. After the tungsten metal layer is formed, an etching process is performed to etch the tungsten metal layer to form a metal plug of a contact hole, and a tungsten metal island or a tungsten metal wire is formed on the top of the metal plug, wherein the tungsten metal wire is inside the integrated circuit Wiring, the tungsten metal island is a contact part reserved for a deep contact hole. Then, a second dielectric layer is deposited to cover the surfaces of the first dielectric layer and the tungsten metal layer, a contact hole is formed above the tungsten metal island, and finally a metal plug is formed in the contact hole of the second dielectric layer. Complete the metal contact of the deep contact hole of the integrated circuit. 5-4 Schematic illustration: Many of the objects and advantages of the present invention will become easier to appreciate and understand by referring to the following detailed description, while referring to the following drawings (please read the note on the back first) Please fill in this page again for this matter) This paper size applies Chinese National Standard (CNS) A4 specification (210X297mm) Printed by the Intellectual Property Bureau Staff Consumer Cooperatives 42185 2 A7 B7 V. Description of the invention () It is a schematic cross-sectional view of a substrate in a conventional technique. The surface of the substrate is covered with a dielectric layer of an integrated circuit, and two contact holes are formed in the dielectric layer. The second diagram is a cross-section of the substrate in a conventional technique. Schematic, covering the dielectric layer with a tungsten metal layer and filling it into the contact holes. The third diagram is a schematic cross-sectional view of a substrate in a conventional technology. The tungsten metal layer is etched back and removed on top of the dielectric layer. The fourth diagram is a schematic cross-sectional view of a substrate in a conventional technology. A metal wire is formed to connect a tungsten metal plug to form an interconnect of an integrated circuit. The fifth diagram A schematic cross-sectional view of a substrate in a conventional technology is shown. A dielectric layer is deposited to cover the surface, and a contact hole is defined to form a deep contact hole in the substrate. The sixth diagram is a schematic cross-sectional view of a substrate in the conventional technology. The tungsten contact material is filled in the deep contact hole to form a metal contact of the integrated circuit. The seventh diagram is a schematic cross-sectional view of the substrate in the present invention. The surface of the substrate is covered with a layer of dielectric material and is placed in the dielectric material. Forming contact holes for integrated circuits; FIG. 8 is a schematic cross-sectional view of a substrate in the present invention, and a tungsten metal layer is deposited on the dielectric layer to fill the contact holes; FIG. 9 is a substrate in the present invention Schematic cross-section view, etch back the tungsten metal layer, form plugs in the contact holes, and form tungsten metal islands and tungsten metal wires above the contact holes, where the tungsten metal wires are used as interconnects of integrated circuits;- --- ^ ------------- Order ------ Guangyi I (Please read the notes on the back before filling in this page) The paper size is applicable to Chinese national standards (CNS > A4 size (210X297 mm )
B7 五、發明説明（） 第十圖係顯示本發明之中基板的剖面示意圖，在介電層與鎮 金屬之上，再沉積一層介電層，並於此介電層之中定 義出深接觸孔；以及 第十一圖係顯示本發明之中基板的剖面示意圖，於深接觸孔 之中填入鎢金屬材料，形成積體電路的金屬接觸。 5-5發明詳細說明： 本發明揭露一種積體電路之深接觸孔的製造方法，先於第 一介電層中形成金屬插塞，並於形成金屬插塞的同時，定義積 體電路的内連線，然後，形成第二介電層覆蓋在第一介電層之 上，於第二介電層中形成金屬插塞，連接第一介電層金屬插塞。 由於定義積體電路之内連線的方法，是直接對鎢金屬層進行蝕 刻製程，於金屬插塞的頂端形成金屬島與金屬線，其中金屬線 與金屬插塞連接，而金屬島是作為後續金屬插塞的連接部份， 由於金屬島的頂面面積較大，在形成深接觸孔的金屬接觸時， 能夠很容易對準金屬島，形成良好的金屬接觸。 請參閱第七圖，提供一基板100，為P型並具有<1〇〇>晶軸 方向的半導體基板，於基板100上製造積體電路或是半導體基 板。在基板1〇〇上覆蓋第一介電層110，第一介電層110之中 具有兩個接觸孔，將基板100的表面暴露出來，通常第一介電 層110的組成材料為二氧化矽材料，作為積體電路的内介電層 (ILD)或是金屬間介電層（IMD)，第一介電層110的厚度約在3000 到20000埃之間。 本紙伕尺度適用中國國家橾準（CNS ) A4規格（2!0X297公釐） (請先聞讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 4 2185 2 A7 B7 五、發明説明（） 請參閱第八圖，沈積一第一阻障層115至第一介電層110 的表面，並覆蓋在第一介電層110中的兩個接觸孔的表面。在 一較佳實施例之中，第一阻障層115的組成材料為一鈦金屬層 與一氮化鈦層，鈦金屬層的厚度係介於200至1500埃之間， 氮化鈦層的厚度係介於300至2000埃之間。沉積鎢金屬層120 "'填入第一介電層Π0的接觸孔中，並覆蓋在第一阻障層115的 表面。沉積鎢金屬層120通常是使用化學氣相沉積製程（chemical vapor deposition, CVD)，沉積厚度約為 2500 到 10000 埃之間。 請參閱第九圊，對鎢金屬層120與第一阻障層115進行蝕 刻製程，所使用的蝕刻製程為電漿蝕刻製程，在第一介電層110 的接觸孔之中與表面，形成金屬島A與金屬線B。金屬島A的 形狀為突出於洞口之外，並覆蓋到洞口周圍的第一介電層110， 與填入於接觸孔中的金屬插塞連接；金屬線B連接接觸孔中的 金屬插塞，覆蓋在第一介電層110的表面，作為積體電路的内 連線（interconnect丨ine)e在姓刻製程之中，第一阻障層115同 時被蝕刻，僅留下在金屬島A與金屬線B對第一介電層11〇之 間的第一阻障層115，作為金屬材料與介電材料之間的黏著層。 形成第一介電層110之接觸孔的金屬插塞時，同時於接觸 孔之上形成金屬島A與金屬線B，金屬島A是預留後續深接觸 孔的金屬接觸，比起習知技術之中所用的金屬插塞，金屬島A 具有較大的頂面，方便後續微影製程的對準步驟。於本發明中， 形成金屬線B的步驟’是於定義金屬插塞的步驟之^中同時進" 所以’無須再定義鋁矽銅金屬線，節省許多製程 少驟，降低生 產成本。 本纸張尺度逋用中國國家椟準（CNS) A4说格（210X297公釐） I I: I. . Γ I 1 …— 丨.11n —i : I n —iiy., (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 4 2 185 2 at _B7 五、發明説明（） 請參閱第十圖，沉積第二介電層130覆蓋在第一介電層110 與鎢金屬層120之上，而且在金屬島A與金屬線B之上各開啟 一個接觸窗，在金屬島A上的接觸窗，與金屬島A形成一個深 接觸孔，金屬線B上的接觸窗是作為金屬接觸之用。於定義第 二介電層130的接觸孔之後，暴露出金屬島A與金屬線B的頂 &面，預留後續金屬連接的接觸點。通常第二介電層130的組成 材料為二氧化矽材料，厚度約為2000到10000埃之間。 請參閱第十一圖，沈積第二阻障層135至第二介電層130、 金屬島A與金屬線B的表面，第二阻障層135的組成材料與厚 度，與第一阻障層115相同。形成鎢金屬插塞140填入到介電 層130之中的接觸孔，連接金屬島A與金屬線B的頂面，完成 積體電路之深接觸孔的金屬接觸。此鎢金屬插塞140的沉積方 法，通常是使用化學氣相沉積製程（chemical vapor deposition, CVD)。 於本發明的詳細說明中，揭露一個積體電路之深接觸孔的 製造方法，於兩層介電層之中形成深接觸孔，並以鎢金屬材料 作為金屬插塞(metal plug)，形成積體電路的金屬接觸與金屬内 連線，可是本發明的重點在於同時形成深接觸孔與金屬内連線 的方法，並不限於使用鎢金屬材料做為金屬插塞材料或是金屬 内連線材料，任何做為金屬插塞或是金屬内連線的金屬材料， 都可運用於本發明的較佳具體實施例之中。 本發明以較佳實施例說明如上，而熟悉此領域技藝者，在 不脫離本發明之精神範圍内，當可作些許更動潤飾，其專利保 護範圍更當視後附之申請專利範圍及其等同領域而定。 本紙張尺度通用中國國家標準（CNS ) A4規格（210X297公釐） i n ik訂 _rI *- (請先閲讀背面之注意事項再填寫本頁)B7 V. Description of the invention (10) The tenth diagram is a schematic cross-sectional view of a substrate in the present invention. A dielectric layer is deposited on the dielectric layer and the ballast metal, and a deep contact is defined in the dielectric layer. Holes; and FIG. 11 is a schematic cross-sectional view of a substrate in the present invention. A tungsten metal material is filled in the deep contact holes to form metal contacts of the integrated circuit. 5-5 Detailed description of the invention: The present invention discloses a method for manufacturing a deep contact hole of an integrated circuit. A metal plug is formed in the first dielectric layer, and the internal of the integrated circuit is defined while the metal plug is formed. Then, a second dielectric layer is formed to cover the first dielectric layer, a metal plug is formed in the second dielectric layer, and the first dielectric layer metal plug is connected. Because the method of defining the interconnections of the integrated circuit is to directly etch the tungsten metal layer, a metal island and a metal wire are formed on the top of the metal plug, where the metal wire is connected to the metal plug, and the metal island is used as a follow-up Due to the large area of the top surface of the metal island in the connection portion of the metal plug, the metal island can be easily aligned to form a good metal contact when forming a metal contact in a deep contact hole. Referring to the seventh figure, a substrate 100 is provided, which is a P-type semiconductor substrate having a crystal axis direction of < 100 >, and an integrated circuit or a semiconductor substrate is manufactured on the substrate 100. The substrate 100 is covered with a first dielectric layer 110. There are two contact holes in the first dielectric layer 110 to expose the surface of the substrate 100. Generally, the material of the first dielectric layer 110 is silicon dioxide. The material is used as an inner dielectric layer (ILD) or an intermetal dielectric layer (IMD) of the integrated circuit. The thickness of the first dielectric layer 110 is about 3000 to 20,000 angstroms. The size of this paper is applicable to China National Standards (CNS) A4 (2! 0X297 mm) (please read the notes on the back before filling out this page) Order the Intellectual Property Bureau of the Ministry of Economic Affairs, the Consumer Cooperative, and the Intellectual Property Bureau of the Ministry of Economic Affairs. Printed by the employee consumer cooperative 4 2185 2 A7 B7 V. Description of the invention () Please refer to the eighth figure, deposit a first barrier layer 115 to the surface of the first dielectric layer 110, and cover the first dielectric layer 110 The surface of the two contact holes. In a preferred embodiment, the first barrier layer 115 is composed of a titanium metal layer and a titanium nitride layer. The thickness of the titanium metal layer is between 200 and 1500 angstroms. The thickness is between 300 and 2000 Angstroms. The tungsten metal layer 120 is deposited in a contact hole of the first dielectric layer Π0 and covers the surface of the first barrier layer 115. The tungsten metal layer 120 is typically deposited using a chemical vapor deposition (CVD) process, with a thickness of approximately 2500 to 10,000 Angstroms. Referring to the ninth step, an etching process is performed on the tungsten metal layer 120 and the first barrier layer 115. The etching process used is a plasma etching process, and a metal is formed in the contact hole and the surface of the first dielectric layer 110. Island A and metal wire B. The shape of the metal island A is a first dielectric layer 110 protruding beyond the hole and covering the hole, and is connected to the metal plug filled in the contact hole; the metal wire B is connected to the metal plug in the contact hole. Covered on the surface of the first dielectric layer 110, as an interconnect circuit of the integrated circuit. During the engraving process, the first barrier layer 115 is etched at the same time, leaving only the metal island A and The first barrier layer 115 between the metal line B and the first dielectric layer 110 serves as an adhesion layer between the metal material and the dielectric material. When the metal plug of the contact hole of the first dielectric layer 110 is formed, a metal island A and a metal wire B are formed on the contact hole at the same time. The metal island A is a metal contact reserved for subsequent deep contact holes. For the metal plug used therein, the metal island A has a large top surface, which facilitates the subsequent alignment steps of the lithography process. In the present invention, the step of forming the metal wire B is performed simultaneously in the step of defining the metal plug " so 'there is no need to define an aluminum-silicon-copper metal wire again, which saves many processes and reduces production costs. This paper uses the Chinese National Standard (CNS) A4 scale (210X297 mm) II: I.. Γ I 1… — 丨 .11n —i: I n —iiy., (Please read the note on the back first Please fill in this page again) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 2 185 2 at _B7 V. Description of the invention () Please refer to the tenth figure, the second dielectric layer 130 is deposited on the first dielectric layer 110 On the tungsten metal layer 120, a contact window is opened on each of the metal island A and the metal wire B. The contact window on the metal island A forms a deep contact hole with the metal island A, and the contact window on the metal wire B For metal contact. After defining the contact holes of the second dielectric layer 130, the top & planes of the metal island A and the metal line B are exposed, and the contact points for subsequent metal connections are reserved. Generally, the second dielectric layer 130 is composed of a silicon dioxide material with a thickness of about 2000 to 10,000 angstroms. Referring to the eleventh figure, the second barrier layer 135 to the second dielectric layer 130, the surface of the metal island A and the metal wire B are deposited, the composition material and thickness of the second barrier layer 135, and the first barrier layer 115 is the same. A contact hole filled with the tungsten metal plug 140 into the dielectric layer 130 is formed, and the metal island A and the top surface of the metal line B are connected to complete the metal contact of the deep contact hole of the integrated circuit. The tungsten metal plug 140 is generally deposited using a chemical vapor deposition (CVD) process. In the detailed description of the present invention, a method for manufacturing a deep contact hole of an integrated circuit is disclosed. A deep contact hole is formed in two dielectric layers, and a tungsten metal material is used as a metal plug to form a product. The metal contact and metal interconnection of the body circuit, but the focus of the present invention is on the method of forming a deep contact hole and the metal interconnection at the same time, and is not limited to using tungsten metal material as the metal plug material or the metal interconnection material Any metal material used as a metal plug or a metal interconnect can be used in the preferred embodiment of the present invention. The present invention has been described above with reference to the preferred embodiments, and those skilled in the art can make some modifications and modifications without departing from the spirit of the present invention. Field-specific. The paper size is in accordance with the Chinese National Standard (CNS) A4 specification (210X297 mm) i n ik order _rI *-(Please read the precautions on the back before filling this page)