TWI222726B - Bond pad structure and method of manufacturing the same - Google Patents

Abstract

A bond pad structure and method of manufacturing the same is provided. The bond pad consists of an ILD which has many isolated dielectric protuberances and is deposited on an upper conductive layer, a barrier layer which is deposited on the isolated dielectric protuberances, a conductor located between the barrier layer and the isolated dielectric protuberances, and a metal layer that defined to many bond pads, wherein the isolated dielectric protuberances would be a grid pattern, the conductor is located in trenches of the grid pattern, and the metal layer is located on the grid pattern.

Description

1222726 ___Case No. 92122333__Year Month Day_ Amendment _ V. Description of the Invention (1) Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, to the formation of a bond pad In order to connect the semiconductor device to an external conductive wire through a bond site, a method of making a connection pad known in the prior art is to provide an upper conductor layer on the substrate. Then, an interlayer dielectric (ILD) is coated on the upper conductor layer. Subsequently, one or more contact window structures are formed in the inner dielectric layer to electrically connect the connection pad to the upper conductor layer. However, during the connection of the connection pad, the connection pad may be broken or separated from the dielectric layer due to the impact of the bonding pressure, which may cause the product and the connection to be poor. The inventor of the invention Therefore, the object of the present invention is to provide a connection pad structure and a method for manufacturing the same, so as to prevent the stress break of the connection pad. Another object of the present invention is to provide a connection pad structure and a manufacturing method thereof. When the connection pad is bonded to the bonding wire, the structure of the present invention can achieve the attenuation of the stress on the connection 塾 (a 11 e n u a t i ο η). Another object of the present invention is to provide a connection pad structure and a manufacturing method thereof 'which can reduce the occurrence of electromigration. Yet another object of the present invention is to provide a bonding pad structure and a method for manufacturing the same 'to increase the adhesive strength between the layers.

9241twfl.ptc Page 8 1222726 Case No. 92122333 _Ά said to amend its manufacturer ifti ng) provide an i nat i on) provide a size, the present invention has several islands of resistive material and dielectric island structure trench clearance The conductor device element of the deformed structure, and a half of an insulating layer leads to a second insulation to define a gold-like structure of a pad on the interlayer barrier layer of the entire edge layer and the inner layer, which is a layer-configured dielectric. Mass island vortex type, and the semiconducting first insulation in the multi-groove section of the semiconductor conductor base layer distribution, the third and the fifth, the description of the invention (2) Another object of the present invention is to reduce stratification (The occurrence of de 1 am. Another object of the present invention is to reduce the density of the bonding wire or the ball junction pad. According to the above and other purposes, it is deposited by an electric layer on an upper conductor layer, an independent dielectric and The conductors between the independent dielectric islands are composed of layers. Among them, the independent and conductive material is arranged on the grid-like structure on the grid-like structure. The present invention can also have other interaction deformations, in addition to the above The invention further provides a half-body device having at least one semiconductor layer, and the connection pad is placed on the first layer including the base layer laminated on the first insulating layer and a portion above the first insulating layer that is patterned and bounded. The number of trench segments, the connection pad layer formed in the trench segments, and the second insulation pad structure and the pull-up situation are covered (1 the connection pad structure and its manufacturing method, and then a single element is added to the connection to propose a connection pad structure with independent dielectric The quality island barrier layer is arranged in a grid canal defined by several links, and gold. For example, it can be independent, it can also be a connection pad structure covered on it. Its characteristics are in the body base layer, the laminated layer, and It is semi-continuous but spaced completely covering the grooved connection cushion.

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Marginal layer. According to the present invention, a method for manufacturing an ice layer and an inner layer of interlayer dielectric k seeding connection plutonium structure is defined on the upper layer of the conductor layer i and t, and then deposited in the inner dielectric layer and deposited one: the number above pa 9 The structure of two independent dielectric islands is on the independent dielectric islands. After that, a conductive material is formed to define a plurality of connection pads, and then a metal layer is deposited, and the metal layer is in the present invention.

Therefore, it can help to remove a barrier layer as an adhesive layer (g 1 U e 1 ayer), which can prevent the conductive layer of Snow Cunning II from adhering to the existing layer, and the barrier layer is also ΐ】: Bu Wai, According to the present invention, the trench and the inner dielectric layer covering the inner layer can increase the strength of the grid-shaped contour formed by the dielectric islands (Prototuberance), and reduce the adhesive strength between the '9 and' 9 due to the manufacturing process. The occurrence of the resulting knots will reduce the likelihood of subsequent bonding wires or balls from the mat. Such a structure can increase the easy-to-understand connections on a single element. The above and other objects, features, and advantages of the present invention can be more clearly described below. A preferred embodiment is given below, and in conjunction with the accompanying drawings, it is used as a detailed reference example. A detailed example will be shown in the accompanying drawings that is the same as or different from the description. Moreover, the icon is about the direction used in the icon

Finer than proposed in the preferred embodiment of the present invention, and. Wherever feasible, similar reference signs used in the drawings refer to the same or similar parts in the form of diagrams, not exact dimensions. Sexual phrases such as top, bottom, left, right,

Page 10 1222726 _ Case No. 92122333_ 色 月 日 绦 正 _ V. Description of the invention (4) Up, down, above, below, below, back and front, reference examples disclosed here Just for convenience and clarity. Such directional terms should not be construed as limiting the scope of the invention in any way. Although the content disclosed herein is about the illustrated embodiments, it can be understood that these embodiments are presented by way of example rather than limitation. The meaning of the following detailed description is to encompass all variations, alternatives, and equivalents defined as subsidiary items within the spirit and scope of the present invention. For example, those skilled in the art can know that the bonding pads manufactured according to the present invention can be directly connected to the wires, or can be used for tape-automated bonding to form solder or gold. Gold bumps are at the bond site. Different barrier materials, different dielectrics, different conductor and metal layers, and different combinations can therefore be used to implement the invention. Known and understood process steps and structures described herein do not include the entire manufacturing process of the bonding pad structure. The present invention can be applied to various integrated circuit manufacturing techniques conventionally used, and even only the general manufacturing techniques included therein need to provide an understanding of the present invention. Please refer to FIG. 1 in detail for a cross-sectional view of a semiconductor device at an intermediate process stage. In the illustrated embodiment, the semiconductor device has gone through a number of manufacturing steps, one of which is to provide an upper conductor layer 10 on top of the formation layer which may include the field oxide layer 8. The field oxide layer 8 may include, for example, any method such as thermal oxidation or chemical vapor deposition (chemical vapor deposition).

9241twfl.ptc Page 11 1222726 _Case No. 92122333_Year Month Day Amend _____ V. Description of the invention (5) Dioxide of oxidized silica (Si 02) formed by vapor deposition (referred to as CVD). Such a device exists on a substrate (not shown), and typically includes a wafer in the form of P-type or n-type doped silicon. Although the substrate preferably includes a silicon substrate, in alternative embodiments, the substrate may include a semiconductor material such as gallium nitride (GaN), gallium arsenide (GaAs), or other conventionally recognized technologies as appropriate. Then, an interlayer dielectric (ILD) 12 is coated on the upper conductor layer 10 by a conventional method. The material of the upper conductor layer may include polycrystalline silicon, copper, or aluminum. The material of the inner dielectric layer 12 may include standards selected from conventional technologies such as spin on glass (S0G), borophosphosi 1 icate glass (BPSG), or dioxide. Shi Xi (Si02). Then, a layer of photoresist was deposited on the substrate of FIG. 1 using a spinner. Next, a stepper or mask aligner is used in combination with a suitable photomask to perform a lithography process, in which a predetermined exposure area of the wafer is irradiated with ultraviolet light. The wafer is then placed in a developer (developerbath) to reveal a pattern in the photoresist, and the hardener will dissolve the depolymerized photoresist (for positive photoresist), Or dissolve the photoresist that is not polymerized by UV light (for negative photoresist). Subsequently, the inner dielectric layer 12 is anisotropically etched using a process such as reactive ion etching (r e a c t i v e i ο η etching, abbreviated as R IE) to transfer the photoresist pattern to the inner dielectric layer 12. In this embodiment, the etching process still completely etches away the areas of the inner dielectric layer 12 exposed by the photoresist.

9241twfl.ptc Page 12 1222726 Case No. 921223 ^ V. Description of the invention (6) domain and stop at the upper conductor layer 〖ashing and cleaning steps After H ^, a standard dielectric layer 12 is used. The second and second pictures formed by etching are shown in the top view of the inner layer. Illustratively, the internal sound,] Hrid Patterii) 15 channel 14 draws a mutual, car layer ^: the shape of the trench formed by etching in the electrical layer 12, to form islands such as independent dielectrics, mu Most of the groove sections of 1 you 2 ^ are grid-like patterns of island structure 1 5. It can be a pattern that is formed by etching in the 7¾ type ^ 1 廿 layer dielectric layer 12: the 型 "type net 'is not limited to the grid-like diagram tea ib shown in Figure 2 〇 Driving In the known example, the general step is to provide several interlayer window structures (V1a structure) to electrically connect the connection pad with the upper conductor layer 1 (^), and the bonding process may cause thermal and structural strain due to the influence of characteristics ( The increase in strain), such as the difference in thermal expansion coefficient (Coefficient Qf thermal expansiQn) between the inner dielectric layer 12 and other layers, causes stress fracture in the inner dielectric layer 12 (stress fracture).幵 > The 袼 grid pattern formed in accordance with the present invention will reduce the net presence of the inner dielectric layer 12. For example, as the resistance between some of the inner dielectric layers 12 is reduced, The inter-dispersion of barrier layer 17 and tungsten 19 can tolerate different expansion and contraction between inner dielectric layer 12 and tungsten layer 19. For example, when connecting pad and When the bonding wires are bonded, the structure of the present invention can be used to achieve Attenuation of the stress to the inner dielectric layer 12. As shown in FIG. 3, the inner dielectric layer 12 and the upper conductor layer 10 sink.

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积 Barrier Layer 17. The barrier layer 17 may include titanium (Ti), titanium nitride (TiN), titanium / titanium nitride (Ti / TiN), nitride button (TaN), tungsten nitride (WN), and molybdenum nitride (MoN). , Silicon nitride (SiN) or silicon oxynitride (SiON). The titanium / titanium nitride used here is either tempering a titanium layer in a nitrogen atmosphere to transform at least part of the titanium layer into titanium nitride, or using a separate process step to deposit a thin titanium nitride layer on a thin titanium layer. .

In this embodiment, the barrier layer 17 includes depositing a titanium nitride layer by sputtering or chemical vapor deposition to obtain a substantially uniform surface on the surface of the inner dielectric layer 12 and the surface of the upper conductor layer 10. thickness. Titanium nitride is a hard and dense refractory material, so it can provide a fairly high electrical conductivity. According to the present invention, the barrier layer 17 serves as a glue layer to help future conductor layers adhere to the existing layer. The early P resist layer 17 is also used to prevent the dark layer 19 from piercing the upper conductor layer 10 or the inner dielectric layer 12 ′ and to reduce the occurrence of electromigration. Once the barrier layer 17 is deposited, it will include a structure similar to the grid pattern 15 of the trenches 4 and the unconnected rectangular inner layer dielectric layer 12. Use such as physical vapor deposition (ph y s i c a 1 after ^ · ,,,,, x --- j — x y a y kj l

deposition (abbreviated as PVD) or sputtering, or chemical vapor deposition ’is used to cover the barrier layer 17 with a conductive material having an appropriate step coverage, and the conductive material is a tungsten layer 19, for example. It is best to flood enough tungsten layer 19 to fill the trenches of the grid-like structure, 4 to approximately 6 ^% ~ 90% of the capacity. The best case before g is to fill only a part of the surface of the final wafer of SUi, which is non-planar, and the difference in height between the tungsten layer 19 and the early P layer 17 and the characteristics that define the surface are revealed. wonderful

1222726 ----- MM 9212233.¾_Year Month Date ___ V. Description of the invention (8) Moreover, tungsten can also completely fill the trenches 14 in another embodiment. After the tungsten layer 19 is deposited, a chemical mechanical polishing (CMP) process is used to remove the tungsten layer 19 on the inner dielectric layer 12, leaving only the tungsten layer 19 in the trench 14. Those familiar with semiconductor processes should know that chemical mechanical polishing is a polishing process used for oxides and metals to remove uneven materials and polish wafer planes. The chemical slurry can be used with a circular sanding action to produce a flat surface and, in the present example, the portion where the tungsten layer 19 has been determined is removed. In the modified embodiment, the trench 14 is completely filled with the crane layer 19, so the chemical mechanical polishing process is omitted, and an etchant with a relatively high selectivity for the tungsten layer 19 is used compared to the barrier layer 17 To etch the tungsten layer 19 on the inner dielectric layer 12. Therefore, the barrier layer 17 can serve as an etch stop layer to help etch into the trenches 14 filled with tungsten. According to yet another embodiment, the trenches 14 are initially completely filled, and then the tungsten layer 19 on the inner dielectric layer 12 is removed by chemical mechanical polishing or etching, so as to generate an extended dielectric layer. 1 2 and the flat surface on the ditch 1 4. The preferred final structure is shown in Fig. 4 ', which includes a grid-like tungsten layer 19 distributed among the 12 inner dielectric layers. In this embodiment, the inner dielectric layer 12 includes a series of isolation blocks protruding from the filling trench 14 and forming a grid-like shape. In FIG. 5, a metal layer 21 is deposited on a wafer, and the material thereof includes a highly conductive metal such as aluminum, copper, gold, or an alloy of the foregoing and other trace elements. According to the present invention, the grid-like contour formed by the trench 14 and the barrier layer protrusion covering the inner dielectric layer 12 can promote the increase between the crane layer 19, the barrier layer 17 and the metal layer 21. Viscous strength

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Various processes, especially the bonding of the bonding layer to the bonding wire, can ultimately endow the bonding pad with mechanical and thermal energy. The grid-like structure of the present invention can minimize stratification, delamination and lifting caused by the manufacturing process, except for the metal layer 21 and the barrier layer 17. It is known that the layering problem of bonding 塾 exists in all types of bonding technologies including aluminum wire bonding ^^ ... ㈣ ^ ... "bond, gold bump bonding, and gold ball bonding. According to the present invention, FIG. 5 shows that the depression 24 exists in the metal layer 21 due to the terrain existing in the lower layer. FIG. 6 is a perspective view illustrating the same structure. The depression 24 can be reflected by § The grid-like structure formed by the pattern of the barrier layer 17 and the tungsten layer 19 on which the metal layer 21 is disposed. ^ The metal layer 21 serves as a connection structure to connect a semiconductor element to a lead (pi η ) 'It can then be attached to a printed circuit board (pr 丨 η ^ edcircuit board). In order to define the range of each connection of the semiconductor element, another lithography process is performed. A photoresist is spin-coated on the metal layer 21, and It is then exposed to UV radiation in a stepper or mask aligner. The depolymerized photoresist is then dissolved, and the metal layer 21 is etched using, for example, reactive ion etching to transfer the photoresist pattern to Metal layer 21. Then removed Resistance, and the final structure element defined as the bonding pads may then be supplied and patterned passivation layer (passivation layer) such as boron phosphorus silicon glass (not

9241twfl.ptc Page 16 1222726 Amendment No. 92122333 V. Topmost layer of the description of the invention (10), leaving only the connection points (b ο n d s i t e) openings to be electrically connected. There are many ways to electrically connect to the crystal cube (d i e), and all of them can be applied to the present invention. In a tape automated bonding (TAB) packaging process, a chip package includes a lead frame with a plurality of conductive leads, and the k is provided for gold or Yi tin Bump. The lead frame includes a crystal receiving area (dk receiving ar »ea), which is arranged so that the lead tin or gold bumps at the ends of the conductors are aligned with the bonding pads on the crystal. In another form of packaging, the package includes a cube placement area containing several conductor pins. The conductor pins are arranged in a geometric pattern, usually in a radial form, to align with each connection on the crystal cube ... 塾. Then ’use a thin Sau or Au bonding wire (b ο n d w i r e) to connect each connection pad to the conductor pin on a one-to-one basis. Fig. 7 shows a plan view of a semiconductor crystal 28 having a plurality of 塾 30. Each connection pad 30 is mechanically and electrically connected to a conductive bonding wire 26 (for example, aluminum or gold), and the bonding wire 26 is arranged radially around the semiconductor crystal cube 28, so there are no two The wires are in contact with each other. With reference to Figure 6, the contour surface of the connection pad can provide better and better bonding characteristics. When the wire 26 or the ball adheres to the connection pad, the wheel surface can provide a better bonding surface area, which results in stronger adhesion. This will reduce the possibility of subsequent bonding wires "or balls divided from the bonding pads by two =. The result of stronger adhesion will reduce the size of the bonding wires 26 or ^ without weakening the bonding force. Such a construction will It becomes feasible to increase the density of the bonding pads on the component.

924ltwfl.ptc Page 17 1222726 _ Case No. 92122333_ Year Month Date _ V. Description of the invention (11) In view of the above, those skilled in the art will know that the present invention can promote the formation of the connection pad structure in the integrated circuit operation . The above-mentioned embodiment is only an example, and the present invention is not limited to this example. Anyone skilled in this art can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application.

9241twfl.ptc Page 18 1222726 _ Case No. 92122333_ Year Month and Day Article _ Brief Description of the Drawings Figure 1 is a cross-sectional view of the process steps according to the present invention; Figure 2 is a plan view according to Figure 1 in the etching process The electric layer becomes a lower conductor layer of a grid pattern. FIG. 3 is a cross-sectional view of the semiconductor device after depositing a barrier layer and further processing according to FIG. 2 of the present invention. Figure 5 is a perspective view of a semiconductor device; Figure 5 is a cross-sectional view after depositing an aluminum layer according to Figure 3 of the present invention; Figure 6 is a connection pad structure with a wire connected to Figure 5 And FIG. 7 is a plan view of a semiconductor wafer connected to a plurality of wires. Graphical description 8: Field oxide layer 1 0: Upper conductor layer 1 2: Inner dielectric layer 14: Trench 15 5: Grid pattern 17: Barrier layer 1 9: Tungsten layer 21: Metal layer 22: Convex Starting surface 24: recess 2 6: bonding wire

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Claims (1)

1222726 _ Case No. 92122333_ Year, Month and Day Article _ 6. Application for Patent Scope 1. A method for forming a connection pad structure, the steps include: depositing an inner dielectric layer on an upper conductor layer; on the inner dielectric layer It defines a structure having a plurality of independent dielectric islands above the upper conductor layer; depositing a barrier layer on the independent dielectric islands; forming a conductor material between the independent dielectric islands; deposition A metal layer; and a plurality of connecting pads defined in the metal layer. 2. The method according to item 1 of the scope of patent application, wherein: the independent dielectric islands are a grid-like structure; the conductor material is arranged in a plurality of trenches of the grid-like structure; and the metal layer Arranged on this grid-like structure. 3. The method according to item 2 of the scope of patent application, wherein the trenches are filled to 60 ° /. ~ 90% of maximum volume. 4. The method according to item 1 of the scope of patent application, wherein the material of the upper conductive layer comprises polycrystalline silicon. 5. The method according to item 1 of the scope of patent application, wherein the material of the conductor includes Yan. 6. The method as described in item 1 of the scope of patent application, wherein the metal layer includes an inscription. 7. The method according to item 1 of the scope of patent application, wherein: a passivation layer is deposited on the structure of the connection pads; and an opening is defined in the passivation layer to expose the connections on the connection pads 9241twfl.ptc Page 21 1222726 _Case No. 92122333_ Year Month Date Article _ VI. Scope of patent application. 8. The method as described in claim 7 of the patent application scope, wherein the passivation layer comprises borophosphosilicate glass. 9. A connection pad structure for a semiconductor device, the semiconductor device having at least one semiconductor element, and covered with a first insulation layer, the connection pad being placed on the first insulation layer, characterized in that the connection pad comprises: A semiconductor base layer is stacked on the first insulating layer; a second insulating layer is stacked on the semiconductor base layer and the first insulating layer, and a portion above the semiconductor base layer is patterned to define a continuous but Most of the trench segments distributed at intervals; a connecting cushion layer formed in the trench segments and covering the trench segments in a whole piece; and a third insulating layer for covering the second insulating layer and Part of this link is tiered. 10. The bonding pad structure of the semiconductor device according to item 9 of the scope of the patent application, wherein the third insulating layer includes borophosphosilicate glass. 1 1. The connection pad structure of the semiconductor device according to item 9 of the scope of the patent application, wherein the connection pad layer further comprises: a barrier layer conformally formed on the wall surfaces of the trench sections and the second insulation layer On the surface; and a conductor layer stacked on the barrier layer and filling the trench segments. 1 2. The bonding pad structure of a semiconductor device as described in item 11 of the scope of the patent application, wherein the conductor layer includes a tungsten filled in the groove sections, and a covering filled in the groove sections. Tungsten and the surface of the barrier layer are selected from a high 9241twfl.ptc Page 22 1222726 _ Case No. 92122333_ Month and Date _ Zheng VI. Patent Application Scope Metals of one of the conductive metal groups. 1 3. The connection pad structure of a semiconductor device according to item 12 of the scope of the patent application, wherein the highly conductive metal is aluminum. 9241twfl.ptc Page 23