A7 B7 421831 五、發明説明（！） 本發明係有關於一種減低凹洞現象之方法，且特別 是有關於一種兩段式餘刻罩幕氧化層以在複晶石夕姓刻中 減低半導體基板凹洞現象之方法。 請 k： 閲 背 1¾ 之 注 意 事 項 再 請參考第1A〜1D圖，此為習知進行罩幕氧化層蝕 刻及複晶矽蝕刻時，形成金屬矽化物針孔及半導體基板 凹洞之剖面示意圖。 在第1A圖中，半導體基板1〇(如矽基板）上具有一 層氧化物12。氣化層π表面則形成一欲進行蝕刻之複 晶矽層14。複晶矽層μ表面具有一層改善電性用之金 屬石夕化物層16，如矽化鎢層。而金屬矽化物層16表面 則依序形成一由TEOS層ί18及BARC j 20組成之罩幕 氧化層，用以做為複晶石夕姑刻時之罩幕。B ARC層2〇表 面因材料缺陷具有裂口 24。 線 經濟部中央楳準局貝工消費合作社印聚 首先，在罩幕氧化層表面形成一層定義圖案之光阻 22。然後’利用光阻22為罩幕及利用π*、Ar、乂電漿 為反應氣體電漿蝕刻BARC層20及TEOS層18，用以 定義罩幕氧化層之圖案。在這個步驟中，由於Ch、Ar、 N2電漿可同時蝕刻BARC層20及TEOS層18，故裂口 24部分會因過渡敍到而在金屬 斜孔26，如第1B岡所示一。 接著，去除光阻層22，並利用蝕气後之罩幕氧化層 (包括BARC層20及TE0S層18)為罩幕及利用〇為反 應氣體電漿蝕刻金屬矽化物層16及複晶矽層14，藉以 完成複晶矽層14蝕刻，如第lc圖所示。在這個步驟中’ 本紙張尺度iS财關家縣(CNS ) A4· ( 2T〇i^i7 421831 經濟部中央標準局貝工消费合作社印f. A7 B7 五、發明説明（2 ) 由於金屬矽化物層16在先前罩幕氧化層蝕刻過程中已遭 破壞（具有針孔26)，因此C1亦會在氧化層12及半導體 基板10之對應位置過渡蝕刻，產生不想要的凹洞28破 壞電路元件，如第1D圖所示。 有鑑於此，本發明的主要目的就是在提供一種蝕刻 中減低凹洞現象的製造方法，其可以在罩幕層（TEOS層 及B ARC層）银刻時有效地防止複晶石夕表面（金屬石夕化物 層）之針孔現象，進而在複晶矽蝕刻時避免半導體基板之 凹洞現象。 為達上述及其他目的，本發明乃提供一種在複晶矽 蝕刻中減低凹洞現象的製造方法。這種方法首先是在矽 基板上提供一欲進行蝕刻之複晶矽層，其表面可以具有 一層改善電性用之金屬矽化物。然後，在複晶矽層表面 依序形成TEOS層及抗反射用之BARC層。BARC層表 面具有一層定義圖案之光阻。然後，以此光阻為罩幕， 利用02、N2電漿蝕刻BARC層，及，利用CHF3、CF4、 Ar、N2電漿蝕刻該BARC層。而蝕刻後之BARC層及TEOS 層便可在光阻去除後用來做為複晶矽層之蝕刻罩幕。在 這個發明中，由於BARC層及TEOS層係利用高選擇比 之反應氣體以兩段蝕刻的方式定義圖案，因此BARC層 表面的缺陷開口便不會過渡蝕刻至複晶矽層，並在複晶 矽蝕刻時傷害到底下元件。 另外，為避免罩幕層（BARC層及TEOS層）蝕刻時 複晶矽層（或其表面之金屬矽化物層）產生針孔現象，本 (請先閲讀背面之注意事項再填寫本頁) ,ιτ 線- 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X 297公釐） 42183 t 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（3 ) 發明首先利用〇2、扎為反應氣體電漿蝕刻Barc層。〇2、 % 了做為電|钱刻b ARC層之反應氣體’但卻對te〇S 層具有極高之選擇比。因此，BARC層的蝕刻可以有效 地停在TEOS層表面且不對TEOS層造成過渡蝕刻破壞。 接著’再利用CHFS ’ CF4，Ar，％為反應氣體電漿蝕刻 TEOS層。在這個步驟中，由於TE〇s層表面並不會因 先鈿之B ARC層餘刻而造成裂口，因此複晶石夕層（或金屬 矽化物層）表面亦，不會有明顯之針孔現象。 為讓本發明之上述目的、特徵、和優點能更明顯易 懂’下文特舉一較佳實施例，並配合所附圖式，作詳細 說明如下： 圖式說明 第1A〜1D圖係習知進行罩幕氧化層银刻及複晶石夕 蝕刻時，形成針孔及矽凹洞的剖面示意圓；以及 第2A〜2F圖係本發明進行罩幕氧化層蝕刻及複晶 矽蝕刻時，形成針孔及矽凹洞的剖面示意圖。 符號說明 10半導體基板；12氡化層；u複晶矽層； 16金屬矽化物層；18 TEOS層；20 BARC層； 22光阻層；24裂口； 26針孔；28凹洞； 3〇半導體基板；32氧化層；3，複晶矽層； 36金屬矽化物層；38 TEOS層；40 BARC層； 42光阻層；44，46裂口； 48針孔；以及 50凹洞。 本紙張尺度適用中國國家標準（CNS ) A4規格（：21〇X297公釐} (請t閲讀背面之注意事項再填寫本頁) - 言 42 183 1 A7 B7 五、發明説明（4 ) 實施例 請參考第2A〜2F圖，此為本發明進行罩幕氧化層 蝕刻及複晶矽蝕刻時，形成針孔及矽凹洞的剖面示意圖。 如第2A圖所示，半導體基板30(如矽基板）上具有 一廣氧化物3 2。I化層3 2表面則形成一被触刻層，如 欲進行蝕刻之複晶矽層34。複晶矽層34表面具有一層 改善電性用戽金屬矽化物層36丨如矽化鎢層。而金屬矽 化物層3 6表面則依序形成一餘刻終止層及一遮蔽層，如 TEOS層38及BARC層40。TEOS層38係罩幕蝕刻時 之終止層。而BARC層40則具有抗反射之特性，可改 進微影製程之準確性。BARC層40表面具有缺陷裂口 44 ° 經濟部中央標準局員工消费合作社印製 (請先閲讀背面之注意事項再填寫本頁) 接著，在遮蔽層（BARC層40)表面形成既定圖案之 罩幕層，如光阻層42。並以光阻層42為罩幕、利用02、 N2择反應氣體電漿蝕刻BARC層40。在這個步驟中，由 於02、N2可做為電漿蝕刻BARC層40時之反應氣體且 對TEOS層38具有極高之選擇比，因此這個步驟可有效 地將蝕刻停在TEOS層40表面且不在TEOS層表面造成 嚴重傷害。如圖所示，TEOS層38會在對應裂口 24之 位置得到一裂口 26，然其深度因02、N2的選擇钱刻 可^^口 24島淺。、A7 B7 421831 V. Explanation of the invention (!) The present invention relates to a method for reducing the phenomenon of pits, and in particular to a two-stage epitaxial mask oxide layer to reduce the semiconductor substrate in the polycrystalline lithography Method of pitting phenomenon. Please k: Please refer to the notes on 1¾ and refer to Figures 1A to 1D again. This is a schematic cross-sectional view of forming metal silicide pinholes and semiconductor substrate recesses when performing conventional mask oxide etching and polycrystalline silicon etching. In FIG. 1A, a semiconductor substrate 10 (such as a silicon substrate) has a layer of oxide 12 thereon. A polycrystalline silicon layer 14 is formed on the surface of the vaporization layer π to be etched. The surface of the polycrystalline silicon layer µ has a metal petrochemical layer 16 for improving electrical properties, such as a tungsten silicide layer. An oxide layer composed of TEOS layer 18 and BARC j 20 is formed on the surface of metal silicide layer 16 in order, which is used as a mask for polycrystalline stone. The surface of the B ARC layer 20 has a crack 24 due to a material defect. In the first place, a photoresist with a defined pattern was formed on the surface of the oxide layer of the mask 22. Then, the BARC layer 20 and the TEOS layer 18 are etched using the photoresist 22 as the mask and π *, Ar, and rhenium plasma as the reactive gas plasma to define the pattern of the oxide layer on the mask. In this step, since the Ch, Ar, and N2 plasma can etch the BARC layer 20 and the TEOS layer 18 at the same time, the part of the crack 24 will be in the metal oblique hole 26 due to the transition, as shown in Fig. 1B. Next, the photoresist layer 22 is removed, and the mask oxide layer (including the BARC layer 20 and the TE0S layer 18) after the etching gas is used as the mask and the metal silicide layer 16 and the polycrystalline silicon layer are etched with plasma as the reaction gas. 14, thereby completing the etching of the polycrystalline silicon layer 14, as shown in FIG. In this step, the paper standard iS Caiguanjia County (CNS) A4 · (2T〇i ^ i7 421831 Printed by the Bayer Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs f. A7 B7 V. Description of the invention (2) Due to metal silicide Layer 16 has been damaged during the previous mask oxide etching process (with pinholes 26), so C1 will also be etched at the corresponding positions of the oxide layer 12 and the semiconductor substrate 10, creating unwanted recesses 28 to damage circuit components. As shown in Figure 1D. In view of this, the main object of the present invention is to provide a manufacturing method for reducing the phenomenon of pits during etching, which can effectively prevent silver during the engraving of the mask layer (TEOS layer and BARC layer). The pinhole phenomenon on the surface of the polycrystalline stone (metallic oxide compound layer), thereby avoiding the pitting phenomenon of the semiconductor substrate when the polycrystalline silicon is etched. To achieve the above and other objectives, the present invention provides a method for etching polycrystalline silicon. A manufacturing method for reducing the pit phenomenon. This method firstly provides a polycrystalline silicon layer to be etched on a silicon substrate, and the surface may have a metal silicide for improving electrical properties. Then, the polycrystalline silicon layer is provided on the silicon substrate. The TEOS layer and the BARC layer for anti-reflection are sequentially formed on the surface. The BARC layer has a photoresist with a defined pattern on the surface. Then, using this photoresist as a mask, the BARC layer is etched with 02 and N2 plasma, and CHF3, CF4, Ar, and N2 plasma etch the BARC layer. The etched BARC layer and TEOS layer can be used as an etching mask for the polycrystalline silicon layer after the photoresist is removed. In this invention, since the BARC layer and the The TEOS layer uses a high selectivity reaction gas to define the pattern in two stages of etching, so the defect openings on the surface of the BARC layer will not be etched to the polycrystalline silicon layer and damage the underlying components during the polycrystalline silicon etching. In order to avoid the pinhole phenomenon of the polycrystalline silicon layer (or the metal silicide layer on the surface) during the etching of the cover layer (BARC layer and TEOS layer), please read the precautions on the back before filling this page. Line-This paper size applies Chinese National Standard (CNS) Λ4 specification (210X 297 mm) 42183 t Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (3) The invention first uses 〇2, and is used as a response Gas Plasma Etching Barc 〇2,% is used as electricity | money engraving b ARC layer reaction gas', but has a very high selectivity for the te〇S layer. Therefore, the etching of the BARC layer can effectively stop on the TEOS layer surface and does not affect the TEOS The layer caused transient etching damage. Then 're-use CHFS' CF4, Ar,% as a reactive gas plasma to etch the TEOS layer. In this step, the surface of the TE0s layer will not be affected by the rest of the BARC layer. As a result of cracks, the surface of the polycrystalline stone layer (or metal silicide layer) will not have obvious pinholes. In order to make the above-mentioned objects, features, and advantages of the present invention more obvious and easy to understand, one of the following is enumerated. The preferred embodiment and the accompanying drawings are described in detail as follows: Schematic illustrations 1A to 1D are conventionally used to form a pinhole and a silicon cavity when performing silver etching of a mask oxide layer and polycrystalline stone etch. The cross-sections are schematic circles; and FIGS. 2A to 2F are schematic cross-sectional views of pinholes and silicon recesses formed during mask oxide etching and polycrystalline silicon etching according to the present invention. DESCRIPTION OF SYMBOLS 10 semiconductor substrate; 12 siliconized layer; u polycrystalline silicon layer; 16 metal silicide layer; 18 TEOS layer; 20 BARC layer; 22 photoresist layer; 24 slit; 26 pin hole; 28 recess; 30 semiconductor Substrate; 32 oxide layer; 3, polycrystalline silicon layer; 36 metal silicide layer; 38 TEOS layer; 40 BARC layer; 42 photoresist layer; 44, 46 slits; 48 pinholes; and 50 recesses. This paper size applies to Chinese National Standard (CNS) A4 specifications (: 21 × 297 mm) (please read the notes on the back and fill in this page)-Yan 42 183 1 A7 B7 V. Description of the invention (4) Examples please Referring to Figs. 2A to 2F, this is a schematic cross-sectional view of pinholes and silicon recesses formed during mask oxide layer etching and polycrystalline silicon etching according to the present invention. As shown in Fig. 2A, a semiconductor substrate 30 (such as a silicon substrate) There is a wide oxide 32 on the surface of the I2 layer 32. A etched layer is formed on the surface of the polycrystalline silicon layer 34. The polycrystalline silicon layer 34 has a layer of hafnium metal silicide for improving electrical properties. Layer 36 丨 is like a tungsten silicide layer. On the surface of metal silicide layer 36, a stop layer and a shielding layer are formed in sequence, such as TEOS layer 38 and BARC layer 40. TEOS layer 38 is a stop layer during mask etching. . And the BARC layer 40 has anti-reflective properties, which can improve the accuracy of the lithography process. The surface of the BARC layer 40 has defect cracks 44 ° Printed by the staff consumer cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling in This page) Next, shape the surface of the masking layer (BARC layer 40) A mask layer of a predetermined pattern, such as a photoresist layer 42. The photoresist layer 42 is used as a mask, and the BARC layer 40 is etched using a 02, N2 selective reactive gas plasma. In this step, 02 and N2 can be used as electricity. The reactive gas when the BARC layer 40 is etched by slurry and has a very high selection ratio to the TEOS layer 38, so this step can effectively stop the etching on the TEOS layer 40 surface and not cause serious damage to the TEOS layer surface. As shown in the figure, TEOS The layer 38 will get a crack 26 at a position corresponding to the crack 24, but its depth can be engraved by the choice of 02 and N2.
接著，以罩幕層（光阻層42)及遮蔽層（BARC層40) 為罩幕、利用CHF3、CF4、Ar、N2為反應氣體電漿蝕刻 TEOS層38，如第2B圖所示。在這個步驟中，由於TEOS 本紙張尺度適用中國國家標準（CNS ) Λ4规格（2]〇X297公釐） 42183 1 A7 B7 五、發明説明（5 ) 層38表面裂口 26已在前述步驟中利用高選擇比反應電 漿予以改善，因此，TEOS層38覆蓋之金屬矽化物層％ 表面就可以得到更淺之針孔48，如第2C圖所示。 隨後’如第2D及2E圖所示’去除光阻層42，並 利用蝕刻後之遮蔽層及蝕刻終止層（BARC層40及TEOS 層38)為罩幕、利用C1為反應電漿蝕刻金屬矽化物層36 及複晶石夕層3 4 ’藉以完成複晶石夕層3 4之银刻，如第2F 圖所示。在這個步驟中，由於金屬矽化物層36之針孔48 已在先前罩幕氧化層的#刻步驟中大致消除，因此C1電 漿蝕刻便較易控制停止在氧化層32及半導體基板30表 面，使電路元件免受凹洞破壞。 綜上所述，在本發明方法中，金屬矽化物層的針孔 現象可在罩幕層餘刻步驟時預先減低，因此複晶石夕钮刻 時半導體基板之凹洞現象便可隨之消除。 雖然本發明已以較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此項技藝者，在不脫離本發明 之精神和範圍内，當可作更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者為準。 (諳先閱讀背面之注意事項再填寫本頁〕 ^91. -* 線 經濟部中央標举局貝工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（2]0X 297公t)Next, the TEOS layer 38 is etched by using the mask layer (photoresist layer 42) and the shielding layer (BARC layer 40) as the mask and using CHF3, CF4, Ar, N2 as the reactive gas plasma, as shown in FIG. 2B. In this step, since the TEOS paper size applies the Chinese National Standard (CNS) Λ4 specification (2) × 297 mm 42183 1 A7 B7 V. Description of the invention (5) The surface crack 26 of the layer 38 has been used in the previous step. It is selected to be better than the reaction plasma. Therefore, the surface of the metal silicide layer covered by the TEOS layer 38 can obtain shallower pinholes 48, as shown in FIG. 2C. Subsequently, as shown in FIGS. 2D and 2E, the photoresist layer 42 is removed, and the masking layer and the etching stop layer (BARC layer 40 and TEOS layer 38) after etching are used as a mask, and the silicidation of the metal is etched using C1 as a reactive plasma. The object layer 36 and the polycrystalite layer 34 are used to complete the silver engraving of the polycrystalite layer 34, as shown in FIG. 2F. In this step, since the pinholes 48 of the metal silicide layer 36 have been substantially eliminated in the previous step of the mask oxide layer, the C1 plasma etching is easier to control and stop on the surface of the oxide layer 32 and the semiconductor substrate 30. Protects circuit components from dents. In summary, in the method of the present invention, the pinhole phenomenon of the metal silicide layer can be reduced in advance during the remaining step of the mask layer, so that the pitting phenomenon of the semiconductor substrate can be eliminated during the polycrystalline stone lithography. . Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make changes and retouching without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application. (谙 Please read the precautions on the back before filling in this page] ^ 91.-* Printed by the Central Bureau of Standards of the Ministry of Online Economy, Shellfisher Consumer Cooperative, this paper is printed in accordance with China National Standard (CNS) A4 (2) 0X 297 g )