TW420869B - 3D memory module and the semiconductor device using the same - Google Patents

3D memory module and the semiconductor device using the same Download PDF

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Publication number
TW420869B
TW420869B TW087103161A TW87103161A TW420869B TW 420869 B TW420869 B TW 420869B TW 087103161 A TW087103161 A TW 087103161A TW 87103161 A TW87103161 A TW 87103161A TW 420869 B TW420869 B TW 420869B
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Taiwan
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wafer
semiconductor
semiconductor device
carrier
circuit pattern
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TW087103161A
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Chinese (zh)
Inventor
Naoji Senba
Yuzo Shimada
Ikusi Morizaki
Hideki Kusamitu
Makoto Ohtsuka
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Nippon Electric Co
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H—ELECTRICITY
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
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    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
    • H05K7/02—Arrangements of circuit components or wiring on supporting structure
    • H05K7/023—Stackable modules
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0652—Bump or bump-like direct electrical connections from substrate to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Semiconductor Memories (AREA)
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Abstract

A 3D memory module comprises: a plurality of semiconductor devices with both neighbored semiconductor devices stacked and connected through the penetration holes by block connection method. Each of the plurality of semiconductor devices comprises carriers with circuit patterns and the penetration holes connecting to the circuit patterns. The semiconductor device comprises at least one semiconductor memory chip mounted on the carrier so that the semiconductor memory chips are connected to the circuit pattern and at least one semiconductor chip for chip selection are installed on the carrier to connect to the circuit pattern so that the chip selection semiconductor chip can select the semiconductor memory chip.

Description

420869 經濟部中央梯準局買工消費合作社印^ A7 --———^ __ 五、發明説明（i ) " ~~~ — 本發明係有關三維記憶模組及使用該模組之半導體 裝置，特別係有關包括半導體記憶晶片以及至少一個晶 片選擇晶片之三維記憶模組及使用該模組之半導體裝 置。 ^ 包括一晶片選擇晶片之習知三維積體電路裝置係揭 露於日本公開專利案件中（JP-A-Heisei 5_1217丨3)。圖丄 顯示習知之三維積體電路裝置之概要結構。 參考圖1 ，三維積體電路裝置具有一疊片結構，該 疊片結構係包括將放大型光元件以矩陣形式安排於其中 而當成第一層之光感測層41，當當第二層之A/D轉換層 42，以及當成第三層之算術邏輯處理層43。光感測層ο 内之各光7L件之閘f位係保持於電洞累積電位該電洞 累積電位係因為光人射而造成之電洞累積所造成之累積 電位。因此’可能在不損壞電洞累積量下讀取信號，也 就是資料。藉由選擇電路之增加，可實現全單片ic結構 之三維積體電路裝置。在三維積體電路裝置中，放大型 光几件係用於造成隨機存取之可能性，使得信號能由排 於矩陣中之任一光元件中讀取出。 圖2顯示圖丨所示之三維積體電路裝置之結構例。 參考圖2，二維積體電路裝置係包括光接收區2〇，水平 描掃電路21，垂直描掃電路22 ’電壓產生電路23，定 時控制器32，類比數位轉換器33 ，緩衝暫存器％， CPU35 ’ 5己憶體36 ’輸出入缓衝器37，定時控制器38， 位址解碼器39以及斷路控制 〇。 本纸張尺度通用中® } (請先聞讀背面之注意事項再填寫本百ζ 丁 •-ίι420869 Printed by the Central Consumers ’Association of the Ministry of Economic Affairs and the Consumers’ Cooperatives ^ A7 --———— ^ __ V. Description of the Invention (i) " ~~~ — The present invention relates to a three-dimensional memory module and a semiconductor device using the module In particular, it relates to a three-dimensional memory module including a semiconductor memory chip and at least one chip selection chip, and a semiconductor device using the module. ^ A conventional three-dimensional integrated circuit device including a chip selection chip is disclosed in a Japanese published patent case (JP-A-Heisei 5_1217 丨 3). Figure 丄 shows the general structure of a conventional three-dimensional integrated circuit device. Referring to FIG. 1, the three-dimensional integrated circuit device has a laminated structure including a light-sensing layer 41 as a first layer in which magnified light elements are arranged in a matrix form, and an A of a second layer / D conversion layer 42 and arithmetic logic processing layer 43 serving as a third layer. The gate f position of each light 7L piece in the light sensing layer ο is maintained at the cumulative potential of the hole. The cumulative potential of the hole is the cumulative potential caused by the accumulation of the hole caused by the light beam. Therefore, it is possible to read the signal, that is, the data, without damaging the accumulation of holes. With the addition of the selection circuit, a three-dimensional integrated circuit device with a fully monolithic IC structure can be realized. In the three-dimensional integrated circuit device, several pieces of amplified light are used to cause the possibility of random access, so that the signal can be read by any optical element arranged in the matrix. FIG. 2 shows a structural example of the three-dimensional integrated circuit device shown in FIG. Referring to FIG. 2, the two-dimensional integrated circuit device includes a light receiving area 20, a horizontal scanning circuit 21, a vertical scanning circuit 22 'a voltage generating circuit 23, a timing controller 32, an analog digital converter 33, and a buffer register. %, The CPU 35'5 has a memory 36 'input / output buffer 37, a timing controller 38, an address decoder 39, and a disconnection control. This paper is standard in size ®} (Please read the precautions on the back before filling in this page.)

• I HI• I HI

I I I -I 經濟部中央標準局員工消費合作社印製 A7 ----—______________ B7 五、發明説明（2 ) ~~ ~~ ---- 因為圖2所示之電路之操作與本發明無關，詳細操 作將給予省略。 如前所述，具有晶片選擇晶片之習知三維積體電路 裝置係使用全單片ic結構。因此，為製造具有所需記憶 體電容之二維積體電路裝置，必需由單片IC之設計開 始。 同樣地，當圮憶體之電容需要有比現有之記憶體之 電容更大時，必要發展單片1C之新製程。 然而’對單片1C之新製程之發展與單片1C之發展 而S，需要有較進步之技術，長期生長時期以及大量資 源。 本發明係解決該問題。因此，本發明之目的在提供 一種併用晶片選擇晶片之三維記憶模組以及使用該三維 記憶模組之半導體裝置，其可不需進步技術與長期生成 時期。 本發明之另一目的在於提供一種使用併用晶片選擇 曰3片之該二維§己憶模組之半導體裝置，其可用低成本製 造出。 為達成本發明之觀點’三維記憶模組包括複數羊導 體裝置單位’各兩兩相鄰之半導體裝置單位彼此係用塊 形連接法，經由通孔而堆疊連接一起。複數半導體裝置 單位之每一個包括具有電路圖樣與連接至該電路圖樣之 通孔之載體，安置於該載體上之至少一個半導體記憶晶 片，使得該半導體記憶晶片係連接至該電路圖樣，以及 5 本紙張尺度適用中國國家標準（CNS ) Λ4规格（210Χ29?公釐） (請先閱讀背面之注意事項再填寫本頁) 11Τ 經濟部中央標準局員工消費合作社印裝 -^ Ο 8 ο 9 J '·' Α7 _______ 五、發明説明（3 ) 安置於該載體上之至少一個晶片選擇半導體晶片，其連 接至該電路圖樣，使得該晶片選擇半導體晶片能選擇該 半導體記憶晶片。 載體具有一空腔’晶片選擇半導體晶片可能安置於 載體之空腔中。在此情況下’該至少一半導體記憶晶片 可安排成經由絕緣樹脂而蓋覆該晶片選擇半導體晶片。 同樣地，當各半導體裝置單位包括複數半導體記憶 晶片’該複數半導體記憶晶片較好安排成使得，晶片選 擇半導體晶片至該複數半導體記憶晶片間之距離為最 短。 為達成本發明之另一目的，三維記憶模組包括複數 半導體裝置單位，各兩兩相鄰之半導體裝置單位彼此係 用塊形連接法’經由通孔而堆疊連接一起。複數半導體 裝置單位之每一個，而非一特殊半導體裝置單位，包括 具有第一電路圖樣與連接至該第一電路圖樣之通孔之載 體，以及至少一個半導體記憶晶片安置於該載體上。該 特殊半導體裝置單位包括具有第二電路圖樣與連接至第 二該電路圖樣之通孔之載體，以及安置於該載體上之至 少一個片選擇半導體晶片’其連接至該第二電路圖 樣，使得該晶片選擇半導體晶片能選擇該複數半導體裝 置單位之一’而非該特殊半導體裝置單位，之該半導體 記憶晶片。 為達成本發明之又另一目的，一半導體裝置，包括 具有第一電路圖樣之電路板，以及安置於該電路板上而 本紙張尺度適用中國國家標隼（CNS)A4規格（210Χ 297公释) (請先閱讀背而之注意事項再4杇本頁III -I Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 -------- ______________ B7 V. Description of the Invention (2) ~~ ~~ ---- Because the operation of the circuit shown in Figure 2 has nothing to do with the present invention, Detailed operations will be omitted. As mentioned earlier, the conventional three-dimensional integrated circuit device having a wafer selection wafer uses a fully monolithic IC structure. Therefore, in order to manufacture a two-dimensional integrated circuit device having a required memory capacitance, it is necessary to start with the design of a monolithic IC. Similarly, when the capacitance of the memory is required to be larger than that of the existing memory, it is necessary to develop a new process of 1C. However, the development of the new process of the single chip 1C and the development of the single chip 1C requires more advanced technology, long-term growth period and a lot of resources. The present invention addresses this problem. Therefore, an object of the present invention is to provide a three-dimensional memory module using a chip selection chip and a semiconductor device using the three-dimensional memory module, which do not require advanced technology and long-term generation period. Another object of the present invention is to provide a semiconductor device using the two-dimensional §memory module, which uses three wafers to select and use, which can be manufactured at low cost. In order to achieve the viewpoint of the invention, the three-dimensional memory module includes a plurality of sheep semiconductor device units. Each of the two adjacent semiconductor device units is connected to each other by a block connection method, and stacked and connected together through a via hole. Each of the plurality of semiconductor device units includes a carrier having a circuit pattern and a through hole connected to the circuit pattern, at least one semiconductor memory chip disposed on the carrier, so that the semiconductor memory chip is connected to the circuit pattern, and 5 books Paper size applies Chinese National Standard (CNS) Λ4 specification (210 × 29? Mm) (Please read the notes on the back before filling out this page) 11Τ Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economy-^ Ο 8 ο 9 J '·· Α7 _______ 5. Description of the invention (3) At least one wafer selection semiconductor wafer placed on the carrier is connected to the circuit pattern so that the wafer selection semiconductor wafer can select the semiconductor memory wafer. The carrier has a cavity ' wafer selection. The semiconductor wafer may be placed in the cavity of the carrier. In this case, the at least one semiconductor memory wafer may be arranged to cover the wafer selection semiconductor wafer via an insulating resin. Similarly, when each semiconductor device unit includes a plurality of semiconductor memory wafers, the plurality of semiconductor memory wafers are preferably arranged such that the distance between the wafer selection semiconductor wafer and the plurality of semiconductor memory wafers is the shortest. In order to achieve another object of the present invention, the three-dimensional memory module includes a plurality of semiconductor device units, and each pair of adjacent semiconductor device units is connected to each other in a stacked manner by a block connection method through via holes. Each of the plurality of semiconductor device units, rather than a special semiconductor device unit, includes a carrier having a first circuit pattern and a through hole connected to the first circuit pattern, and at least one semiconductor memory chip is disposed on the carrier. The special semiconductor device unit includes a carrier having a second circuit pattern and a through-hole connected to the second circuit pattern, and at least one piece selection semiconductor wafer disposed on the carrier, which is connected to the second circuit pattern such that the Wafer selection A semiconductor wafer can select one of the plurality of semiconductor device units' instead of the special semiconductor device unit, the semiconductor memory wafer. In order to achieve yet another object of the present invention, a semiconductor device includes a circuit board having a first circuit pattern, and the paper size is adapted to the Chinese National Standard (CNS) A4 specification (210 × 297). ) (Please read the back precautions before 4 杇 this page

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"I 經濟部中央標準局貝工消費合作社印掣 “ 2 Ο 8 6 g」碥 ^ A 7 —------------ B7 五'發明説明（4) * ~ 連接至該第一電路圖樣之複數三維記憶模組。各個三維 °己隐模組包括複數半導體裝置單位，藉由塊形連接法而 將每兩兩相鄰之半導體裝置單位經由通孔而堆疊連接一 起。各複數半導體裝置單位包括具有第二電路圖樣與連 接至該第二電路圖樣之通孔之載體，至少一半導體記憶 晶片，其安置於該載體上’使得半導體記憶晶片連接至 該第二電路圖樣，以及至少一晶片選擇半導體晶片，其 安置於载體上，連接至該第二電路圖樣，使得該晶片選 擇半導體晶片能選擇該丰導體記憶晶片。 為達成本發明之又另一目的，一半導體裝置包括具 有第一電路圖樣之電路板’以及安裝在該電路板上並連 接至該第一電路圖樣之複數三維記憶模組。各該複數三 維記憶模組包括複數半導體裝置單位，各兩兩相鄰之半 導體裝置單位係由塊形連接法而經由通孔而堆疊連接 著。各複數半導體裝置單位’而非一特殊半導體裝置單 位’包括具有第二電路圖樣之載體以及連接至該第二電 路圖樣之通孔，以及至少一半導體記憶晶片安裝於該載 體上’使得該半導體記憶晶片連接至該第二電路圖樣。 該特殊半導體裝置單位包括具有第三電路圖樣之電路 板’連接至該第三電路圖樣之通孔，以及至少一晶片選 擇半導體晶片’其安裝於該裁體上以連接至該第三電路 圖樣，使得該晶片選擇半導體晶片能選擇該複數半導體 裝置單位之一’而非該特殊半導體裝置單位，之半導體 吞己憶晶片。 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公釐〉 (請先閱讀背面之注意事項再填寫本頁) 、*! ^ ：ΐ： OSS 9 A7 B7 經濟部中央標準局貞工消费合作社印製 五、發明説明（5) -- 圖式簡述： 圖1係描繪併用晶片選擇晶片之一種習知三維積體 電路裝置之結構圖； 圖2係描緣併用晶片選擇晶片之一種習知 電路裝置之電路圖； 圖3 A與3B係本發明之第_眘丨Λ 弟貫施例中，併用晶片選 擇晶片之記憶單位之結構之平面圖與剖面圖； 圖3C係—維,5己憶組模之側視圖，其中圖3 a與π所 示之二維記憶單位係堆疊起來； 圖3D係具有SIMM結構之半導體裝置之平面圖’其 中圖3C所示之半導體裝置係以直線排列； ' 圖4A與4B係分別為本發明之第二實施例中，使用 於三維記憶模組中之晶片選擇單位之結構之平面圖與剖 面圖； 圖4C係使用圖4A與4B所示之晶片選擇單位之三维 記憶模組之侧視圖； 圖4D係具有SIMM結構之半導體裝置之平面圖，其 中圖4C所示之半導體裝置係以直線方式排列； 圖5A係本發明之第三實施例中，併用晶片選擇晶片 之三維記憶單位之結構之平面圖； 圖5B係三維記憶模組之結構之剖面圖，其中將圖 所示之本發明之第三實施例之三維記憶單位堆疊起來； 圖6係本發明之第四實施例之併用晶片選擇晶片之 三維記憶單位之結構之平面圖； (請先閱讀背面之注意事項再填ϊΐτ本頁) .I— - 11" I Printed by the Central Standards Bureau of the Ministry of Economic Affairs of the Shellfish Consumer Cooperative "2 Ο 8 6 g" 碥 A 7 —------------ B7 Five 'Invention Description (4) * ~ Link to The plurality of three-dimensional memory modules of the first circuit pattern. Each three-dimensional hidden module includes a plurality of semiconductor device units, and every two or two adjacent semiconductor device units are stacked and connected together through a via hole by a block connection method. Each of the plurality of semiconductor device units includes a carrier having a second circuit pattern and a through-hole connected to the second circuit pattern, and at least one semiconductor memory chip disposed on the carrier so that the semiconductor memory chip is connected to the second circuit pattern, And at least one wafer selection semiconductor wafer is disposed on the carrier and connected to the second circuit pattern, so that the wafer selection semiconductor wafer can select the abundant conductor memory chip. To achieve another object of the present invention, a semiconductor device includes a circuit board having a first circuit pattern 'and a plurality of three-dimensional memory modules mounted on the circuit board and connected to the first circuit pattern. Each of the plurality of three-dimensional memory modules includes a plurality of semiconductor device units, and each of the two adjacent semiconductor device units is connected in a stack by a block connection method through a through hole. Each of the plurality of semiconductor device units 'rather than a special semiconductor device unit' includes a carrier having a second circuit pattern and a through-hole connected to the second circuit pattern, and at least one semiconductor memory chip is mounted on the carrier, so that the semiconductor memory A chip is connected to the second circuit pattern. The special semiconductor device unit includes a circuit board having a third circuit pattern 'through-holes connected to the third circuit pattern, and at least one wafer selection semiconductor wafer' mounted on the body to be connected to the third circuit pattern, This enables the wafer selection semiconductor wafer to select one of the plurality of semiconductor device units, rather than the special semiconductor device unit, of a semiconductor memory chip. This paper size applies to the Chinese National Standard (CNS) Λ4 specification (210X297 mm) (Please read the precautions on the back before filling this page), *! ^: Ϊ́: OSS 9 A7 B7 Zhengong Consumer Cooperative, Central Standards Bureau, Ministry of Economic Affairs Printed 5. Description of the invention (5)-Brief description of the diagram: Figure 1 is a structural diagram of a conventional three-dimensional integrated circuit device depicting and using a wafer to select a wafer; FIG. 2 is a conventional method of describing a margin and using a wafer to select a wafer The circuit diagram of the circuit device; Figures 3A and 3B are the plan and cross-sectional views of the structure of the first and the second embodiment of the present invention, and the chip is used to select the memory unit of the chip; Figure 3C-Dimensions, 5 Jiyi Group A side view of the mold, in which the two-dimensional memory units shown in Fig. 3a and π are stacked; Fig. 3D is a plan view of a semiconductor device having a SIMM structure 'wherein the semiconductor device shown in Fig. 3C is arranged in a straight line;' Fig. 4A And 4B are respectively a plan view and a sectional view of a structure of a wafer selection unit used in a three-dimensional memory module in the second embodiment of the present invention; FIG. 4C is a three-dimensional memory using the wafer selection unit shown in FIGS. 4A and 4B mold Fig. 4D is a plan view of a semiconductor device having a SIMM structure, wherein the semiconductor devices shown in Fig. 4C are arranged in a straight line; Fig. 5A is a third embodiment of the present invention, and a wafer is used to select a three-dimensional memory unit of the wafer A plan view of the structure; FIG. 5B is a cross-sectional view of the structure of the three-dimensional memory module, in which the three-dimensional memory units of the third embodiment of the present invention shown in the figure are stacked; FIG. 6 is a combination of the fourth embodiment of the present invention The plan view of the structure of the three-dimensional memory unit of the chip selection chip; (Please read the precautions on the back before filling this page). I—-11

i I - IIi I-II

In 本紙張尺度適用中國囷家標準（CNS ) Λ4規播（210X297公犮）In This paper size applies to Chinese Standards (CNS) Λ4 regulation broadcast (210X297)

經濟部中央標準局負工消费合作社印S 42 086 9」省 Μ --______________B7 五、發明説明（6 ) 圖7A與7B係本發明之第五實施例之併用晶片選擇 晶片之三維記憶單位之結構之平面圖與剖面圖； 圖8 A與8B係本發明之第六實施例之併用晶片選擇 晶片之三維記憶單位之結構之平面圖與剖面圖； 圖9係本發明之三維記憶模組之—例之電路圖；以 及 圖10係本發明中，使用於三維記憶模組之記憶裝置 之圖示。 符號說明 1〜載體；2〜堆疊墊；3〜晶片選擇晶片；4〜記憶晶 片；5〜樹脂；6、7〜塊狀接合物：8〜母板；1〇〜電路板 較佳實施例 將參考所附圖示來詳細描敘本發明之併用晶片選擇 晶片之三維記憶模組。 首先’將描敘本發明之第一實施例之三維記憶模 組。圖3 A與3B係本發明之第一實施例中，併用晶片選 擇晶片之記憶單位之結構之平面圖與剖面圖。圖3C係三 維記憶組模之侧視圖，其中圖3A與3B所示之三維記憶 單位係堆疊起來。圖3D係具有SIMM結構之半導體裝 置之平面圖’其中圖3C所示之半導體裝置係以直線方式 排列。 參考圖3A與3B ’載體1具有電路圖樣（未示出）以及 堆疊墊2。晶片選擇晶片3與記憶晶片4係安裝於載體1 上，並使用塊狀接合物6而連接至載體1之電路圖樣。 本纸張尺度適用中國國家標率（CNS ) A4規格（210X297公釐） (锖先閱讀背而之注項再填寫本頁)Printed by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives S 42 086 9 "Province M-______________ B7 V. Description of the Invention (6) Figures 7A and 7B show the structure of a three-dimensional memory unit using a chip selection chip in the fifth embodiment of the present invention 8A and 8B are plan and sectional views of the structure of a three-dimensional memory unit using a wafer selection chip in a sixth embodiment of the present invention; and FIG. 9 is an example of the three-dimensional memory module of the present invention. Circuit diagram; and FIG. 10 is a diagram of a memory device used in the three-dimensional memory module in the present invention. DESCRIPTION OF SYMBOLS 1 ~ carrier; 2 ~ stacking pad; 3 ~ wafer selection wafer; 4 ~ memory wafer; 5 ~ resin; 6, 7 ~ block joint: 8 ~ mother board; 10 ~ circuit board A detailed description of the three-dimensional memory module of the present invention using a chip selection chip is made with reference to the accompanying drawings. First, a three-dimensional memory module of the first embodiment of the present invention will be described. 3A and 3B are a plan view and a cross-sectional view showing the structure of a memory unit of a chip selected by a chip in the first embodiment of the present invention. Fig. 3C is a side view of a three-dimensional memory module, in which the three-dimensional memory units shown in Figs. 3A and 3B are stacked. Fig. 3D is a plan view of a semiconductor device having a SIMM structure, wherein the semiconductor devices shown in Fig. 3C are arranged in a straight line. 3A and 3B ', the carrier 1 has a circuit pattern (not shown) and a stacked pad 2. The wafer selection wafer 3 and the memory wafer 4 are mounted on the carrier 1 and are connected to the circuit pattern of the carrier 1 using a block-shaped joint 6. This paper size applies to China National Standards (CNS) A4 specifications (210X297 mm) (锖 read the back note before filling in this page)

丁 -'S 經濟部中央摞準局—工消費合作社印絮 Α7 Β7 五、發明説明（ 載體！具有複數個堆㈣2，如前所述。某些或全部之 複數堆疊墊2係經由載體1之背表面所提供之通孔而連 接至墊肖樣地，塊狀接合物6係由樹脂$所密封以 造單一記憶單位。 时其次’如圖3C所示，如上所製造出之複數單一記憶 單位係經由堆疊墊2與塊狀接合物7而堆疊於母板8上， 以形成多層半導體裝置， 肋·衣直’也就是此例中之三維記憶模 組。 ^ 在第f施例中’單—記憶晶片與單-晶片選擇晶 片係安裝於單-載體U。在此結構之案例中，圖从與 3B所不之記憶單位之應用性變得非常高。 圖3〇描繪將圓3C所示之三維記憶模組以直線形式 排列於電路板10上以形成SIMM之結構圖。在此例中， 各具有晶片選擇晶片之四個三維記憶單位係堆疊起來。 要注意的是，雖然三維記憶模組係安裝在電路板之 一側，二維記憶模組也可安裝於電路板之兩側。 圖4A與4B係本發明之第二實施例中，使用於三維 記憶模組中之晶片選擇晶片之平面圖與剖面圖。晶片選 擇晶片3係安裝於載體11 i，使得晶片選擇晶片3經由 塊狀接合物6而連接至載體u之電路圖樣。載體n具有 連接至電路圓樣之堆疊墊2，如第一實施例般。堆疊墊2 係用於將記憶單位堆疊起來，在各記憶單位中，記憶晶 片係安裝於載體上，如第一實施例般。同樣地，塊狀接 合物6係由具絕緣性質與抗濕氣性質之樹脂所密因 __ 10 ^紙張尺度適财國國家ΛΤ^Γλ4規格~T1^X297,讀 1 (請先間讀背面之注意事項再填寫本瓦)Ding-'S Central Bureau of Standards of the Ministry of Economic Affairs-Industrial and Consumer Cooperatives Print A7 B7 V. Description of the invention (Carrier! With multiple stacks 2 as described above. Some or all of the multiple stacking pads 2 pass through the carrier 1 The through hole provided on the back surface is connected to the pad, and the block-shaped joint 6 is sealed with resin $ to make a single memory unit. Secondly, as shown in FIG. 3C, a plurality of single memory units manufactured as above It is stacked on the mother board 8 through the stack pad 2 and the block-shaped joint 7 to form a multi-layer semiconductor device, and the ribs are straight, which is the three-dimensional memory module in this example. ^ In the f-th embodiment, the single —The memory chip and the single-chip selection chip are mounted on the single-carrier U. In the case of this structure, the applicability of the memory unit from 3B is very high. Figure 30 depicts the circle 3C The three-dimensional memory module is arranged in a linear form on the circuit board 10 to form a SIMM structure diagram. In this example, four three-dimensional memory units each having a chip selection chip are stacked. It should be noted that although the three-dimensional memory module The system is mounted on the circuit board On the side, the two-dimensional memory module can also be installed on both sides of the circuit board. Figures 4A and 4B are a plan view and a sectional view of a wafer selection chip used in the three-dimensional memory module in the second embodiment of the present invention. Chip selection The wafer 3 is mounted on the carrier 11 i so that the wafer selection wafer 3 is connected to the circuit pattern of the carrier u via the block-shaped joint 6. The carrier n has a stacking pad 2 connected to a circuit-like pattern, as in the first embodiment. Stacking The pad 2 is used for stacking the memory units. In each memory unit, the memory chip is mounted on a carrier, as in the first embodiment. Similarly, the block joint 6 is made of insulating and moisture-resistant properties. Resin Secret __ 10 ^ Paper size is suitable for the country of wealth ΛΤ ^ Γλ4 specification ~ T1 ^ X297, read 1 (please read the precautions on the back before filling in this tile)

經濟部中央標準局貝工消費合作，杜印褽 A7 B7 五、發明説明（8) 此，係形成晶片選擇單位，並使用於三維記憶模組中。 圖4C係，當將3個記憶單位以及併用晶片選擇晶片 3之晶片選擇單位經由使用堆疊墊以及塊狀接合物7而 堆疊在母板8上時，以形成三維記憶模组之左視圖，其 中各記憶單位係併用一個記憶晶片4。在此例中，單一 晶片選擇晶片3係提供於各堆疊結構中。在此結構中， 效率變得非常高。 圖4D顯示將圖4C所示之三維記憶模組以直線形式 排列於電路板10上以形成SIMM模組之結構。 要注意的是，雖然三維記憶模組係安裝於電路板之 —側’三維記憶模組也可安裝於電路板之兩側。 圖5A係本發明之第三實施例之記憶單位之平面 圖。在第三實施例中之記憶單位中，單一晶片選擇晶片3 與四個記憶晶片4係經由塊狀體而安裝於多重晶片型載 體12上。塊狀體係由樹脂$所密封。因此，形成記憶單 位。連接至多重晶片型載體12上之電路圖樣之堆疊墊2 係用於堆疊記憶單位。 圖5B係當四個記憶單位經由使用堆疊墊與塊狀接 合物7與堆疊於母板8上時，三維記憶模組之側視圖。 在此例中，四個記憶晶片與—個晶片選擇晶片係安 裝在多重晶片型載體12上。在此結構中，同質性變得非 常高’記憶容量也可大大增加。 圖6係描敘本發明之第四實施例之三維記憶單位之 平面結構之平面圖。在圖6中，顯示多重晶片型載體12 11 Μ氏張尺度適用中_家標準（CNS )如規格（2Ι〇χ 297公赴 (諳先閱讀背面之注意事項再填寫本頁)Cooperating with Shellers and Consumers of the Central Standards Bureau of the Ministry of Economic Affairs, Du Yinji A7 B7 V. Description of Invention (8) This is to form a chip selection unit and use it in a three-dimensional memory module. FIG. 4C is a left view of a three-dimensional memory module when three memory units and a wafer selection unit of the wafer selection wafer 3 are stacked on the mother board 8 by using a stacking pad and a block-shaped joint 7. Each memory unit uses a memory chip 4 in combination. In this example, a single wafer selection wafer 3 is provided in each stacked structure. In this structure, the efficiency becomes very high. FIG. 4D shows the structure of arranging the three-dimensional memory module shown in FIG. 4C on the circuit board 10 in a straight line to form a SIMM module. It should be noted that although the three-dimensional memory module is installed on the side of the circuit board, the three-dimensional memory module can also be installed on both sides of the circuit board. Fig. 5A is a plan view of a memory unit according to a third embodiment of the present invention. In the memory unit in the third embodiment, a single wafer selection wafer 3 and four memory wafers 4 are mounted on a multi-wafer type carrier 12 via a block. The block system is sealed with resin $. Therefore, a memory unit is formed. The stack pad 2 connected to the circuit pattern on the multi-chip type carrier 12 is used for stacking memory units. FIG. 5B is a side view of the three-dimensional memory module when four memory units are stacked on the mother board 8 by using a stack pad and a block-shaped connector 7. In this example, four memory chips and one wafer selection chip are mounted on the multi-wafer type carrier 12. In this structure, the homogeneity becomes very high 'and the memory capacity can also be greatly increased. Fig. 6 is a plan view describing a planar structure of a three-dimensional memory unit according to a fourth embodiment of the present invention. In FIG. 6, the multi-chip carrier 12 11 Μ Zhang scale is applicable in China _ home standards (CNS) such as specifications (2Ιχχ 297) (谙 Please read the precautions on the back before filling this page)

A7 B7 經滴部中央標準局員工消費合作社印聚 五、發明説明（9 ) 上之記憶晶片4與晶片選擇晶片3之最佳排列。在此例 中’由晶片選擇晶片3至記憶晶片4之繞線長度變為最 短》因此，可實現三維記憶模組之高速操作。 圖7A係本發明之第五實施例中，三維記憶模组之半 導體裝置單位之平面圖。圖7B係本發明之第五實施例 中，沿著三維記憶模組之半導體裝置單位之線c_c‘之剖 面圖。 由圖7B可看出’空腔π係提供於載體1中。晶片 選擇晶片3係安装於空腔13中，並經由塊狀體，電路圖 樣以及塊狀體而連接至記憶晶片4。然後，晶片選擇晶 片3係經由具有絕緣與抗濕性質之樹脂而密封。在此時， 密封用之樹脂5係填滿於空腔13中，使得樹脂5之頂表 面不超過載體1之表面外。 其次’記憶晶片4係用相同於第一實施例之方法， 而經由塊狀體而安裝在載體1上。在此之後，塊狀體係 由樹脂5所密封。 根據此結構，可實現具有小尺寸、重量輕以及高密 度之半導體裝置。在此種結構之例中，空腔13之數量係 不受限於一個。如果需要的話，可提供更多數量之空腔 13 - 圖8Α係本發明之第六實施例中，三維記憶模組之半 導體裝置單位之平面圖。圖8Β係本發明之第六實施例 中，沿著三維記憶模組之半導體裝置單位之線D-D‘之剖 面圖。 ί#先閲讀背面之注意事項再填涔本I ) .丁 ，-* 本紙張尺度適用中國國家標準（CNS ) Λ4規格UlOx297公舞） 經濟部中央橾準局員工消費合作社印製 42 086 9 ^ A7 ______B7 五、發明説明（1〇 ) 由圖8B可看出’空腔13係提供於多重晶片型載體 12中。晶片選擇晶片3係安裝於空腔13中，並經由塊狀 體’電路圖樣以及塊狀體而連接至記憶晶片4。然後， 晶片選擇晶片3係經由具有絕緣與抗濕性質之樹脂而密 封。在此時’密封用之樹脂5係填滿於空腔π中，使得 樹脂5之頂表面不超過載體1之表面外。 其次’記憶晶片4係用相同於第四實施例之方法， 而經由塊狀體而安裝在載體1上。在此之後，塊狀體係 由樹脂5所密封。 根據此結構’可實現具有小尺寸、重量輕以及高密 度之半導體裝置。在此種結構之例中，如果需要的話， 可提供更多數量之空腔，更多之晶片選擇晶片以及更多 之記憶晶片。 其次，圖9顯示根據本發明之實施例，併用晶片選 擇晶片之三維記憶模組之等效電路圖。參考圖9，—個 RAM模組，D424400，可由NEC公司獲得，係當成記憶 晶片4使用，而可由NEC公司獲得之晶片選擇晶片係當 成晶片選擇晶片3。圖1〇顯示記憶晶片4之接腳之詳細 連接情形。 如前所述，根據本發明，在量產中之更多晶片與晶 片選擇晶片係經由倒裝片連接法而連接至載體，以形成 單一半導體裝置單位。複數半導體裝置單位係經由使用 塊狀物而堆疊與連接。因此，併用晶片選擇晶片之三維 記憶模組可在下一代產品中，㈣時間與低成本而實 ____ 13 本纳Γ張尺度適用中國國家標準（CNS ) Λ4規格---- (請先閱讀背面之注意事項再填寫本頁)A7 B7 Printed by the Consumers' Cooperative of the Central Standards Bureau of Didi Ministry 5. The best arrangement of the memory chip 4 and the chip selection chip 3 on the description of invention (9). In this example, the winding length from the wafer selection wafer 3 to the memory wafer 4 becomes the shortest. Therefore, the high-speed operation of the three-dimensional memory module can be realized. Fig. 7A is a plan view of a semiconductor device unit of a three-dimensional memory module in a fifth embodiment of the present invention. Fig. 7B is a cross-sectional view of the semiconductor device unit line c_c 'in the fifth embodiment of the present invention. It can be seen from FIG. 7B that the cavity π is provided in the carrier 1. The wafer selection wafer 3 is mounted in the cavity 13 and is connected to the memory wafer 4 via a block, a circuit pattern, and a block. Then, the wafer selection wafer 3 is sealed by a resin having insulation and moisture resistance properties. At this time, the resin 5 for sealing is filled in the cavity 13 so that the top surface of the resin 5 does not exceed the surface of the carrier 1. Secondly, the 'memory chip 4' is mounted on the carrier 1 via a block in the same manner as in the first embodiment. After that, the block system is sealed with resin 5. According to this structure, a semiconductor device having a small size, light weight, and high density can be realized. In the example of such a structure, the number of the cavities 13 is not limited to one. If necessary, a larger number of cavities 13 may be provided. Fig. 8A is a plan view of a semiconductor device unit of a three-dimensional memory module in the sixth embodiment of the present invention. Fig. 8B is a sectional view taken along the line D-D 'of the semiconductor device unit of the three-dimensional memory module in the sixth embodiment of the present invention. ί # Please read the notes on the back before filling in this copy I). Ding,-* This paper size applies to China National Standard (CNS) Λ4 Specification UlOx297 Public Dance) Printed by the Central Consumers Bureau of the Ministry of Economic Affairs Consumer Cooperatives 42 086 9 ^ A7 ______B7 5. Description of the invention (10) It can be seen from FIG. 8B that the 'cavity 13 is provided in the multiple wafer type carrier 12. The wafer selection wafer 3 is mounted in the cavity 13 and is connected to the memory wafer 4 via a block body 'circuit pattern and the block body. Then, the wafer selection wafer 3 is sealed by a resin having insulation and moisture resistance properties. At this time, the resin 5 for sealing is filled in the cavity? So that the top surface of the resin 5 does not exceed the surface of the carrier 1. Next, the 'memory chip 4' is mounted on the carrier 1 via a block in the same manner as in the fourth embodiment. After that, the block system is sealed with resin 5. According to this structure, a semiconductor device having a small size, light weight, and high density can be realized. In the example of such a structure, if necessary, a larger number of cavities, more wafer selection wafers, and more memory wafers can be provided. Next, FIG. 9 shows an equivalent circuit diagram of a three-dimensional memory module using a chip selection chip according to an embodiment of the present invention. Referring to FIG. 9, a RAM module, D424400, can be obtained from NEC company as a memory chip 4, and a wafer selection wafer obtained from NEC company can be used as a wafer selection chip 3. Fig. 10 shows the detailed connection of the pins of the memory chip 4. As described above, according to the present invention, more wafers and wafer selection wafers in mass production are connected to a carrier via a flip-chip connection method to form a single semiconductor device unit. A plurality of semiconductor device units are stacked and connected by using a block. Therefore, the three-dimensional memory module that uses the chip selection chip can be used in the next generation of products with time and low cost. (Notes on the back then fill out this page)

，1T Ύ s J磡. A7 _____—___B7 五、發明説明（u) -- 現’以獲得所需之記憶容量。 (讀先閱讀背面之注意事項再填寫本頁) 同樣地，可用數種方法以將晶片選擇晶片安裝在载 體上，使得單一晶片選擇晶片可安裝在單一栽體上，使 得單一晶片選擇晶片係提供有複數堆疊形半導體裝置單 位，或使得單一晶片選擇晶片能在多晶片型載體上有複 數記憶晶片。因此，可根據所需之記憶容量，封裝密度， 尺寸與重量等等，而在數種安裝晶片選擇晶片方法中選 擇其中一種。 ' 甚至’本發明之併用晶片選擇晶片之三維記憶模組 不需要習知技術所需之進步技術’長生成時間與大量資 源專等。因此’在下一代產品中之大記憶容量之單片ic， 係以併用晶片選擇晶片之三維記憶模組之形式，而在短 生長時期與低成本下實現。 雖然本發明已以較佳實施例描敘於上，然其並非用 以限制本發明，本發明之精神與範圍當視後附之申請專 利範圍。 經濟部中央標準局負工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公釐）, 1T Ύ s J 磡. A7 _____—___ B7 V. Description of the Invention (u)-Now ’to obtain the required memory capacity. (Read the precautions on the back before you fill out this page.) Similarly, there are several ways to mount a wafer selection wafer on a carrier, so that a single wafer selection wafer can be mounted on a single carrier, so that a single wafer selection wafer system A plurality of stacked semiconductor device units are provided, or a single wafer selection wafer can have a plurality of memory wafers on a multi-wafer type carrier. Therefore, you can choose one of several mounting chip selection chip methods based on the required memory capacity, package density, size and weight, etc. 'Even' The three-dimensional memory module of the present invention which uses a chip to select a chip does not require the advanced technology required by the conventional technology 'long generation time and a large number of resources. Therefore, the single-chip IC with a large memory capacity in the next-generation product is realized in the form of a three-dimensional memory module using a chip selection chip in combination with a short growth period and low cost. Although the present invention has been described in the preferred embodiments, it is not intended to limit the present invention. The spirit and scope of the present invention should be regarded as the scope of the attached patent. Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Consumer Cooperatives. This paper size applies to the Chinese National Standard (CNS) Λ4 specification (210X297 mm).

Claims (1)

第871齊1-亂I®充 年871rd Qi 1-Chaos I® Year 號申請專利範圍修正本A8 DO /1.2 0RG 9 ^ B8 C8 D8 修正日期：88·07.08 經濟部t央揉準局負工消费合作社印策 利範圍 1. 一種三維記憶模組，包括： 複數個堆疊半導體裝置單位，兩兩相鄰之半導體裝 置單位彼此經由通孔和塊形連接而堆疊連接一起， 其中各兩兩相鄰之半導體裝置單位包括： 一載體’其具有電路圖樣與連接至該電路圖樣之該 通孔； 至少一個半導體記憶晶片，其安置於該載體上，使 得該半導體記憶晶片係連接至該電路圖樣；以及 至少一個晶片選擇半導體晶片，其安置於該載體上 而連接至該電路圖樣，使得該晶片選擇半導體晶片能選 擇該半導體記憶晶片。 2·如申請專利範圍第1項之三維記憶模組，其中該 載體更包括一空腔，晶片選擇半導體晶另係安置於該載 體之該空腔之表面上。 3-如申請專利範圍第2項之三維記憶模組，其中該 至少一半導體記憶晶片可安排成經由絕緣樹脂而蓋覆 該晶片選擇半導體晶片》 4·如申請專利範圍第1項之三維記憶模組，其中各 半導體裝置單位包括複數半導體記憶晶片，該複數半導 體記憶晶片之安排使得，該晶片選擇半導體晶片與該複 數半導體記憶晶片間之繞線長度為最小。 5.—種半導體裝置，包括： 一電路板，具有第一電路圖樣；以及 複數三維記憶模組，如申請專利範圍第丨項至第4 15 ΜΛ張尺度速用中國g家樣準（cns ) Α4規格（210Χ297公釐 1.-------------A------訂------咬 — (請先閑讀背面之注$項再填寫本頁)No. Application for Patent Scope Amendment A8 DO /1.2 0RG 9 ^ B8 C8 D8 Revision Date: 88.07.08 Ministry of Economic Affairs, Central Government Procurement Bureau, Consumer Work Cooperative, India, Scope of Reliability 1. A three-dimensional memory module, including: multiple stacks Semiconductor device units, two adjacent semiconductor device units are stacked and connected to each other via vias and block connections, wherein each two adjacent semiconductor device units include: a carrier having a circuit pattern and connected to the circuit pattern The through hole; at least one semiconductor memory chip disposed on the carrier so that the semiconductor memory chip is connected to the circuit pattern; and at least one wafer selection semiconductor wafer disposed on the carrier and connected to the circuit pattern , So that the wafer selection semiconductor wafer can select the semiconductor memory wafer. 2. The three-dimensional memory module according to item 1 of the patent application scope, wherein the carrier further includes a cavity, and the semiconductor wafer selected by the wafer is disposed on the surface of the cavity of the carrier. 3- If the three-dimensional memory module of item 2 of the patent application scope, wherein the at least one semiconductor memory chip can be arranged to cover the wafer with an insulating resin to select the semiconductor wafer. In the group, each semiconductor device unit includes a plurality of semiconductor memory wafers, and the arrangement of the plurality of semiconductor memory wafers is such that a winding length between the wafer selection semiconductor wafer and the plurality of semiconductor memory wafers is minimized. 5. A semiconductor device comprising: a circuit board having a first circuit pattern; and a plurality of three-dimensional memory modules, such as the scope of application for patents from item 丨 to the 4 15 ΜΛ Zhang scale quick-use Chinese family standard (cns) Α4 Specification (210 × 297 mm 1 .------------- A ------ Order ------ Bite— (Please read the note $ on the back side first and then fill out this page) 穴、申請專利範圍 --— 經濟部t央榡率局貝工消費合作社印装 項之任-顧述者，安裝於職此平行㈣路板上，並 連接至該第一電路圊樣。 6.—種三維記憶模組，包括： 複數半導體裝置單位，各兩兩相鄰之半導體裝置單 位係用塊形經由通孔而堆叠連接一起， 其中’各該複數半導體裝置單位，而非—特殊 體裝置單位，包括： -載體’其具有第一電路圖樣以及連接至該第—電 路圖樣之該各半導體裝置單位之該通孔；以及 至少一個半導體記憶晶片，其安置於該載體上，使 得該半導體記憶晶片係連接至該第一電路圖樣， 其中’該特殊半導體裝置單位包括： 一載體，其具有第二電路圖樣以及連接至該第二電 路圖樣之該特原來半導體装置單位之該通孔；以及 至少一個晶片選擇半導體晶片，其安置於該載體上 而連接至該第一電路圖樣，使得該晶片選擇半導體晶片 忐選擇該複數半導體裝置單位之一，而非該特殊半導體 裝置單位’之該半導體記憶晶片。 7·如申請專利範圍第6項之三維記憶模組，其中該 特殊半導體裝置單位之該載體具有一空腔，該特殊半導 體裝置單位之該晶片選擇半導體晶片係安裝於該載體 之該空腔之表面上。 8-如申請專利範圍第7項之三維記憶模组，其中該 至少一半導體記憶晶片之排列係經由絕緣樹脂而覆蓋 T：--- 16 +舐饮尺度適用中國固家標準（CNS > A4規格（21〇χ297公釐） -------------'*"-__ (諳先閩讀背面之注項再填寫本夏) 訂 線 4 2 086 9 A8 B8 C8 _______D8 六、申請專利~~ 該晶片選擇半導體晶片。 9. 如申請專利範圍第6項之三維記憶模組，其中各 該半導體裝置單位包括複數半導記憶晶片，該複數半導 體記憶晶片-之排列使得該晶片選擇半導體晶片與該複 數半導記憶晶片間之距離為最小。 10. —種半導體裝置，包括： 一電路板，具有第一電路圖樣；以及 複數三維記憶模組，如申請專利範圍第6至第9項 之任一項所述者，安裝於該彼此平行的電路板上，並連 接至該第一電路圖樣。 (請先聞讀背面之注意事項再壤寫本頁} 經濟部肀失揉準局員工消费合作社印51 本紙張尺度適用中國國家標準（CNS ) Α4規格（210 X 297公嫠）Application scope of patents --- Any person who prints items of the Ministry of Economic Affairs of the Central Government Bureau of Bayong Consumer Cooperatives-installed on the parallel circuit board and connected to the first circuit sample. 6. A three-dimensional memory module, including: a plurality of semiconductor device units, each of which is adjacent to each other and connected in a block shape through a through hole, wherein each of the plurality of semiconductor device units is not a special A body device unit including: a carrier having a first circuit pattern and the through holes connected to the semiconductor device units of the first circuit pattern; and at least one semiconductor memory chip disposed on the carrier such that the The semiconductor memory chip is connected to the first circuit pattern, wherein 'the special semiconductor device unit includes: a carrier having a second circuit pattern and the through hole of the special original semiconductor device unit connected to the second circuit pattern; And at least one wafer selection semiconductor wafer, which is disposed on the carrier and connected to the first circuit pattern, so that the wafer selection semiconductor wafer 忐 selects one of the plurality of semiconductor device units instead of the semiconductor of the special semiconductor device unit Memory chip. 7. The three-dimensional memory module according to item 6 of the application, wherein the carrier of the special semiconductor device unit has a cavity, and the wafer selection semiconductor wafer of the special semiconductor device unit is mounted on the surface of the cavity of the carrier. on. 8- The three-dimensional memory module according to item 7 of the scope of the patent application, wherein the arrangement of the at least one semiconductor memory chip is covered by an insulating resin T: --- 16 + sip standards are applicable to Chinese solid standards (CNS > A4 Specifications (21〇χ297mm) ------------- '* " -__ (谙 Please read the notes on the back before filling in this summer) Line 4 2 086 9 A8 B8 C8 _______D8 6. Apply for a patent ~~ This chip selects a semiconductor wafer. 9. For example, the three-dimensional memory module of the patent application scope item 6, wherein each of the semiconductor device units includes a plurality of semiconductive memory chips, and the arrangement of the plurality of semiconductor memory chips is such that The distance between the wafer selection semiconductor wafer and the plurality of semiconducting memory wafers is the smallest. 10. A semiconductor device includes: a circuit board having a first circuit pattern; and a plurality of three-dimensional memory modules, such as the sixth in the scope of patent application Any one of the items described in item 9 is mounted on the parallel circuit boards and connected to the first circuit pattern. (Please read the precautions on the back before writing this page} The Ministry of Economy lost Rubbing the staff of the prospective bureau India 51 cooperatives paper scale applicable to Chinese National Standard (CNS) Α4 Specifications (210 X 297 male widow)
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US5973392A (en) 1999-10-26
KR100293775B1 (en) 2001-07-12
KR19980080562A (en) 1998-11-25
JP2964983B2 (en) 1999-10-18
JPH10284683A (en) 1998-10-23

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