A7 B7 五、發明说明（） 發明頜域：_ ^-- (請先聞讀背面之注意事項再填寫本頁) 本發明與一種半導體製程有關，特别是與可程式邏 輯電路（programmable logic)有關’更特别是一種防止 程式化電壓變異之金屬融絲製程。 發明背景： 目前積體電路體製程趨向於多重内連線之製作並且 半導體工業因爲技術的提昇而朝向將元件之尺寸縮小邁 進，當半導體元件不斷地縮小時，製程上之條件更趨向於 嚴苛。不論是微影解析度、或是触刻條件上都是一種新的 挑戰。所以在面對縮小化之趨勢下，各種製程之參數對於 元件特性均有一定程度之影響。若是無法控制參數於一定 範圍内，將可能造成良率的下降。 經濟部智慧財產局員工消費合作社印製 FPGA(field programmable gate array)或 field programmable logic之技術於最近受到十分之重視以及 投入研發。這些技術通常與反融絲電路或製程（antifuse) 有關’上述之反融絲電路通常連接於原先爲開路狀態 (open circuit)下之電路’但是經過—些技術之處理可以 選擇性地將上述原先之開路電路改變爲短路電路（sh〇rt circuit)。例如利用雷射加熱可以改變上述之開路狀態。 加偏壓方式也是在反融絲技術中一種常用之方法，此方法 主要是加上一電偏壓通過反融絲電路來形成原先爲開路 — 本紙張尺度適財關家梯準（CNS) A4規格（2淑297讀）-A7 B7 5. Description of the invention () Inventive jaw area: _ ^-(Please read the notes on the back before filling out this page) The present invention is related to a semiconductor process, especially to programmable logic 'More specifically, a metal fusion wire process that prevents stylized voltage variation. Background of the Invention: At present, the integrated circuit system process tends to produce multiple interconnects and the semiconductor industry is moving towards shrinking the size of components due to technological advances. When semiconductor components continue to shrink, process conditions tend to be more stringent. . It is a new challenge in both lithographic resolution and touch conditions. Therefore, under the trend of shrinking, the parameters of various processes have a certain degree of influence on the characteristics of the components. If it is impossible to control the parameters within a certain range, the yield may decrease. The technology of field programmable gate array (FPGA) or field programmable logic printed by employees' cooperatives in the Intellectual Property Bureau of the Ministry of Economic Affairs has recently received great attention and has been put into research and development. These technologies are usually related to anti-fuse circuits or processes. 'The above-mentioned anti-fuse circuits are usually connected to circuits that were previously in open circuit.' However, some technologies can selectively treat the original The open circuit is changed to a short circuit. For example, laser heating can be used to change the open circuit state. The bias method is also a commonly used method in anti-fuse technology. This method is mainly by adding an electrical bias to form an open circuit through the anti-fuse circuit. This paper is suitable for financial and economic standards (CNS) A4. Specifications (2 Shu 297 reading)-
420Ββ B Α7 Β7 五、發明説明（ 之電路爲短路狀態。此偏壓將使原先絶緣狀態之膜層改變 而導通。通常利用非晶形矽（amorphous silicon)來做爲 反融絲電路之材質，因此又可以稱做反融絲矽層 (antifuse silicon)。利用矽作爲融絲之材料主要是因爲 上述之非晶形矽具有較高之電阻値，但是經過熱處理以及 重新結晶（recry stalize)則其電阻値便會降低。在美國專 利 U. S. Patent No. 5,322,812，發明人爲 Dixit 的一 篇專利中已揭露一種製作反融絲矽層之方法。 經濟部智慧財產局員工消費合作社印製 在製作反融絲電路之過程中，在形成非晶形發層 圖索前，通常會製作金屬導電栓用以作爲電性傳導之 道*上述製程將於下所述。首先於基板2之上先行形 一金屬圖案4作爲電性連線。接著再於其上沈積—介 看6覆蓋金属圖案4作爲絶緣層。一般可以利用氧化物 氮化物、掺雜玻璃層或其他之類似材料達到上述之目的 接著再利用微影製程形成光阻圖案定義一窗孔之區域， 後利用蝕刻製程蝕刻該介電層6形成一窗孔以曝露梦 屬圖案4。再形成鎢導電栓之前，先行沈積—氮化蘇膜 8於窗孔之表面作爲黏著層用以增加後續钱之黏著 力。後績之製程爲形成一鎢金屬層10於介電層6之上 回填進入窗孔之中，藉由一化學機械研磨製程將位於介 層6上之鎢層1〇研磨去除進而形成金屬鎢栓1〇於^ 層6之中。如習知知技術所知，研磨過程之中必須 研衆等化學藥劑衆其表面平坦化。也有利用回蝕刻^ 之 通 成 電 而 金 層 能 並 電 電 利用 程將 —^· I— nii. ϋ n ϋ. 袖衣 ~~ n n ~"訂 (請先閲讀背面之注意事項再填寫本頁} 本紙張尺度遄用中國國家標準（CNS } A4规格（210><297私釐） 42 0B6 6 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（） 鎮回敍刻而達到製作嫣栓之目的。由於辑之晶粒較大，囡 此在回蝕刻或研磨後其截面分别示之於第二圖 A與B。 第二圖 A中爲利用回蝕刻製程所造除之截面，其將造成 鎢栓之過度蝕刻而凹凸不平，其表片平坦度十分差，造成 .後續之膜層不易達到良好之平坦表面。第二圖B中之斜 線區域將因W C Μ P而被移除。 是故，一般爲採用化學機械研磨製程將鎢層研磨， 但是由於鎢之晶粒較大，在研磨過程中容易在晶粒之交界 處沿著晶界而被移除形成小孔或隙缝1 3，示之於第二圖 Β。參閲第三圖，接下之步驟爲形成非晶型矽1 2與氮化 鈦14之圖案。由於小孔或隙缝13之存在，對於鎢栓之 垂直電阻將有區域上之不同，如此將會造成後續偏壓時產 生變異，造成小孔尖角部份提前開啓（turn on)，因此無 法有效控制程式化電壓値，進而降低元件之良率。 囡此，目前所需求的爲一種可以降低程式化電壓變 異之金屬融絲製程。 發明目的及概述： 本發明之主要目的在提供一種與FPGA有關之製作 方法。 本發明之另一目的爲提供一種反融絲電路之製作方 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 420BB6 ; A7 ________B7 五、發明説明（） 法。 本發明之再一目的爲提供一種降低程式化電壓變異 之金屬融絲製程。 在不限定本發明之精神之下，本發明實施例如下， 做爲電性連接之第一導電層利用沈積以及微影製程定義 其圖案形成於绝緣膜層之上。隨後第二絶緣膜層形成於第 一導電層之上以達到電性絶緣之目的。一窗孔藉由蝕刻形 成於絶緣膜之中。形成一氮化鈦於窗孔之表面用以增加後 續鎢栓之黏著性。隨後利用化學氣相沈積珐形成鴿金屬栓 於上述之窗孔之中做爲電性連接之橋樑。經過圖案化以及 平坦化過程可以將金屬栓定義於窗孔之肀。在經過化學機 械研磨過程造成之缺陷位於鎢栓之表面。沈積一氮化鈇填 補缺陷。沈積之氮化鈦具有較小之晶粒可以塡入其缺陷， 而且容易黏著於鎢材質之上。選用之氮化鈦在後續加熱過 程中’將與後續之非晶型矽產生化學反應而形成矽化金屬 (TiSix)而具有良好之導電性。已有專利使用二氧化矽填 補’絶緣體之·一乳化發在媽上容易制離，且使用〇xide CMP時，iMD在oxied CMP之研磨速度較快，易使鎢栓高 於IMD介電層之表面，造成缺陷。 J , 裝-------訂 (請先聞讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 ，反4 著成上 接完之 ， 上發 形融 氛 絲後可 融之了 反層除 I 發鈦 成絲化 之 屠 膜 緣 絶 二 第 之 述 上 於 層 絲之 融金 反合 在鋁 鈦或 化鋁 氮績 I 後 積與 沈梦 著爲 接作 ， 以 本紙張尺度適用t國國家梂準（CNS ) A4現格（210X297舍釐） 2 086 6 Α7 Β7 五、發明説明（） 阻障廣之外，其在加熱後也一並形成矽化金屬，增加導電 性。第二導電層如金屬或合金，形成於反融絲矽層之上， 隨後一抗反射層形成於第二導電層之上用以增加微影之 解析度’利用電漿蝕刻以定義金屬圖案於鎢栓之上。 圖式簡單說明： 第一圖爲傳統技術形成鎢栓之截面圖。 第二圖A以及第二圏b爲傳統技術造成鎢栓缺陷之截面 圖。 第三圖爲傳統技術形成反融絲矽層與氮化鈦之截面圖。 形成窗孔之截面圖。 第形成鎢栓與塡充薄膜之截面圖。 第六圖矣本發明之形成反融絲膜層之截面圖。 第七圖爲本發明之形成金屬圖案之截面圖。 發明詳細說明： 經濟部智慧財產局員工消旁合作社印製 鑑於傳統製程中，於製作反融絲（anti-fuse)製程時 易對於鎢栓造成缺陷，而導致無法控制其品質，囡此本發 明提供一種反融絲之製程以降低程式化電壓之變異，再者 更提供一種方法使得有關FPGA產品之反融絲電路之良 率穩定" 本紙張尺度適用中國國家標準（CNS ) Α4规格< 210X297必釐）420Bβ B Α7 Β7 V. Description of the invention (The circuit is short-circuited. This bias will change the original insulation film to be conductive. Usually amorphous silicon is used as the material of the anti-fuse circuit, so It can also be called antifuse silicon layer. The main reason for using silicon as the material for the fuse is that the above amorphous silicon has a higher resistance, but it has a resistance after heat treatment and recry stalize. It will be reduced. In US Patent No. 5,322,812, a patent inventor Dixit has disclosed a method for making anti-fuse silicon layer. The Intellectual Property Bureau of the Ministry of Economic Affairs's Consumer Cooperative printed on the production of anti-fuse circuit In the process, before forming an amorphous hair layer, a metal conductive plug is usually used as a way of electrical conduction. The above process will be described below. First, a metal pattern 4 is first formed on the substrate 2 as Electrical connection. Then deposit on it-see 6 to cover the metal pattern 4 as an insulating layer. Generally, oxide nitride, doped glass layer can be used Other similar materials achieve the above purpose, and then use a photolithography process to form a photoresist pattern to define an area of a window hole, and then use an etching process to etch the dielectric layer 6 to form a window hole to expose the dream pattern 4. Then form tungsten conductive Before bolting, first deposit a nitride film 8 on the surface of the window hole as an adhesive layer to increase the adhesion of subsequent money. The subsequent process is to form a tungsten metal layer 10 on the dielectric layer 6 and backfill the window hole. Among them, the tungsten layer 10 located on the interlayer 6 is ground and removed by a chemical mechanical polishing process to form a metal tungsten plug 10 in the layer 6. As is known in the prior art, during the grinding process, it is necessary to Yanzhong and other chemical agents have flattened their surfaces. There are also etch backs ^ to make electricity and the gold layer can be combined with electricity. The process will be-^ · I- nii. Ϋ n ϋ. Sleeve ~~ nn ~ " Order ( Please read the notes on the back before filling in this page} This paper size uses the Chinese national standard (CNS) A4 size (210 > < 297 private cents) 42 0B6 6 A7 B7 Description of the invention () It is engraved to achieve the purpose of making Yan bolts. Due to the large grain size of the series, the cross sections after etch back or grinding are shown in the second pictures A and B, respectively. The second picture A is made by the etch back process. The removed cross-section will cause excessive etching of tungsten plugs and unevenness, and the flatness of its surface is very poor, resulting in. The subsequent film layer is not easy to achieve a good flat surface. The oblique area in the second figure B will be due to WC P is removed. Therefore, the tungsten layer is generally ground by a chemical mechanical polishing process, but because the grain size of tungsten is large, it is easy to be removed along the grain boundary at the grain boundary during the grinding process. The small holes or slots 1 3 are shown in the second figure B. Referring to the third figure, the next step is to form a pattern of amorphous silicon 12 and titanium nitride 14. Due to the existence of the small holes or gaps 13, the vertical resistance of the tungsten plug will be different in area. This will cause variations in subsequent biases and cause the sharp corners of the small holes to turn on in advance, so it cannot be effective. Control the stylized voltage 进而 to reduce the yield of components. Therefore, what is currently required is a metal fusion process that can reduce the variation in stylized voltage. Object and Summary of the Invention: The main object of the present invention is to provide a manufacturing method related to FPGA. Another object of the present invention is to provide a producer of anti-fuse circuit (please read the precautions on the back before filling this page) The paper size is applicable to China National Standard (CNS) A4 specification (210X 297 mm) 420BB6; A7 ________B7 V. Description of invention () method. It is yet another object of the present invention to provide a metal melting wire process for reducing stylized voltage variation. Without limiting the spirit of the present invention, the embodiment of the present invention is as follows. As a first conductive layer for electrical connection, a pattern is formed on the insulating film layer by a deposition and lithography process definition. Then a second insulating film layer is formed on the first conductive layer to achieve the purpose of electrical insulation. A window hole is formed in the insulating film by etching. A titanium nitride is formed on the surface of the window hole to increase the adhesion of subsequent tungsten plugs. Subsequently, a chemical vapor deposition enamel was used to form a dove metal plug in the above window hole as a bridge for electrical connection. Through the patterning and planarization process, the metal bolt can be defined in the window hole. Defects caused by chemical mechanical grinding are located on the surface of the tungsten plug. A hafnium nitride is deposited to fill the defect. The deposited titanium nitride has smaller grains that can penetrate into its defects and easily adhere to the tungsten material. In the subsequent heating process, the selected titanium nitride will chemically react with the subsequent amorphous silicon to form a metal silicide (TiSix), which has good electrical conductivity. The existing patent uses silicon dioxide to fill the 'insulator'. An emulsified hair is easy to peel off, and when using 0xide CMP, the grinding speed of iMD in oxied CMP is faster, which makes the tungsten plug higher than the IMD dielectric layer. Surface, causing defects. J, Outfit ------- Order (please read the notes on the back before filling out this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. After the wire is melted, the layer is removed. I The titanium film is turned into a silky film. The second is described above. The fusion of the gold on the layer wire is combined with aluminum titanium or aluminum nitride. For this paper, the national standard (CNS) A4 is applicable (210X297 rounds) 2 086 6 Α7 Β7 V. Description of the invention () In addition to wide barriers, it also forms silicided metal after heating. To increase conductivity. A second conductive layer, such as a metal or an alloy, is formed on the anti-fuse silicon layer, and then an anti-reflection layer is formed on the second conductive layer to increase the lithography resolution. The plasma pattern is used to define the metal pattern on Tungsten plug. Brief description of the drawings: The first figure is a sectional view of a tungsten plug formed by a conventional technique. The second figure A and the second 圏 b are cross-sectional views of a tungsten plug defect caused by a conventional technique. The third figure is a cross-sectional view of a conventional technique for forming an anti-fuse silicon layer and titanium nitride. Form a cross-sectional view of the window hole. The first section is a cross-sectional view of the tungsten plug and the rhenium filling film. FIG. 6 is a cross-sectional view of the antifuse film layer of the present invention. The seventh figure is a cross-sectional view of a metal pattern formed in the present invention. Detailed description of the invention: Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. In the traditional manufacturing process, it is easy to cause defects in tungsten plugs during the production of anti-fuse process, resulting in the inability to control its quality. Provide an anti-fuse process to reduce the variation of the stylized voltage, and also provide a method to stabilize the yield of the anti-fuse circuit of the FPGA product. "This paper size applies the Chinese National Standard (CNS) Α4 specification" 210X297 must)
五、發明説明（ 經濟部智慧財產局員工消費合作社印製 第四圖爲本發明之半導體截面圖。一半導體基板 將做爲一實施例之説明，然於熟知該項技藝者所了解，任 何型態之半導體基板亦可以作爲一實施例，在不限定本發 明之精神之下以一晶向< 100 >之矽基板20做一説明。首 先，一膜層間之介電層（IL D) 2 2，可以利用化學氣相沈積 法形成於基板20之上做爲絶緣膜層《—般可以利用氧化 5夕或其他類似之氧化材料做爲絶緣膜層2 2，舉例而言， 可以利用化學氣相沈積法（CVD)以臭氧（ozone)、TEOS做 爲反應物形成氡化層（稱爲ozone-TEOS氧化層），也可 以利用高密度電漿製程形成，或者利用saline所形成之氧 化層形成於上述之複晶矽負載之上。TEO S -氧化層也可以 利用於本發明，利用低壓化學氣相沉積法（LPCVD)或電漿 增強化學氣相沉積法（PECVD)形成。然而此非本發明之重 點，不予以督述a 做爲電性連接之第一導電層24利用沈積以及微影製 程定義其圖案形成於上述之絶緣膜層22之上。一般可以 利用金屬或是合金來做爲上述之導電層24。此外利用摻 雜之複晶矽層亦可以做爲導電層。隨後第二絶緣膜層26 形成於第一導電層2 4之上以達到電性絶緣之目的。一窗 孔28藉由微影製程將第二絶緣膜層26蝕刻以形成於其中 並構成與第一導電看24連接之通道。 參閲第五囷A，完成窗孔28之製作後，先行形成一氮 本紙張尺度適用中國國家揉準（CNS ) A4規格（210X297>4^ ) {請先聞讀背面之注意事項再填寫本瓦) 裝- 訂 良 丨νί Α7 Β7 五、發明説明（) 化欽3 0於窗孔2 8之表面用以增加後續鶴栓之黏著性。隨 後利用化學氣相沈積法形成鎢金屬栓3 2於上述之窗孔2 8 之中做爲電性連接之橋樑。經過圖案化以及平坦化過程可 以將金屬栓32定義於窗孔28之中，一般爲利用化學機械 研磨製程。在經過化學機械研磨過程後，研磨造成之小孔 缺陷34位於鎢栓之表面。在形成反融絲之前先行沈積一 薄膜36用來填補小孔缺陷34。沈積之薄膜36必須具有較 小之晶粒可以填入其缺陷3 4 ’而且必須容易黏著於鎢材 質之上’經過本案發明人之實驗’以利用化學氣相沈積法 所形成之氮化鈥可以作爲填充薄膜，以化學氣相沈積之氣 化鈥爲較佳之選擇，其厚度約爲8〇〇至12〇〇埃之間，形 成之溫度約爲400至500度C，較佳爲450度》選用之氮化 鈦在後續加熱過程中’將與後續之非晶型矽產生化學反應 而形成石夕化金屬（TiSix)而具有良好之導電性。經過cmp 後’形成如第五圖B’ CMP將TiN (膜層36丨磨至鎢之表面。 經濟部智慧財產局WK工消費合作社印製 參閲第六圖’接著’形成_反融絲層38，舉一實施 例，可以沈積一非晶形矽層3 8於上述之第二絶緣膜層2 6 之上’此非晶形矽層38當作反融絲矽層{antifuse silicon)，反融絲矽層通常在目前爲開路狀態（〇pen circuit) ’但是在後續之步驟中經過處理可以選擇性地將 上述開路之反融絲矽層改變爲短路電路（sh〇rt circuit)。例如利用雷射加熱或是袍以偏壓通過反融絲發 層來形成短路狀態。上述之處理將使原先絶緣狀態之非晶 本紙张尺度適用中國國家標準（CNS ) Α4规格（210X297舍釐） A7 B7 經濟部智慧財產局員工消費合作杜印製 五、發明説明（ 形矽層改變電阻値，而轉變爲導通狀態。上述之非晶型矽 之厚度約爲7〇〇至800埃之間。 仍參閲第六圖，完成反融絲矽層38之後’接著沈 積一氮化鈦4 0在反融絲矽層之上。此氮化欽除了可以作 爲防止金屬層铭或鋁合金之擴散之外，其在加熱後也一並 形成矽化金屬，增加導電性。 第二導電層42如金屬或合金形成於反融絲石夕廣38之 上’以一實施例而言可以爲銘铜合金（AlCu)，隨後一抗反 射層44形成於第二導電層42之上用以增加微影之解析 度，一般可以利用氮化矽。—光阻圖索（未圖示）形成於其 上以定義其圈案。利用電漿蝕刻以光阻做爲蝕刻罩幕將第 二導電層4 2、氮化鈦4 〇以及反融絲矽層3 8蝕刻以形成金 屬圖案於鎢拴之上。經過本案之處理可以消除鎢栓之缺陷 並且可以在後續加熱過程中形成矽化金屬而增進導電 性β 如此將避免後續偏壓時產生之電壓變異，缝隙尖角 所造成之提前開啓（turn 011)將被消除，因此可以有效控 制程式化電壓値，進而提昇元件之良率。因此，本發明可 以降低程式化電壓變異之金屬融絲製程。 本發明以較佳實施例説明如上，而熟悉此領域技藝 本紙張纽ϋ财國國家標準（CNS ) Α4规格（210Χ297ϋ5~]· II—.L------裝------訂'------良 (請先閲讀背面之注意事項再填寫本頁) 五、發明説明（ A7 B7 潤增 動以 更可 許熱 些加 作及 可以 當性 ，著 内黏 圍據 範、 、 TJ 神 精 之 明 發 本 離 脱 不如 在例 者飾 粒 晶 用 利 明 發 本 卜定 專 程」域 低明領 降發同 來本等 質Φ']其 材限及 之以圍 性肖範 電非利 導，專 進例請 異 變 壓 電 化 舉申 一 之 爲附 鈦後 化視 氮當 而更 圍 範 護 保 考 (請先閲讀背面之注意事項再填寫本頁) :装- 訂 經濟部智慧財產局員工消費合作社印製 本紙張尺度通用中國國家標準（CNS M4規格（2toX297公釐）V. Description of the Invention (The fourth picture printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is a cross-sectional view of the semiconductor of the present invention. A semiconductor substrate will be used as an illustration of an embodiment. State semiconductor substrates can also be used as an example, without limiting the spirit of the present invention, a silicon substrate 20 with a crystal orientation of < 100 > will be described. First, a dielectric layer (IL D) between film layers 22, which can be formed on the substrate 20 as an insulating film layer by chemical vapor deposition method—in general, an oxide film or other similar oxide material can be used as the insulating film layer 2 2. For example, chemical Vapor deposition (CVD) uses ozone (ozone) and TEOS as reactants to form a tritium oxide layer (called an ozone-TEOS oxide layer). It can also be formed by a high-density plasma process or an oxide layer formed by a saline. It is formed on the above-mentioned polycrystalline silicon load. The TEO S-oxide layer can also be used in the present invention, and is formed by low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). However, this The point of the present invention is not described in detail a. As the first conductive layer 24 for electrical connection, the pattern is defined on the above-mentioned insulating film layer 22 by deposition and lithography processes. Generally, it can be made of metal or alloy. It is the above-mentioned conductive layer 24. In addition, a doped polycrystalline silicon layer can also be used as a conductive layer. Then a second insulating film layer 26 is formed on the first conductive layer 24 to achieve the purpose of electrical insulation. A window The hole 28 is etched by a lithography process to form a second insulating film layer 26 therein and forms a channel connected to the first conductive watch 24. Referring to the fifth 囷 A, after the fabrication of the window hole 28 is completed, a nitrogen is formed first. This paper size is applicable to Chinese National Standard (CNS) A4 (210X297 > 4 ^) {Please read the precautions on the back before filling in this tile) Binding-Book 丨 7 Β7 V. Description of the invention () Hua Qin 3 0 on the surface of the window hole 28 is used to increase the adhesion of the subsequent crane bolts. Subsequently, a tungsten metal plug 3 2 is formed by the chemical vapor deposition method in the window hole 2 8 as a bridge for electrical connection. The metal plug 32 can be defined in the window hole 28 through a patterning and planarization process, which is generally a chemical mechanical polishing process. After the chemical mechanical polishing process, the hole defects 34 caused by the polishing are located on the surface of the tungsten plug. A thin film 36 is deposited to fill the pinhole defects 34 before the antifuse is formed. The deposited film 36 must have smaller grains to fill its defects 3 4 'and must be easily adhered to the tungsten material' through the experiments of the inventor of this case 'to use the nitride formed by chemical vapor deposition. As a filling film, chemical vapor deposition is preferred. Its thickness is between 800 and 12,000 angstroms, and the temperature of formation is about 400 to 500 degrees C, preferably 450 degrees. " In the subsequent heating process, the selected titanium nitride will chemically react with the subsequent amorphous silicon to form a petrified metal (TiSix) and has good electrical conductivity. After the cmp, the formation is as shown in the fifth figure B. CMP grinds the TiN (film layer 36 丨 to the surface of tungsten. Printed by the WK Industrial and Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, see the sixth figure, “Next” to form an antifuse layer 38. As an example, an amorphous silicon layer 38 can be deposited on the second insulating film layer 2 6 described above. This amorphous silicon layer 38 is used as an antifuse silicon layer. The silicon layer is currently in an open circuit state. However, after the subsequent steps are processed, the open-circuit antifuse silicon layer can be selectively changed to a short circuit. For example, laser heating or robes are used to bias the anti-fuse hair layer to form a short circuit. The above-mentioned treatment will make the original insulating paper size applicable to the Chinese National Standard (CNS) A4 specification (210X297 centimeters) A7 B7 Printed by the consumer cooperation of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. The description of the invention (the shape of the silicon layer is changed) The resistance is changed to an on state. The thickness of the above-mentioned amorphous silicon is between about 700 and 800 angstroms. Still referring to the sixth figure, after the antifuse silicon layer 38 is completed, a titanium nitride is then deposited. 40 is on the anti-fuse silicon layer. In addition to preventing the diffusion of the metal layer or aluminum alloy, the nitride also forms a silicided metal after heating to increase the conductivity. The second conductive layer 42 For example, a metal or an alloy is formed on the anti-fused stone Xiguang 38 '. In one embodiment, it can be a copper alloy (AlCu), and then an anti-reflection layer 44 is formed on the second conductive layer 42 to increase the microstructure. The resolution of the shadow can generally be made of silicon nitride. A photoresist (not shown) is formed on it to define its case. Plasma etching is used to use the photoresist as an etching mask to place the second conductive layer 4 2. Etching of titanium nitride 4 0 and antifuse silicon layer 38 Engraved to form a metal pattern on the tungsten plug. After the treatment in this case, the defects of the tungsten plug can be eliminated and a silicided metal can be formed in the subsequent heating process to improve the conductivity β. This will avoid the voltage variation and gap tip generated during the subsequent bias. The turn-on (turn 011) caused by the angle will be eliminated, so the stylized voltage 値 can be effectively controlled, thereby improving the yield of the component. Therefore, the invention can reduce the stylized voltage variation in the metal melting process. The best embodiment is described above, and the paper is familiar with the art in this field. The paper is a national standard (CNS) Α4 specification (210 × 297ϋ5 ~). II—.L ------ installation ------ order '- ---- Good (please read the notes on the back before filling out this page) 5. Description of the invention (A7 B7 Runzeng to allow more hot additions and applicability, the inner sticking according to the standard, TJ The dedication of the demon's hair is not as good as the person who used the example to decorate the grain. Use the Mingming hair to make a special trip. "Yu Mingming leads the hair to send the same quality as the original Φ ']. Special cases, please change the piezoelectric The application of Huayi Shenyi is to protect the test after attaching titanium with nitrogen and nitrogen (please read the precautions on the back before filling out this page): Packing-Order the paper size printed by the Employees' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Common Chinese National Standard (CNS M4 specification (2toX297 mm)