TW410384B - Method of reducing the surface roughness of the poly silicon gate - Google Patents

Abstract

The importance of employing the dual gate structure of the poly silicon material on the device process of complementary metal oxide semiconductor (CMOS) transistor is increasing. However, the surface of the undoped poly silicon gate used in the present process is rough and adverse for the subsequent process. Therefore, the invention provides an improved method for reducing the surface roughness of the poly silicon gate. The deposition of a conformal dielectric layer on the rough surface of the undoped poly silicon layer is included. The process of argon sputter or argon/oxygen sputter is then used to strip the conformal dielectric layer stated above. The rough surface part of the undoped poly silicon layer is stripped at the same time such that the planar surface of poly silicon layer is formed and is favorable to the subsequent process of manufacturing transistor structure.

Description

------------- V. Description of the Invention α) [Field of the Invention] The present invention relates to the manufacture of semiconductor integrated circuits, and more specifically, the present invention relates to a method for reducing complex The method of rough surface crack of spar stone gate is suitable for the process of CMOS device with double doped gate structure to improve the surface caused by rough polycrystalline spar layer: the feature size (CD) is difficult to control when defining the pattern, Problems such as pits, insufficient insulation gap thickness, and uneven thickness of metal lithophytes are caused in the base after the remaining moments. [Explanation of the know-how] Complementary metal-oxide-semiconductor transistor (CMOS) is an important basic element in integrated circuit technology today, especially when the integrat ion of semiconductor elements is getting higher and higher in the past. The heat generated by the N-channel transistor (four 0S) due to a large amount of power consumption will relatively increase, which will reduce the stability and reliability of the device. Therefore, "CMOS devices with the advantages of low energy consumption" will follow the semiconductor The increase in the degree of accumulation has gradually replaced the status of NMOS, especially when the process technology enters the sub-micron or even finer size, and has become one of the mainstream technologies in the industry. The so-called complementary metal-oxide-semiconductor transistor, as its name implies, is another basic semiconductor element composed of a combination of complementary P-channel transistors and η-channel transistors. Among them, the gate electrode of the transistor element is usually made of polycrystalline silicon material. As the feature size of the element continues to shrink, in order to continue to provide sufficient conductivity, generally suitable impurities will be implanted into the process. The polycrystalline silicon layer t 'becomes a doped polycrystalline silicon gate electrode layer. In the past, no matter whether the P-channel transistor or the η-channel transistor's complex-crystal silicon gate electrode layer ’was implanted with the same conductivity type,

Page 4__ £ 10384 V. Description of the Invention (2) " ~ In accordance with the needs of the process, the so-called dual-gate technology (dual-gate) technology has also been developed, which is targeted at the p_ channel transistor complex The silicon layer is doped with a P-type impurity and the polycrystalline silicon layer for the n-channel transistor is doped with an n-type impurity. For clarity, please refer to Figures 1 to 10 below to explain the manufacturing process of the double-doped gate structure. First, as shown in FIG. 4, a thin insulating layer ^ and a polycrystalline silicon layer 12 are sequentially formed on a semiconductor substrate 10. For example, a thin silicon oxide layer is first formed by a thermal oxidation method or a deposition process 丨丨, covering the surface of the semiconductor substrate 10, and then depositing an undoped polycrystalline silicon layer 12 on the thin silicon oxide layer 11 by a chemical vapor deposition (CVD) process. In the figure, the left and right parts are shown for forming a p-channel transistor and an n-channel transistor, respectively. Secondly, referring to FIG. 1B, a conventional lithography imaging and etching process is performed to define the gate electrode layers 12a, 12b, and the gate insulating layer 11a, lib patterns. First apply a photoresist layer (not shown), perform an exposure and development step to define its pattern, and cover the area where the gate structure of the transistor element will be formed; then use this photoresist layer pattern as a mask to sequentially etch the non-doped The hetero-multicrystalline silicon layer 12 and the thin silicon oxide layer 11 are used to fabricate the gate structure of the transistor element. After the photoresist layer pattern is removed, the gate electrode layers 12a, 12b and the gate are left as shown in the figure. Electrode insulation layer 11a, lib pattern. Next, referring to FIG. 1C, a portion of the semiconductor substrate 10 is covered with a photoresist layer (not shown) pattern. For example, in the right half of the figure, η-type impurities are implanted to form η -A channel transistor; after removing the photoresist layer pattern, another photoresist layer pattern (not shown) is used to cover the semiconductor substrate

Page 5 410384 V. Description of the invention (3) The other part of the bottom 10 ', that is, the left half of the figure, is formed by p-type impurity implantation to form a p-channel transistor. . The implantation of the 'η-type impurity forms the n + complex silicon gate electrode layer i2b and the n + source / drain region 13b, and the implantation of the p-type impurity forms the p + complex silicon gate electrode layer 12a and n + source / drain region 13a. Since the polycrystalline silicon layer is doped with impurities of different conductivity types for transistors with different conductivity types, it is different from those using only one conductivity type impurity, so it is called a semiconductor transistor process with double doped gate structure. As mentioned above, in the process of double-doped gate structure transistors, an undoped polycrystalline silicon layer must be deposited before defining the required gate pattern for individual impurity implantation procedures. However, from many actual production results, it is found that the un-doped polycrystalline spar layer has a rough surface, which is not conducive to the implementation of subsequent process steps, which often affects the properties of product components. Please refer to Section 2A below. To the 2D figure, detail the problems caused by it. First, as shown in FIG. 2A, a thin oxide chip 21 and an undoped polycrystalline silicon layer 22 are sequentially formed on a semiconductor substrate 20, and the above-mentioned undoped layer is deposited by a CVD process. The hetero-polycrystalline silicon layer 22 has a relatively rough surface. A photoresist layer is coated on the surface of the undoped polycrystalline silicon layer 22, and a photoresist layer pattern 23 is defined by a lithography imaging procedure, leaving a region covered by a gate structure to be formed. Since the undoped polycrystalline silicon layer 22 has a rough surface and is not conducive to the execution of the exposure step, it is easy to affect the control of the feature size (CD) due to the reflection and interference on its surface, which reduces the precision of the lithography imaging process. Next, referring to FIG. 2B, the photoresist layer pattern 23 is used as a cover.

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Curtain 'is sequentially etched with undoped polycrystalline silicon layer 22 and thin silicon oxide layer 21 in order to define the gate electrode layer 22a and the gate insulating layer pattern. Among them, because the undoped polycrystalline spar layer 22 has a rough surface, which represents that the thickness of each part is not uniform: 'Therefore, the pace of removing the undoped polycrystalline silicon layer 22 can not be consistent, and the remaining knife etcher will Accelerating the etching along the depression of the undoped polycrystalline silicon layer 22 and finally causing pits 24 on the semiconductor substrate 20, which seriously damages the integrity of the device fabrication area, which is the second disadvantage. . Next, as shown in FIG. 2C, an insulating layer 25, such as a nitride layer, is deposited on the above-mentioned gate electrode layer 22a, the gate insulating layer pattern, and the exposed surface of the semiconductor substrate 20. Similarly, since the undoped polycrystalline dream layer 22 has a rough surface, the surface of the insulating layer 25 also has an uneven structure. Then, an anisotropic back-etching process is performed on the insulating layer 25, for example, a reactive ion etching (R) E process, to leave the insulating spacer 25a on the side wall of the gate electrode layer 22a, as in the 2D Shown in the picture. Among them, 'to ensure that the insulating layer 25 on the top of the gate electrode layer 22a can be completely removed', it needs to be etched, and as a result, the remaining thickness of the insulating spacer 25a is too small to provide enough Insulation effect. In addition to this, after the doped polycrystalline stone gate electrode layer 22a and the doped source / drain regions (not shown) are formed by implanting impurities of an appropriate conductive type, a self-alignment is usually performed. A salicide process to further improve conductive properties. However, again, since the polycrystalline silicon gate electrode layer 22a has a rough surface ', the thickness of the metal silicide layer generated by the reaction is uneven, which affects the conductive properties of the transistor element.

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V. Description of the invention (5) [Summary of the invention] In view of this, the main purpose of the present invention is to provide a method for reducing the surface roughness of a polycrystalline silicon gate, which is suitable for a double doped gate. Structured CMOS device manufacturing process to improve the surface caused by the rough surface of the polycrystalline silicon layer: the feature size (CD) is not easy to make when defining the pattern, the pits are formed on the substrate after the etching, and the thickness of the insulation gap is not ^ , And uneven thickness of metal dreams. In order to achieve the above and other objectives, the present invention proposes an improved method for reducing the coarseness of the surface of a polycrystalline stone gate, which adds a planarization dielectric layer on the rough surface of an undoped polycrystalline hard layer. dielectric), and then an argon or argon / oxygen sputtering process is used to describe the planarization dielectric layer, and a part thereof is carried out to form a flat complex crystal structure. In detail, the present invention proposes a method suitable for the following steps of a double doped gate: forming a thin insulating layer, an undoped polycrystalline layer on the above-mentioned thin surface; forming a planarized dielectric layer under an argon gas quenching (Ar sputter) or the above-mentioned planarized dielectric layer, and the surface portion is connected, leaving a flat un-doped flat undoped polycrystalline dream layer and a layer and a gate insulating layer; and implanting the undoped complex The spar layer is rough; the surface of the silicon layer is conducive to the subsequent fabrication of CMOS device processes that reduce the surface roughness of the polycrystalline silicon gate structure, including on the surface of a semiconductor substrate; forming an insulating layer, which has roughness The above-mentioned undoped polycrystalline silicon layer is implemented; a complex gas / oxygen base strike procedure is performed to remove and remove the rough superficial complex polycrystalline sand layer of the undoped polycrystalline silicon layer; and a thin insulating layer is selectively etched to form respectively Appropriate impurities of the gate electrode enter the above-mentioned gate electrode layer

Page 8 410384 V. Description of the invention (6) =, and it is not gated into a pair of doped source / drain regions on the surface of the semiconductor substrate, and it is better to implement the improved method according to the present invention. The applied # ^ 晶 / 结构 ° 层 # ^ & Comparative example, wherein the above thin insulating deposit (cvW) bed stone layer, the above undoped polycrystalline silicon layer is formed in a chemical vapor phase. In addition, The above-mentioned planarized dielectric layer system-hafnium oxide i! Is between 5 °° and 100 ° angstrom. Among them, the -iU deposition (SACVD) procedure is performed, and ozone-tetraethoxylithium (= EOS) is used as The above-mentioned silicon oxide layer is deposited by using raw materials; or the above-mentioned silicon oxide layer is formed by applying a plasma-enhanced chemical vapor deposition (PECVD) process or a low-pressure chemical gas "deposition (LPCVD) process; The slurry enhances the chemical vapor deposition (PECVD) process and uses the redundant method to form the silicon oxide layer described above. The conditions for carrying out the argon or argon / oxygen spattering procedure are as follows: the pressure is 0.4 mT, the temperature is room temperature, the power / bias power is 300/1 00w, and the spatter rate is 4 to 5 angstroms. /second. [Brief description of the drawings] In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below and described in detail with the accompanying drawings as follows: Sections 1A to 1 Figure 1C is a cross-sectional view of a series of semiconductor substrates, showing the manufacturing process of a CMOS device with a double-doped gate structure; Figures 2A to 2D are cross-sectional views of a series of semiconductor substrates, showing the conventional use of undoped complex crystals Shi Xijie's manufacturing process for the production of transistor elements and various problems caused by the rough surface of the polycrystalline silicon layer; and Figures 3A to 3D are cross-sectional views of a series of semiconductor substrates.

_f £ 〇384 V. Description of the invention (7) Reduction of complex crystalline silicon gate [Detailed description of the invention As mentioned above, various problems caused by the process of CMOS element manufacturing with rough surface of crystalline silicon gate. The first 30 is, for example, a silicon crystal layer 32. For example, the first silicon layer 31 covers the semi-conducted un-doped polycrystalline silicon, so the surface is formed. Manufacturing process for rough surface roundness. The improved method of the present invention is to improve the cause. For example, on the 3A circle, the square conductor substrate 30 layer 32 is thermally oxidized in sequence, and the same main method of undoped complex crystal is suitable for formation as shown in the rough diagram. In one method or on the surface, the silicon layer 32 is used for the double compound, and in the thin insulation product process, the material has a lower supply—a type that reduces the surface of the heavily doped gate structure silicon layer. A semiconductor base layer 31 and a complex crystal are formed-a thin oxide-a CVD process itself deposits a thick rough surface

Secondly, a flat dielectric layer (c0nf0rmal dieieck layer) 33 is formed, covering the undoped polycrystalline silicon having a rough surface as described above, and a flat surface structure is obtained by compensating for the thickness drop, such as Figure 3A does not. In this embodiment, the planarized dielectric layer is a silicon oxide layer, and its thickness is between 500 angstroms and 1,000 angstroms. According to the results of the inventors' multiple experiments, we have found that we can use the atmospheric pressure chemical vapor deposition (SACVD) procedure and use ozone-tetraethoxysilylmethane (〇rTE〇s) as the raw material to deposit The above silicon oxide layer; or the formation of the above silicon oxide layer by performing a plasma enhanced chemical vapor deposition (PECVJ) procedure or a low pressure chemical vapor deposition (LpcvD) procedure; in addition, a plasma enhanced chemical The vapor deposition (PECVD) process uses rhenium as a raw material to form the above-mentioned oxide dream layer.

Page 10 410384 V. Description of the invention (8) Refer to Fig. 3B 'Perform an Ar sputter procedure. With its powerful etching effect, in addition to removing the above-mentioned planarized dielectric layer 33, it is also removed together. The surface portion of the rough seam of the undoped polycrystalline silicon layer 32 leaves a flat undoped polycrystalline silicon layer 32a as shown in the figure. The execution conditions of this argon spattering procedure are as follows: the pressure is 0.4 mT, the temperature is room temperature, the power / bias power is 300/100 w, and the spattering rate is 4-5 angstroms / second. According to the experimental results made by the inventors, it is found that the improved method of the present invention can effectively reduce the surface roughness of the undoped polycrystalline silicon layer 32 from 4.4 nm RMS to 0.8 nm RMS, and the effect is extremely obvious. Next, as shown in FIG. 3C, a photoresist layer is coated on the undoped polycrystalline silicon layer 32 & =, and a photoresist layer pattern 34 is defined by a lithography imaging program, and a cover is left to form Gate structure area. Compared with FIG. 2b, the non-doped polycrystalline silicon layer 32a in this embodiment has been subjected to an argon sputtering process on the flat surface first. Therefore, it is not known that the exposure step is not seen in the conventional manufacturing process, and it is possible to The characteristics of the photoresist layer pattern 34 are precisely controlled. Still referring to FIG. 3C, the photoresist layer pattern 34 is used as a mask to sequentially replace the spar, spar, and miscellaneous materials. The Fuming silicon layer 32a and the thin silicon oxide layer are defined in the figure of the gate electrode layer 32b and the gate insulating layer. * Because the surface of the undoped polycrystalline silicon layer 32a mentioned above ^ 2: top: = not after the sequence Will be like the f process: half: 1 undesired pit on the body substrate 0, and the integrity of the component fabrication area will be destroyed. After that, an insulating layer is deposited, such as a nitride electrode, a closed electrode pattern, and a semiconductive layer substrate. Page 11

V. Description of the invention (9), and perform an anisotropic etch-back process, such as-active ion etching (RIE) process to leave the insulation gap on the side wall of the gate electrode latent 32b 3 5 'As shown in FIG. 3C, it is obvious that since the over-etching process is no longer required', the problem of insufficient remaining thickness of the insulating spacer 35 will not be caused. Next, the appropriate conductive type of impurities, which may be p_-type shed ions or η-type phosphorus or arsenic ions, are implanted into the above-mentioned gate electrode layer 32b, and enter the non-gate on the surface of the semiconductor substrate 30 The portion covered by the electrode layer forms a pair of doped source / drain regions 36, and a transistor structure is completed. Although in order to simplify the illustration here, only a transistor structure of a conductive type of 00 is drawn, the improvement method according to the present invention can also use a photoresist layer (not shown) as shown in FIG. 1C. The pattern covers a part of the semiconductor substrate 10, and an n-channel transistor is formed by implanting n-type impurities. After removing the above photoresist layer pattern, another photoresist layer pattern (not shown) is used to cover it. The other part of the semiconductor substrate 10 is held, and a p-channel transistor is formed by implanting a P-type impurity, and the manufacture of CMOS is completed. Although the present invention is disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some changes and decorations without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

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Claims (1)

6. Scope of patent application 1. A method for reducing the surface roughness of a polycrystalline silicon gate (surface rougHness), which is suitable for the process of a CMOS device with a double doped gate structure (dua gate), including the following steps: forming a thin insulation Layer on a semiconductor substrate surface; forming an undoped polycrystalline silicon layer on the surface of the thin insulating layer; forming a planarized dielectric layer on the undoped polycrystalline silicon layer; performing an argon Gas or argon / oxygen sputtering process to remove the planarized dielectric layer and remove the rough surface of the undoped polycrystalline silicon layer together to leave a flat undoped polycrystalline silicon layer; selectivity Etch the flat undoped polycrystalline silicon layer and the thin insulation layer to form a gate electrode layer and a gate insulation layer, respectively; and, implant appropriate impurities into the gate electrode layer, and place the The part of the surface that is not covered by the gate electrode layer forms a pair of drain regions and completes the required transistor structure. "Source 2. The method as described in item 1 of the scope of patent application, wherein The thin layer is a thin layer of oxidized stone. The margin 3 is the method described in item 1 of the scope of patent application, wherein the undoped polycrystalline silicon layer is formed by a chemical vapor deposition (CVD) process. 4. The method according to item 1 of the scope of patent application, wherein the flat twisted dielectric layer is a silicon oxide layer. ~ 5 The method as described in item 4 of the scope of patent application, the thickness of the layer is between 500 Angstroms and 1000 Angstroms. 6. The method as described in item 4 of the scope of patent application, wherein The 13th tribute 6. The scope of the patent application ------ Sub-atmospheric pressure chemical vapor deposition (SACVD) procedure, pat. * * Tianling TT? Nc, Afcnz ,,. The oxidized stone layer was deposited by using methane (03_TEOS) as a raw material. 7. The method as described in item 4 of the scope of patent application, wherein a plasma enhanced chemical vapor deposition (PE (; VD)) procedure is performed to form the silicon oxide layer. 8. As described in item 4 of the scope of patent application The method includes performing a low pressure chemical vapor deposition (LPCVD) procedure to form the silicon oxide layer. 9. The method according to item 4 of the scope of the patent application, wherein the electric enhanced chemical vapor deposition (PECVD) cake is performed. And use the silicon oxide layer as a raw material to form the silicon oxide layer. 1 0 _ The method described in item 1 of the scope of the patent application 'wherein N-plastic impurities are implanted into the gate electrode layer. 11. As the scope of patent application The method described in item i, wherein the implanted impurities enter the gate electrode layer. Page 14