KR20040011912A - method for fabricating thin film transistor in semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming a transistor of a semiconductor device is provided to improve a short channel effect by adding a process for forming the second spacer between a process for forming source/drain and a process for forming a gate of a damascene structure. CONSTITUTION: A sacrificial layer pattern is formed on a semiconductor substrate(1). An LDD ion implantation process is performed by using the sacrificial layer pattern as a mask. A spacer(5) is formed on the side of the sacrificial layer pattern. A source/drain ion implantation process is performed by using the sacrificial layer pattern including the spacer(5) as the mask. The first oxide layer(9) is formed on the entire surface of the semiconductor substrate(1). The sacrificial layer pattern is exposed by performing a CMP process for the first oxide layer(9). The sacrificial layer pattern is removed. A gate insulating layer(10) is formed on the resultant structure. A metal layer(11) for gate is formed on the gate insulating layer(10). A gate(12a) of a damascene structure is formed by etching the metal layer(11) for gate and the gate insulating layer.

Description

Method for fabricating thin film transistor in semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a transistor of a semiconductor device in which a short channel is prevented by applying a gate having a damascene structure.

With the recent development of sub-0.10 micron devices, polycrystalline silicon gates or polyside gates, which are used as conventional gate electrodes, have encountered the following limitations. That is, in the polycrystalline silicon gate, problems such as an increase in the effective thickness of the gate insulating layer due to the gate depletion phenomenon, a dopant penetration phenomenon from the p + or n + polycrystalline silicon gate to the substrate, and a change in the threshold voltage due to the dopant distribution variation occur.

In addition, there is a problem that the gate using the conventional polycrystalline silicon can no longer implement the low resistance value required on the fine line width.

Therefore, there is a need for development of a new material and a gate electrode having a new structure that can replace a gate using a conventional polycrystalline silicon.

According to this demand, the development of metal gate electrodes is being actively promoted. In the case of the metal gate, since the dopant is not fundamentally used, there is no problem that occurs in the conventional polycrystalline silicon gate. At this time, W, WN, Ti, TiN, Mo, MoN, Ta, TaN, Ti3Al, Ti3AlN, or the like is used as the metal gate material.

However, when manufacturing a CMOSFET formed of the metal gate, the flat band voltage is reduced in the NMOS and PMOS regions, and as a result, the threshold voltage is increased.

Therefore, in order to lower the threshold voltage, a buried channel is formed through counter doping, which causes problems such as an increase in short channel effect and an increase in leakage current of the transistor.

Accordingly, an object of the present invention is to provide a method for fabricating a transistor of a semiconductor device capable of improving the short channel effect.

1A to 1F are cross-sectional views illustrating a method of forming a transistor of a semiconductor device.

* Explanation of Signs of Major Parts of Drawings *

1. Semiconductor substrate 2. Oxide film

3. Sacrifice 3a. Sacrifice Pattern

5. Spacer 6. LED Area

7. Source / drain region 8. Second nitride film

9. Second oxide film 10. Second spacer

11. Gate insulating film 12. Metal film for gate

12a. Gate 20. Photoresist pattern

In accordance with another aspect of the present invention, there is provided a method of fabricating a transistor of a semiconductor device, the method comprising: forming a sacrificial layer pattern covering a gate region on a semiconductor substrate; And forming a spacer on the side of the sacrificial film pattern, and performing source / drain ion implantation on the entire surface of the substrate using the sacrificial film pattern including the spacer as a mask, and the entire surface of the substrate including the spacer and the sacrificial film pattern. Forming a first oxide film on the substrate, chemically-mechanically polishing the first oxide film until the sacrificial film pattern is exposed, removing the sacrificial film pattern, and chemical vapor deposition on the entire surface of the resulting product Forming a metal layer; forming a gate metal film on the gate insulating film; and a time point at which the first oxide film is exposed. Characterized by including the step of etching to form the gate of the damascene structure and how the metal gate film and the gate insulating film for.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1F are cross-sectional views illustrating a method of forming a transistor of a semiconductor device.

In the method for forming a transistor of a semiconductor device according to the present invention, as shown in FIG. 1A, first, field oxide films (not shown) defining an element formation region are formed on a surface of a semiconductor substrate 1, and then The first oxide film 2 and the sacrificial film 3 are sequentially formed on the substrate 1. At this time, the first oxide film 2 has a structure in which a multilayer oxide film is laminated.

Subsequently, a photoresist pattern 20 covering the gate region is formed on the sacrificial layer 3.

Next, as shown in FIG. 1B, the photoresist pattern is used as a mask, and the sacrificial layer is dry etched to expose the surface of the first oxide layer 2. At this time, in the dry etching process, the first oxide layer 2 is used as an etching barrier. Hereinafter, the sacrificial layer remaining by the dry etching process is referred to as a sacrificial layer pattern 3a.

Thereafter, after removing the photosensitive film pattern, the sacrificial film pattern 4 is used as a mask and ion implantation for LEDs is applied to the entire surface of the substrate. Subsequently, a first nitride film (not shown) is formed on the entire surface of the substrate including the sacrificial film pattern 4, and then the first nitride film is etched back or a chemical mechanical polishing process is performed. To form a spacer 5.

Then, the LED region 6 and the source / drain region 7 are formed by performing source / drain ion implantation using the sacrificial layer pattern 4 including the spacer 5 as a mask.

Subsequently, as shown in FIG. 1C, the second nitride film 8 and the second oxide film 9 are sequentially formed on the entire surface of the substrate including the spacer 5 and the sacrificial film pattern 4.

Then, as shown in FIG. 1D, the second oxide film and the second nitride film are chemically mechanically polished to expose the sacrificial film pattern surface. At this time, in the chemical-mechanical polishing process, the second nitride film is used as the polishing stop layer.

Thereafter, the sacrificial film pattern exposed as a result of the chemical-mechanical polishing process is removed. In this case, the sacrificial layer pattern is removed by a wet etching process.

Subsequently, after the third nitride layer (not shown) is formed on the entire surface of the substrate from which the sacrificial layer pattern is removed, the third nitride layer is etched entirely to form the second spacer 10 on the side of the first spacer 5.

Next, as shown in FIG. 1E, a gate insulating film 11 is formed on the entire surface of the resultant by a chemical vapor deposition process, and then a gate metal film 11 is formed on the gate insulating film 11. To form. In this case, any one of a tantalum oxide film and an aluminum oxide film may be used as the gate insulating film 10.

Thereafter, as shown in FIG. 1F, the gate metal film and the gate insulating film are chemically-mechanically polished until the surface of the second oxide film 9 is exposed to form a gate 12a having a damascene structure.

According to the present invention, after forming a source / drain region, when forming a gate electrode having a damascene structure, a second spacer is formed on the side of the gate electrode, whereby the second spacer can produce a transistor having an improved short channel effect. Do.

In the present invention, a gate insulating film is formed by a chemical vapor deposition process, and any one of a tantalum oxide film and an aluminum oxide film is used as the gate insulating film.

As described above, in the present invention, a step of forming a second spacer on the side of the gate electrode is added between the step of forming a source / drain region and a step of forming a gate electrode having a damascene structure, and thus the second spacer is shortened by the second spacer. It is possible to manufacture transistors with improved channel effects.

Further, in the present invention, any one of a tantalum oxide film and an aluminum oxide film is formed by chemical vapor deposition to form a gate insulating film, which is applicable to a fine highly integrated device.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (6)

Forming a sacrificial layer pattern covering the gate region on the semiconductor substrate; Using the sacrificial layer pattern as a mask and performing an LED implant on the entire surface of the substrate; Forming a spacer on a side of the sacrificial layer pattern; Performing source / drain ion implantation on the entire surface of the substrate using the sacrificial layer pattern including the spacer as a mask; Forming a first oxide film on an entire surface of the substrate including the spacers and the sacrificial film pattern; Chemically-mechanically polishing the first oxide layer until the sacrificial layer pattern is exposed; Removing the sacrificial layer pattern; Forming a gate insulating film on the entire surface of the result by chemical vapor deposition; Forming a gate metal film on the gate insulating film; And forming a gate having a damascene structure by etching the gate metal layer and the gate insulating layer until the first oxide layer is exposed. The method of claim 1, wherein in the forming of the sacrificial layer pattern covering the gate region on the semiconductor substrate, the second oxide layer is interposed between the substrate and the sacrificial layer pattern, and the second sacrificial layer pattern etching process is performed. A method of manufacturing a transistor of a semiconductor device, comprising using an oxide film as an etching barrier. The method of claim 1, wherein the sacrificial layer pattern is removed by a wet etching process. 2. The method of claim 1, wherein the first oxide film has a multilayer stack structure. The method of claim 1, wherein the forming of the first oxide layer on the entire surface of the substrate including the spacers and the sacrificial layer pattern and etching the first oxide layer until the sacrificial layer pattern is exposed, A transistor of a semiconductor device, wherein the nitride film is used as a polishing stop layer in a process of chemically-mechanically polishing the first oxide film by interposing a nitride film between the entire surface of the substrate including the spacer and the sacrificial film pattern and the first oxide film. Manufacturing method. The method of claim 1, wherein the gate insulating film is formed of any one of a tantalum oxide film and an aluminum oxide film.