KR100902593B1 - Method for forming gate electrode in semiconductor device - Google Patents

Method for forming gate electrode in semiconductor device Download PDF

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KR100902593B1
KR100902593B1 KR1020070086498A KR20070086498A KR100902593B1 KR 100902593 B1 KR100902593 B1 KR 100902593B1 KR 1020070086498 A KR1020070086498 A KR 1020070086498A KR 20070086498 A KR20070086498 A KR 20070086498A KR 100902593 B1 KR100902593 B1 KR 100902593B1
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forming
gate electrode
film
semiconductor device
oxide film
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KR20090021732A (en
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강동우
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주식회사 동부하이텍
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 반도체소자의 게이트 전극 형성방법에 관한 것으로, 본 발명에 따른 반도체 소자의 게이트 전극 형성방법은 기판 상에 캡 산화막을 형성하는 단계와, 상기 캡 산화막 상에 소정 간격의 거리를 둔 두 개의 측벽 질화막을 형성하는 단계와, 상기 측벽 질화막이 형성된 기판 상에 게이트 산화막 및 폴리 실리콘막을 형성하는 단계와, 상기 폴리 실리콘막에 패터닝공정을 수행하여, 상기 두 개의 측벽 질화막 사이에 게이트 전극을 형성하는 단계를 포함한다. The present invention relates to a method of forming a gate electrode of a semiconductor device, the method of forming a gate electrode of a semiconductor device according to the present invention comprises the steps of forming a cap oxide film on a substrate, and a predetermined distance on the cap oxide film Forming a sidewall nitride film, forming a gate oxide film and a polysilicon film on the substrate on which the sidewall nitride film is formed, and performing a patterning process on the polysilicon film to form a gate electrode between the two sidewall nitride films Steps.

게이트전극 Gate electrode

Description

반도체 소자의 게이트 전극 형성방법{Method for forming gate electrode in semiconductor device}Method for forming gate electrode in semiconductor device

본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 반도체 소자의 게이트 전극 형성방법에 관한 것이다. The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a gate electrode of a semiconductor device.

반도체 소자의 고집적화에 따라 게이트 전극의 선폭 축소를 필요로 하는데 게이트 전극의 선폭이 축소되면 소자의 집적도가 높아지고 스위칭 속도가 빨라지게 된다. Higher integration of semiconductor devices requires reduction of the line width of the gate electrode, which results in higher integration and faster switching speed.

그러나 미세 선폭을 갖는 게이트 전극을 형성하기 위한 공정 진행시, 식각 공정 제어의 어려움 등으로 인해, 상부보다 선폭이 좁아진 하부를 갖는 게이트 전극의 프로파일을 갖는 노칭(notch)현상이 발생하게 된다. However, during the process of forming a gate electrode having a fine line width, a notch phenomenon occurs with a profile of the gate electrode having a lower portion having a narrower line width than the upper portion due to difficulty in controlling an etching process.

이렇게 발생된 노칭 현상으로 인해, 게이트 전극의 실제 길이가 짧아져 트랜지스터의 채널길이가 짧아지게 되어 포화전류(Saturation Current)의 특성과 브레이크다운 전압(Break-down Voltage)의 특성을 저하시켜 반도체 소자의 전기적 특성을 저하시키는 문제점을 가져온다. As a result of the notching phenomenon, the actual length of the gate electrode is shortened and the channel length of the transistor is shortened, thereby decreasing the characteristics of the saturation current and the breakdown voltage. This brings about a problem of deteriorating electrical characteristics.

상기와 같은 문제점을 해결하기 위하여, 본 발명은 게이트 전극의 실제길이를 확보함으로써, 트랜지스터의 채널길이가 줄어드는 것을 방지하고 포화전류의 특성 및 브레이크다운 전압의 특성을 향상시켜 소자의 전기적 특성을 향상시킬 수 있도록 하는 반도체 소자의 게이트 전극 형성방법을 제공함에 있다. In order to solve the above problems, the present invention by securing the actual length of the gate electrode, to prevent the channel length of the transistor is reduced, improve the characteristics of the saturation current and the breakdown voltage to improve the electrical characteristics of the device The present invention provides a method for forming a gate electrode of a semiconductor device.

상기와 같은 과제를 달성하기 위한 본 발명에 따른 반도체 소자의 게이트 전극 형성방법은 기판 상에 소정 간격의 거리를 둔 두 개의 측벽 질화막을 형성하는 단계와, 상기 측벽 질화막이 형성된 기판 상에 게이트 산화막 및 폴리 실리콘막을 형성하는 단계와, 상기 폴리 실리콘막에 패터닝공정을 수행하여, 상기 두 개의 측벽 질화막 사이에 게이트 전극을 형성하는 단계를 포함한다. According to an aspect of the present invention, there is provided a method of forming a gate electrode of a semiconductor device, the method including: forming two sidewall nitride films at a predetermined interval on a substrate, and forming a gate oxide film on the substrate on which the sidewall nitride film is formed; Forming a polysilicon film; and forming a gate electrode between the two sidewall nitride films by performing a patterning process on the polysilicon film.

기판과 상기 측벽 질화막 사이의 계면에 캡 산화막을 형성하는 단계를 더 포함한다. And forming a cap oxide film at an interface between the substrate and the sidewall nitride film.

상기 게이트 산화막은 산화공정을 수행하여 형성한다. The gate oxide film is formed by performing an oxidation process.

상기 폴리 실리콘막의 패터닝공정은 상기 폴리 실리콘막 상에 게이트 전극 형성용 포토레지스트 패턴을 형성하는 단계와, 상기 포토레지스트 패턴을 식각 마스크로 상기 폴리실리콘막의 일부두께를 식각하는 단계와, 상기 포토레지스트 패턴을 제거하는 단계와, 상기 일부 두께가 제거된 폴리실리콘막을 식각 마스크로 상기 게이트 산화막이 노출될 때까지 식각하는 단계를 포함한다.The patterning of the polysilicon layer may include forming a photoresist pattern for forming a gate electrode on the polysilicon layer, etching a partial thickness of the polysilicon layer using the photoresist pattern as an etch mask, and forming the photoresist pattern. And removing the polysilicon layer from which the partial thickness has been removed until the gate oxide layer is exposed using the etching mask.

상기 포토레지스트 패턴을 제거하는 단계는 에싱공정 또는 습식세정공정을 수행하여 형성한다. Removing the photoresist pattern is formed by performing an ashing process or a wet cleaning process.

상기 일부 두께가 제거된 폴리실리콘막을 식각 마스크로 상기 게이트 산화막이 노출될 때까지 식각하는 단계는 에치백공정을 수행하여 형성한다. The etching of the polysilicon layer from which the partial thickness is removed until the gate oxide layer is exposed using the etching mask is performed by performing an etch back process.

본 발명에 따른 반도체 소자의 게이트전극 형성방법은 두 개의 측벽 질화막을 형성하여 게이트 전극 형성 영역을 정의한 후 게이트 전극을 형성함으로써, 정확한 게이트 전극의 실제길이를 확보할 수 있게 되어 트랜지스터의 채널길이가 줄어드는 것을 방지하고 포화전류의 특성 및 브레이크다운 전압의 특성을 향상시켜 소자의 전기적 특성을 향상시키는 효과가 있다. In the method of forming a gate electrode of a semiconductor device according to the present invention, two sidewall nitride films are formed to define a gate electrode formation region, and then a gate electrode is formed, so that the actual length of the gate electrode can be secured, thereby reducing the channel length of the transistor. It is effective to improve the electrical characteristics of the device by preventing it and improving the characteristics of the saturation current and the breakdown voltage.

또한, 본 발명에 따른 반도체소자의 게이트 전극 형성방법은 산화공정을 통해 제2 게이트 산화막을 측벽 질화막상에 형성함으로써, 트랜지스터의 게이트 산화막 형성공정과 게이트전극인 폴리 실리콘막의 보호막 형성공정을 동시에 수행함으로써 공정단순화의 효과를 갖는다. In the method of forming a gate electrode of a semiconductor device according to the present invention, a second gate oxide film is formed on a sidewall nitride film through an oxidation process, thereby simultaneously performing a gate oxide film forming process of a transistor and a protective film forming process of a polysilicon film as a gate electrode. It has the effect of process simplification.

이하, 첨부된 도면 및 실시 예를 통해 본 발명의 실시 예를 구체적으로 살펴보면 다음과 같다.Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings and embodiments.

도 1 내지 도 7은 본 발명에 따른 반도체 소자의 게이트 전극 형성방법을 도시한 공정 순서도이다. 1 to 7 are process flowcharts illustrating a method of forming a gate electrode of a semiconductor device according to the present invention.

도 1에 도시된 바와 같이, 반도체 기판(10)상에 캡(cap) 산화막(12), 질화 막(14a)을 순차적으로 형성한다.As shown in FIG. 1, a cap oxide film 12 and a nitride film 14a are sequentially formed on the semiconductor substrate 10.

이어, 도 2에 도시된 바와 같이, 질화막(14a) 상에 사진공정을 통해 측벽 정의용 포토레지스트 패턴(16)을 형성한다. 상기 측벽 정의용 포토레지스트 패턴(16)을 식각 마스크로 이용하여 상기 질화막(14)을 식각하여 소정간격의 거리(L)를 둔 두 개의 측벽 질화막(14b)을 형성한다. Next, as shown in FIG. 2, the photoresist pattern 16 for defining sidewalls is formed on the nitride film 14a through a photolithography process. The nitride layer 14 is etched using the sidewall defining photoresist pattern 16 as an etching mask to form two sidewall nitride layers 14b having a distance L of a predetermined interval.

상기 소정간격의 거리(L)는 게이트 전극의 채널 길이로써, 이는 두 개의 측벽 질화막이 형성되고 그 사이에 게이트 전극 형성 영역을 정의함으로써 게이트 전극의 채널길이로 확보될 수 있다. The distance L of the predetermined interval is a channel length of the gate electrode, which may be secured to the channel length of the gate electrode by forming two sidewall nitride layers and defining a gate electrode formation region therebetween.

이어, 상기 측벽 정의용 포토레지스트 패턴(16)을 에싱 공정 또는 습식세정공정을 통해 제거한다. Next, the sidewall defining photoresist pattern 16 is removed through an ashing process or a wet cleaning process.

다음으로, 도 3에 도시된 바와 같이, 상기 두 개의 측벽 질화막(14b)이 형성된 기판(10) 전면에 산화공정을 수행하여 제2 게이트 산화막(18)을 형성한다. Next, as shown in FIG. 3, the second gate oxide layer 18 is formed by performing an oxidation process on the entire surface of the substrate 10 on which the two sidewall nitride layers 14b are formed.

이때, 산화공정을 통해 형성된 제2 게이트 산화막(18)은 측벽 질화막(14b)이 이후 제2 게이트 산화막(18)상에 형성될 폴리실리콘막의 게이트 전극으로의 침투를 막기 위해 형성하고, 기판 상에 형성된 제2 게이트 산화막(18)은 이후 형성될 게이트 전극의 게이트 산화막으로의 역할을 수행하기 위해 형성된다. At this time, the second gate oxide film 18 formed through the oxidation process is formed to prevent the sidewall nitride film 14b from penetrating into the gate electrode of the polysilicon film to be formed on the second gate oxide film 18 on the substrate. The formed second gate oxide film 18 is formed to serve as a gate oxide film of the gate electrode to be formed later.

이와 같이, 산화공정을 통해 제2 게이트 산화막(18)을 측벽 질화막(14b)상에 형성함으로써, 트랜지스터의 게이트 산화막 형성공정과 게이트전극인 폴리 실리콘막의 보호막 형성공정을 동시에 수행함으로써 공정단순화의 측면을 갖는다. As described above, the second gate oxide film 18 is formed on the sidewall nitride film 14b through the oxidation process, thereby simultaneously performing the gate oxide film forming process of the transistor and the protective film forming process of the polysilicon film serving as the gate electrode. Have

도 4에 도시된 바와 같이, 제2 게이트 산화막(18)이 형성된 기판(10)상에 게 이트 전극용 폴리 실리콘막(20a)을 형성한다. 이어, 상기 폴리 실리콘막(20a) 상에 게이트전극 정의용 포토레지스트 패턴(22)을 형성한다. As shown in FIG. 4, the polysilicon film 20a for the gate electrode is formed on the substrate 10 on which the second gate oxide film 18 is formed. Subsequently, a gate electrode defining photoresist pattern 22 is formed on the polysilicon layer 20a.

도 5에 도시된 바와 같이, 상기 게이트 전극 정의용 포토레지스트 패턴(22)을 식각 마스크로 상기 폴리실리콘막(20a)의 일부 두께만 식각하여 패터닝한다. As shown in FIG. 5, only a partial thickness of the polysilicon layer 20a is etched and patterned using the gate electrode defining photoresist pattern 22 as an etching mask.

도 6에 도시된 바와 같이, 상기 포토레지스트 패턴(22)을 에싱공정 또는 습식세정공정을 통해 제거한다. As shown in FIG. 6, the photoresist pattern 22 is removed through an ashing process or a wet cleaning process.

도 7에 도시된 바와 같이, 일부 두께만 패터닝된 폴리실리콘막(20a)에 제2 게이트 산화막(18)이 노출될 때까지 에치백공정을 수행하여, 게이트 전극(20c)의 형성을 완성한다. As illustrated in FIG. 7, an etch back process is performed on the polysilicon film 20a having only a partial thickness until the second gate oxide film 18 is exposed to complete formation of the gate electrode 20c.

이상에서 설명한 본 발명은 상술한 실시 예 및 첨부된 도면에 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 종래의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

도 1 내지 도 7은 본 발명에 따른 반도체 소자의 게이트 전극 형성방법을 도시한 공정 순서도이다.1 to 7 are process flowcharts illustrating a method of forming a gate electrode of a semiconductor device according to the present invention.

Claims (6)

기판 상에 캡 산화막을 형성하는 단계와,Forming a cap oxide film on the substrate; 상기 캡 산화막 상에 소정 간격의 거리를 둔 두 개의 측벽 질화막을 형성하는 단계와,Forming two sidewall nitride films spaced at a predetermined interval on the cap oxide film; 상기 측벽 질화막이 형성된 기판 상에 게이트 산화막 및 폴리 실리콘막을 형성하는 단계와,Forming a gate oxide film and a polysilicon film on the substrate on which the sidewall nitride film is formed; 상기 폴리 실리콘막에 패터닝공정을 수행하여, 상기 두 개의 측벽 질화막 사이에 게이트 전극을 형성하는 단계를 포함하는 반도체 소자의 게이트 전극 형성방법.And forming a gate electrode between the two sidewall nitride layers by performing a patterning process on the polysilicon layer. 삭제delete 제1 항에 있어서, 상기 게이트 산화막은The method of claim 1, wherein the gate oxide film 산화공정을 수행하여 형성하는 것을 특징으로 하는 반도체 소자의 게이트 전극 형성방법.A gate electrode forming method of a semiconductor device, characterized in that formed by performing an oxidation process. 제1 항에 있어서, 상기 폴리 실리콘막의 패터닝공정은The method of claim 1, wherein the patterning of the polysilicon film is performed. 상기 폴리 실리콘막 상에 게이트 전극 형성용 포토레지스트 패턴을 형성하는 단계와,Forming a photoresist pattern for forming a gate electrode on the polysilicon film; 상기 포토레지스트 패턴을 식각 마스크로 상기 폴리실리콘막의 일부두께를 식각하는 단계와,Etching a portion of the polysilicon layer using the photoresist pattern as an etching mask; 상기 포토레지스트 패턴을 제거하는 단계와,Removing the photoresist pattern; 상기 일부 두께가 제거된 폴리실리콘막을 식각 마스크로 상기 게이트 산화막이 노출될 때까지 식각하는 단계를 포함하는 반도체 소자의 게이트 전극 형성방법.Etching the polysilicon layer from which the partial thickness is removed until the gate oxide layer is exposed using an etching mask. 제4 항에 있어서, 상기 포토레지스트 패턴을 제거하는 단계는 The method of claim 4, wherein removing the photoresist pattern 에싱공정 또는 습식세정공정을 수행하여 형성하는 것을 특징으로 하는 반도체 소자의 게이트 전극 형성방법. A method of forming a gate electrode of a semiconductor device, characterized in that formed by performing an ashing process or a wet cleaning process. 제4 항에 있어서, 상기 일부 두께가 제거된 폴리실리콘막을 식각 마스크로 상기 게이트 산화막이 노출될 때까지 식각하는 단계는The method of claim 4, wherein the etching of the polysilicon layer having the partial thickness removed until the gate oxide layer is exposed using an etching mask is performed. 에치백공정을 수행하여 형성하는 것을 특징으로 하는 반도체 소자의 게이트 전극 형성방법. A gate electrode forming method of a semiconductor device, characterized in that formed by performing an etch back process.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06188259A (en) * 1992-12-17 1994-07-08 Toshiba Corp Manufacture of semiconductor device
KR19990032919A (en) * 1997-10-22 1999-05-15 구본준 Manufacturing Method of Semiconductor Device
KR20040011912A (en) * 2002-07-31 2004-02-11 동부전자 주식회사 method for fabricating thin film transistor in semiconductor device
JP2007250610A (en) 2006-03-14 2007-09-27 Oki Electric Ind Co Ltd Semiconductor device and method for manufacturing the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06188259A (en) * 1992-12-17 1994-07-08 Toshiba Corp Manufacture of semiconductor device
KR19990032919A (en) * 1997-10-22 1999-05-15 구본준 Manufacturing Method of Semiconductor Device
KR20040011912A (en) * 2002-07-31 2004-02-11 동부전자 주식회사 method for fabricating thin film transistor in semiconductor device
JP2007250610A (en) 2006-03-14 2007-09-27 Oki Electric Ind Co Ltd Semiconductor device and method for manufacturing the same

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