五、發明說明（1) 本發明是有關於半導體製程技術，且特別是有關於一 種利用犧牲層防止蝕刻終止層於拋光（buf f ing)過程中受 損的金屬化製程。 β 近年來’為配合元件尺寸縮小化的發展以及提高元件 操作速度的需求’具有低電阻常數和高電子遷移阻抗的銅 金屬’已逐漸被應用來作為金屬内連線的材質，取代以往 的銘金屬製程技術。其中配合銅金屬的鑲嵌式内連線技術 不僅可達到内連線的縮小化並且可減少RC時間延遲，同時 也解決了金屬銅蝕刻不易的問題，因此已成為現今多重内 連線主要的發展趨勢。 鑲嵌式（damascene)製程有別於傳統先定義金屬圖案 再以介電層填溝的金屬化製程，其方法是先在一平坦的介 電上蝕刻出金屬線的溝槽後再將金屬層填入，最後並將多 餘的金屬移去，而得到一具有金屬鑲嵌於介電層中的平坦 結構。鑲嵌式製程比起傳統的金屬化製程具有以下優點： (1 )可使基底表面隨時保持平坦；（2)可排除傳統製程中介 電材料不易填入金屬導線間隙的缺點；（3)可解決金屬材 料蚀刻不易的問題，特別是銅金屬的姓刻。 在上述的鑲嵌式製程中，為了利於金屬線溝槽的蝕刻 定義，一般都會在導線介電質（line dielectric)底下增 設一蝕刻終止層，而此蝕刻終止層通常是在製作插塞的階 段即預先形成，以下請參照第1A〜1 C圖之說明。 首先，如第1A圖，在基底10上沈積介電層12作為内層 介電層（ILD)或金屬間介電層（IMD)，接著並沈積一氮氧化V. Description of the Invention (1) The present invention relates to semiconductor process technology, and in particular, to a metallization process that uses a sacrificial layer to prevent the etching stop layer from being damaged during buff fing. β In recent years, “to match the development of component size reduction and increase the speed of component operation” copper metal with low resistance constant and high electron migration resistance ”has gradually been used as the material of metal interconnects, replacing the previous inscription Metal process technology. Among them, the mosaic interconnect technology with copper metal can not only reduce the interconnect size and reduce the RC time delay, but also solve the problem of difficult copper metal etching, so it has become the main development trend of multiple interconnects today. . The damascene process is different from the traditional metallization process in which a metal pattern is first defined and a trench is filled with a dielectric layer. The method is to first etch a groove of a metal line on a flat dielectric and then fill the metal layer. And finally remove the excess metal to obtain a flat structure with metal embedded in the dielectric layer. The inlay process has the following advantages over the traditional metallization process: (1) It can keep the surface of the substrate flat at any time; (2) It can eliminate the disadvantage that the dielectric material is not easy to fill the gap of the metal wire in the traditional process; (3) It can solve the metal Material is not easy to etch, especially copper metal engraving. In the above-mentioned damascene process, in order to facilitate the definition of the etching of metal wire trenches, an etch stop layer is generally added under the line dielectric, and this etch stop layer is usually at the stage of making plugs. Pre-formed, please refer to the description of Figures 1A ~ 1C below. First, as shown in FIG. 1A, a dielectric layer 12 is deposited on the substrate 10 as an inner dielectric layer (ILD) or an intermetal dielectric layer (IMD), and then a nitrous oxide is deposited.
五、發明說明（2) ' 石夕層（SiON) 14作為將來定義内連線溝槽的蝕刻終止層。之 後’以微影與姓刻程序在介電層12與氮氧化矽層14中定義. 出接觸窗（或介層洞），並依序沈積一阻障層16與一鎢金屬 層18，如第1B圖所示。接下來的步驟，是以化學機械研磨 去除氮氧化梦層14上多餘的鎢金屬層與阻障層，而形成一 導電插塞，如第1C圖所示。 在鶴插塞的研磨過程中，受到金屬研磨液的影響介 電層表面通常會有細小的刮痕（scratch)出現，為了確保 介電層的品質，一般都會在研磨的最後更換漿液，然後推 L一—道所—見巧"复光X㈣f ing)，，程序，以t介電層上^p 除。…、而’由於傳統也光程序所使用的漿液係針對 ，而應用在氮氧化矽材質上往往會有研磨H ==缺陷的情形(如圖中14,所示)。由於 ^漢神斤路f刻終先見’如此一來，^^^ 線溝槽19發生困難’影響内連線的可靠度。 供本發明的主要目的為了解決上述問題而提 八，D兔蝕刻終止層受的金表化製程。 -犧=上：：的’本發明之方法係在㈣終止層上形成 中保持^替 此犧牲層冑其下的餘刻終止層於抛光過程 明的方Ϊ ,其後續定義内連線溝槽之用。根據本發 夕主i3t 其主要步驟包括：（a)提供一覆有第一介雷層 層以及2層(b()y:介電層上依序形成一姓刻終止 介電層義刻終止層、犧牲層以及第-在其中形成一開口作為接觸窗或介層窗；（d) 五、發明說明（3) 依序沈積第一阻障層及第一金屬層，且第一金屬層填滿上 述開口；（e)對上述基底進行化學機械研磨，而在上述開 口中留下一導電插塞；以及（f)進行一拋光（buffing)程 序’俾使上述犧牲層可於該拋光程序被去除而使其下之蝕 刻終止層保持完整，以利於後續金屬内連線溝槽的蝕刻。 為完成鑲嵌式内連線的製作，在步驟（f)之後可更包 括以下步驟：（g)在基底上沈積第二介電層；（h)利用上述 蝕刻終止層，於第二介電層中定義出内連線溝槽；（i)在 基底上依序沈積第二阻障層及第二金屬層，且第二金屬層 填滿上述内連線溝槽；以及（j)對上述基底進行化學機械 研磨’而在上述内連線溝槽中留下一金屬内連線。 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂’下文特舉一較佳實施例’並配合所附圖式，作詳 細說明如下： 圖式之簡單說明 第1A〜1C圖為一系列剖面圖，用以說明習知一種金屬 化製程。 第2 A〜2D圖為一系列剖面圖，用以說明本發明一較佳 實施例之金屬化製程。 符號說明 10、20〜基底與半導體元件； 12、22、32〜介電層； 14、24〜蝕刻終止層； 1 4 ’〜有缺陷的蝕刻終止層；V. Description of the invention (2) 'Shi Xi layer (SiON) 14 is used as an etching stop layer for defining interconnect trenches in the future. Afterwards, the lithography and surname engraving procedures are used to define the dielectric layer 12 and the silicon oxynitride layer 14. A contact window (or a via hole) is formed, and a barrier layer 16 and a tungsten metal layer 18 are sequentially deposited, such as Shown in Figure 1B. The next step is to remove the excess tungsten metal layer and barrier layer on the oxynitride dream layer 14 by chemical mechanical polishing to form a conductive plug, as shown in FIG. 1C. During the grinding process of the crane plug, the surface of the dielectric layer is usually affected by metal abrasives. There are usually small scratches on the surface of the dielectric plug. L—the place—see Qiao &X; Fuguang X㈣f ing), the program, divided by ^ p on the dielectric layer. …, And because the slurry used in the traditional photo-optical process is aimed at, the application of silicon oxynitride materials often has grinding H == defects (as shown in Figure 14). Since ^ Han Shen Jin Lu f foresees the end ‘so, the ^^^ wire groove 19 is difficult’ affects the reliability of the interconnect. For the main purpose of the present invention, in order to solve the above problems, the process of gold surface treatment of D rabbit etching stop layer is mentioned. -Sacrifice = up :: 'The method of the present invention maintains the formation of the termination layer ^ instead of the sacrificial layer, and the remaining termination layer below is polished during the polishing process, and the subsequent definition of the interconnect trenches Use. According to the main i3t of the present invention, its main steps include: (a) providing a layer with a first dielectric layer and two layers (b () y: a sequential formation of a dielectric layer on the dielectric layer to terminate the dielectric layer) Layer, sacrificial layer, and-forming an opening therein as a contact window or via window; (d) five. Description of the invention (3) sequentially depositing the first barrier layer and the first metal layer, and the first metal layer is filled Fill the opening; (e) chemically and mechanically grind the substrate while leaving a conductive plug in the opening; and (f) perform a buffing process to enable the sacrificial layer to be polished during the polishing process. It is removed to keep the etch stop layer underneath intact, so as to facilitate the subsequent etching of metal interconnect lines. In order to complete the production of the mosaic interconnect, the following steps may be further included after step (f): (g) in Depositing a second dielectric layer on the substrate; (h) using the etch stop layer to define interconnect trenches in the second dielectric layer; (i) sequentially depositing a second barrier layer and a second barrier layer on the substrate A metal layer, and the second metal layer fills the interconnecting trench; and (j) the substrate Perform chemical mechanical polishing 'while leaving a metal interconnect in the interconnect trench. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below. 'In conjunction with the drawings, the detailed description is as follows: Brief description of the drawings Figures 1A to 1C are a series of cross-sectional views, which are used to explain the conventional metallization process. Figures 2 A to 2D are a series of cross-sectional views. , Used to explain the metallization process of a preferred embodiment of the present invention. Symbol description 10, 20 ~ substrate and semiconductor element; 12, 22, 32 ~ dielectric layer; 14, 24 ~ etch stop layer; 1 4 '~ Yes Defective etch stop layer;
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16、28、34〜阻障層； 18、30、36〜金屬層； 19〜内連線溝槽； 26〜犧牲氧化層； 26’〜殘餘的犧牲氧化層。 實施例 請參照第2A圖，其顯示本實施例之起始步驟。在介電 ^22以下的部分，可能包含數層金屬内連線與數個電性上 ^互連接的半導體元件，如M〇s電晶體、電阻、邏輯元件 I:方面起見，介電層22以下的半導體基底與積體電路 ^以標號20代表之。介電層22可為單層或數層由氧化 把氮化矽、硼矽玻璃、硼磷矽玻璃、或其它低介電係數 如FURE、PAE — 2、FSG、HSQ等）所構成的結構，但在 此處僅以標號22簡單表示之。 按傳統的方式，首先在介電層22沈積一氮氧化矽層 ，作為將來定義内連線溝槽的蝕刻終止層。之後，根據 之方法在氮氧化矽層24上更沈積-氧化層26作為 犧牲層，此犧牲氧化層可利用電漿加強化學氣相沈積法 (PECVD)加以沈積而成，厚度約1〇〇〇埃。 請參照第2B圖，接著以微影與蝕刻程序在上述介電層 22、氮氧化矽層24、犧牲氧化層26中定義出接觸窗 (conhct)或介層窗（via)以露出其下之金屬矽化物或導線 金屬（未顯示）。然後，先在基底上沿著接觸窗或介層窗的 輪廓沈積一阻障層28，再進行全面性的鎢沈積製程16, 28, 34 ~ barrier layer; 18, 30, 36 ~ metal layer; 19 ~ interconnecting trench; 26 ~ sacrificial oxide layer; 26 '~ residual sacrificial oxide layer. Example Please refer to FIG. 2A, which shows the initial steps of this example. The part below the dielectric layer 22 may contain several layers of metal interconnects and several electrically connected semiconductor components, such as Mos transistors, resistors, and logic components. I: In terms of the dielectric layer, Semiconductor substrates and integrated circuits below 22 are denoted by reference numeral 20. The dielectric layer 22 may be a single layer or several layers made of silicon nitride, borosilicate glass, borophosphosilicate glass, or other low dielectric constants such as FURE, PAE-2, FSG, HSQ, etc. However, it is simply indicated by reference numeral 22 here. In a conventional manner, a silicon oxynitride layer is first deposited on the dielectric layer 22 as an etch stop layer defining an interconnect trench in the future. Then, according to the method, an oxide layer 26 is further deposited on the silicon oxynitride layer 24 as a sacrificial layer. This sacrificial oxide layer can be deposited by using plasma enhanced chemical vapor deposition (PECVD) to a thickness of about 1,000 Aye. Please refer to FIG. 2B, and then use a lithography and etching process to define a contact window (via) or a via (via) in the dielectric layer 22, the silicon oxynitride layer 24, and the sacrificial oxide layer 26 to expose the underlying Metal silicide or wire metal (not shown). Then, a barrier layer 28 is deposited on the substrate along the outline of the contact window or via window, and then a comprehensive tungsten deposition process is performed.
五、發明說明（5) (blanket WCVD process)。對鎢而言，常用的阻障/黏著 層為鈦/氮化鈦（Ti/TiN)或鎢化鈦（Tiw)。鎢金屬層3〇的沈 積，一般是以兩階段的反應，先以較緩和少量s丨扎與WFe反 應生成一均勻之成核層（nucleation layer)，再以大量H2 與快速成長鎢膜，其厚度約5000〜8000埃。此步驟之反 應溫度約在4 00〜800 °C之間’壓力則控制在卜1〇〇 T〇rr& 右。 請參照第2C圖，以化學機械研磨法去除多餘的鎢金屬 層以形成鎢插塞，在研磨的最後，並以一道氧化物拋光 (oxide buff ing)將研磨所產生的到痕去除。拋光的過程 中，可將大部分的犧牲氧化層去除而不會對製程造成影 響，而底下的氮氧化矽層24在犧牲層的覆蓋下將可保持完 整。 請參照第2D圖，接下來的步驟是製作鑲嵌式内連線， 首先在基底既有的結構上沈積介電層32作為導線介電質5. Description of the invention (5) (blanket WCVD process). For tungsten, the commonly used barrier / adhesive layer is titanium / titanium nitride (Ti / TiN) or titanium tungsten (Tiw). The deposition of the tungsten metal layer 30 is generally a two-stage reaction. First, the reaction with WFe is moderated to generate a uniform nucleation layer, and then a large amount of H2 is used to rapidly grow the tungsten film. The thickness is about 5000 ~ 8000 angstroms. The reaction temperature in this step is about 400 ~ 800 ° C, and the pressure is controlled at 100 Torr & right. Referring to FIG. 2C, a chemical mechanical polishing method is used to remove the excess tungsten metal layer to form a tungsten plug. At the end of the polishing, an oxide buff ing is used to remove the traces generated by the polishing. During the polishing process, most of the sacrificial oxide layer can be removed without affecting the process, and the underlying silicon oxynitride layer 24 will remain intact under the coverage of the sacrificial layer. Please refer to Figure 2D. The next step is to make a mosaic interconnect. First, a dielectric layer 32 is deposited on the existing structure of the substrate as the wire dielectric.
Cli^e dielectric)，然後以微影與蝕刻程序在介電層32 中疋義出内連線溝槽，並露出先前所形成之鎢插塞3〇。在 蝕刻内連線溝槽的過程中，由於作為蝕刻終點的氮氧化矽 層2 4係保持在完整的狀態下，因此該蝕刻步驟將可得到良 好的控制，同時也可避免金屬導線有厚度不一致的情形出 現。 之後’沿著基底上既有的輪廓沈積一阻障層34，此擴 ，阻障層可幫助後續金屬的附著並防止其擴散，對銅而 S，適當的擴散阻障層材料包括：鈕（Ta)，氮化鈕Cli ^ e dielectric), and then define the interconnect trenches in the dielectric layer 32 by lithography and etching procedures, and expose the tungsten plug 30 previously formed. In the process of etching the interconnecting trenches, since the silicon oxynitride layer 24 as the end point of the etching is maintained in a complete state, the etching step can be well controlled, and the thickness of the metal wire can be avoided. The situation arises. Afterwards, a barrier layer 34 is deposited along the existing contour on the substrate. This expansion layer can help the subsequent metal adhesion and prevent its diffusion. For copper and S, suitable diffusion barrier materials include: button ( Ta), nitride button
第8頁 五、發明說明（6) ' (TaN) ’氮化鎢（wn) ’或是習知製程中常用的氮化鈦 (TiN)。接著，在阻障層上沈積一銅導電層，並使其填滿 内連線溝槽。較佳者’可利用離子化金屬電漿（IMp)先在 基底上沈積一層的晶種層，然後再以電鍍法完成銅導電層 的沈積。之後，以介電層32為研磨終點進行化學機械研 磨’而在内連線溝槽中留下銅導線36，即完成鑲嵌 線的製作。 硬 綜上所述’本發明所提出之金屬化製程，藉由一犧牲 層的保護，可避免蝕刻終止層在拋光的過程中受到損宝。 如此’在後續蝕刻内連線溝槽時將可得到較好的控 了、 提高金屬内連線的可靠度。 工’以 雖然本發明已以一較佳實施例揭露如上，然其並 以限定本發明，任何熟習此技藝者，在不脫離本發 = 神和範圍内，當可作各種之更動與潤飾，因此本發 護範圍當視後附之申請專利範圍所界定者為準。 保Page 8 V. Description of the invention (6) '(TaN)' Tungsten nitride (wn) 'or titanium nitride (TiN) commonly used in conventional processes. Next, a copper conductive layer is deposited on the barrier layer to fill the interconnect trenches. The better one can use an ionized metal plasma (IMp) to deposit a seed layer on the substrate first, and then complete the copper conductive layer deposition by electroplating. After that, chemical mechanical polishing is performed with the dielectric layer 32 as the polishing end point, and the copper wire 36 is left in the interconnecting groove, thereby completing the fabrication of the damascene line. Hard In summary, the metallization process proposed by the present invention can prevent the etch stop layer from being damaged during the polishing process by the protection of a sacrificial layer. In this way, better control can be achieved during subsequent etching of the interconnect trenches, and the reliability of the metallic interconnects can be improved. Although the present invention has been disclosed as above with a preferred embodiment, it also limits the present invention. Anyone skilled in this art can make various changes and decorations without departing from the scope of the present invention. Therefore, the scope of this protection shall be determined by the scope of the attached patent application. Guarantee
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