A7 B7 4^84 87 五、發明說明（/ ) 發明背景上 本發明大致係關於半導體元件，尤其是具有淺絕緣溝 渠之半導體元件。 如習知之技術，形成在半導體積體電路中之工作元件 係用介電質作電性絕緣，其形成在矽基板中之元件的絕 緣技術.係在元件之間形成二氧化矽區，此種技術有時 稱為鬲部氧化（LOCOS)過程，其中在元件之間的矽曝露 區會氧化，而形成場氧化區，在另一種技術方面，還有 一種所謂的淺絕緣溝渠（STI)技術，其會先在矽曝露區形 成淺溝渠，然後再用介電質，通常為TE0S,將其填滿，在 埴滿該溝渠之前，要先在包含溝渠側壁之表面上，以熱 氯化法成長一二氣化矽薄層，其次，再用化學氣相沈積 法沈稽一氮化矽薄層在該二氧化矽上，之後，再沈積一 TE0S層在該氮化矽之上，其中部分的TE0S會填滿溝渠， 然後，在TE0S的稠化處理期間，通常會將此結構進行濕 式m火，該氮化矽層係用μ防止氧在濕式退火期間進人 矽中，換言之，氮化矽會防止矽溝渠側壁氧化，否則， 此種氧化容易在矽中產生不想要的應力和晶體差排，然 後再移除TE0S的上部，Μ曝露出毗鄰STI區之矽表面的 部分，再將矽表面氧化用Μ當作閘極氧化物，最後在該 閘極氧化物上形成摻雜多晶矽，並且用微影製程將其製 作成將要形成M0SFET元件之閘極電極的圖案。 再如習知之枝術，有痤積體電路會使用在η通道上 有Ρ通道之η通道MOSFETs,如DRAM,記憶體單胞陣列係 -3 _ 本紙張尺度適用中國國家標準（CNS)A4規格（210x 297公釐) ： ^-----裝-------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 4 184 BT ， - -^---一 _ 五、發明說嗎（> ) 提供在電路的某一區，而輔肋電路，如位址和邏輯電路 ，則I形成在電路的另一區，如環繞在陣列區週邊，一 棰梨式之DRAM單睢包含一連接到埋入，或溝渠電容器之 Μ Π S F E T ,如h所述，若沒有沿著S I T溝渠側壁之氮化物 挚圈，則溝渠的矽側堅會在用以稠化T E 0 S的濕式退火期 間受到氧化，此種氧化會在矽中造成應力和差排，因而 減Φ DRAM單睢的電荷保持時間，因此，需要在絕緣溝渠 側鞮上形成一氧化矽層，K保護矽側壁，此外，當用在 陣列中之MOSFETs為n-FET元件時，輔助電路可包含P-FET 元件，再者，當兩種型式之M0SFET具有大致相同之工作 兩數時，為了要使P-MOSFETs和n-MOSFETs所用的多晶矽 使用相同型式的摻雜，P-M0SFET元件會採用埋人通道 M0SFET ° 發明.概並_ 根據本發明，提供一種在矽本體中形成電性絕緣半導 餺元件之方法，溝渠會形成本體的選擇區，障壁材科沈 積在該溝渠的側壁上，部分的障壁材料會自溝渠的第一 側壁部分移除，Μ曝露溝渠的第一側壁部分，但是保留 部位位在溝渠第二側壁部分之上的障壁材料，Μ在其上 形成一障壁層，有一介電質材料沈積在溝渠之中，該介 雷質材料的一部分係沈積在曝露之溝渠的第一側壁部分 上.而此沈積之介電質材料的另一部分則會沈積在該障 荦材料之上，該介電質材料要在氧化環境中退火，Κ稠 化此稱沈積的介甯質材料，該障壁層會防止溝渠之該第 -4- 本紙張尺度適用中國國家標準（CNS)A4規格（2]0 X： 297公釐） 1 . 裝--------訂---------線 <請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 A7 _B7_ 五、發明說明（4 ) 二側壁部分氧化，許多形成在矽本體中之半導體元件， 其係藉由溝渠中的介電質材料作元件的電性絕緣。 根撺太發明之另一特激，工作元件的形成步驟，包含 :形成一 丁作元件當作P-MOSFET,和形成另一個工作元 件當作n-MOSFET。 根撺本發明之又一特戤，該形成步驟包含：形成一元 件當作埋人通道元件。 根據本發明之再一特徵，該形成工作元件之步驟包含 ：形成一工作元件當作毗鄰溝渠第一側壁部分之埋人通 道元件。 拫據本發明之仍一特徵，該形成障壁材料之步驟包含 :形成氮化矽之障壁材料。 根撺本發明之又再一特激，本發明所提供之半導體结 櫞具有一位在矽本體中之溝渠，此溝渠具有側壁部分， 有一障荦材料位在側檗的第二部分之上，Μ提供一沿溝 渠測擊部分排列之障壁材料，至於側壁的第一部分，則 並未繪著該障壁材料，有一介電質材材位在溝渠之中， 一部分的介電質材料會與塗著在溝渠的側壁第二部分之 障壁材料接觸，而介電質材料的另一部分則與溝渠的側 荦第一部分接觸，一對工作元件係位在矽本體之中，此 種元件傜利用溝渠中的介電質工作電性絕緣。 根撺本發明之仍再一特激^工作元件的其中之一為f>-MOSFET,而另一個工作元件則是n-MOSFET。 拫據本發明之仍再一特徵，元件的其中之一為埋入通 -5 — 本紙張尺度適用中國國家標準（CNS>A4規格（210 X 297公釐） J. j 裝·! -----訂----I----線 (請先閱讀背面之注意事項再填寫本頁) A7 4184 _B7_ 五、發明說明（* ) 通元件。 拫據本發明之仍再一特徵，工作元件的其中之一為鄰 沂溝渠的側筚第一部分之埋入通道元件。 _式簡單..說.朋_ 當參考相關的圖式時，本發明及其他特徵將會圼更明 瞭，其中： 第1Α-1ί圖為根據本發明之電性絕緣MOSFEh其在製造 時之各階段横截面圈； 第2圖為示於第II圖之一 M0SFET的平面圖，在第II圖 中，此M0SFET之横截面被取為第2圖之線11-11;及 第3圖為示於第2圖之M0SFET的横截面圖，其取第2 圖沿矂3 - 3之區域。 較佳實.1.例.JOI.... 琨在參考第1A_,其圖示一種半導體本體或基板1〇, 此處為P型導電性矽，在基板10之上表面上，以熱氧化 法成長一二氧化之層12,此處厚度之範圍為5〇S,沈積 一氮化矽之層1 4 ,此處係利用化學氣相沈積法（C V D ),其 沈積在二氧化矽層12上之的厚度範圍為250〇S,如圔所示。 接著參考第1B圖，在氮化矽層14之上，沈積一光阻層 16.再利用微影製程製作圖案，如圖所示，使在基板10 之區域上的光咀層16中形成窗口 18,此係為了要形成STI ^溝屬因此，如第1B圖所示，製作成圖案之光阻層16 係要當作鈾刻遮罩，然後蝕刻掉结構的暘露部分，此處 傜利用乾式飩式，先移除藉由窗口 18而曝露之氮化矽層 -6 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 7---Γ------------訂-----^--ί 線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印紫 經濟部智慧財產局員工消費合作社印製 4 184 87 A7 _B7___ 五、發明說明（） 14的部分，再去除光砠曆16,其次，使用製成圖案之氮 化砂圃1 4當作蝕刻遮罩，在此處係利用乾式蝕刻移除在 其下之二氧化矽12已曝露的部分，因此可Μ曝露在下面 之的基板1 0的表面部分，其次，蝕刻矽的曝露部分，此 處使用乾式蝕刻，使在矽基1 0的表面之中形成溝渠2 0， 如第1 C _所示。 其次參考第11)圖，在溝渠20的壁22(第1C圖）之上，Μ 熱氣化法成畏厚1 0 〇〖'之二氧化矽薄曆2 4 ,然後.在該结 構上沈積一障壁材料•此處為墊圈，或氮化矽層26,此 處，該氮化矽瞟2 6係利用化學氣相沈積法沈積，而其厚 度刖約為6 0 $。 其次參考第1E圖，在該结構之表面上沈積一光阻層28 .並利用徹影製程製作圖案，以提供當作遮罩，注意， 由光阳睛28所提供之進罩，其所曝露之區域為要形成η 型導電性井30之ρ型導電性基板10,另外遒須注意：由 光阳層28所提供之遮罩，當此遮罩具有孔徑時，其係位 在溝渠20之側壁部分32上，Μ曝露溝渠20之不同的側壁 部分34,尤其，基於更明顯之原因，該製作成圖案之光 阳層28係曝露出側壁部分34,其位在η型導電性井30的 周園τ但是，就此而言，η型導電性井30將形成Ρ在通道 M0SFET元件之中，而在Ρ型導電性基板之中，利用溝 蕖20作電性絕緣之區36,將會形成在η通道M0SFET元件 之中。 在製作好示於第1Ε圖之光狙層28之後，蝕刻該结構， -7- 本紙張尺度適用t國國家標準（CNS)A4規格（2】0 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝--------訂-----^----•線_ A7 4184 87 B7_ 五、發明說明（心） 此處係利用乾式蝕刻，以移除由光阻層2 8中之孔徑所曝 光的部分氮化矽層2 6 ,如第1 E圖所示，注意，該蝕刻係要 柊除位在溝渠20之側壁部分34上之氮化矽層26的部分，而 保由位存溝渠2 0之側壁部分3 2上之氮化矽層2 6的部分，另 外選須注意：位在溝渠20之底部上，由製成圖案之光阻層 28曝靄之氮化矽層26的部分，其也會被移除，而且位在 溝渠20之底部上，由製成園案之光阻層28覆蓋之氮化矽 圃2 的部分也會被保留。 其次.離子佈植一適當的ti型導電性摻雜物，此處為 瞵，或將其擴散進入由製成圖案之光咀層23曝露的矽部 分，Μ製造η型導電性井30,如第1E圖所示。 其次，參考第1F画，去除光阻層28,然後在該结構的表 而卜.沈積一二氧化矽介電質材料38,此處為TE0S,此TE0S 的部分會沈積在溝渠20之中，如第1F圖所示，而部分的 材料38會延伸在氮化5夕層14上，這個部分未圖示，然後 再將該結構作濕式退火，Μ稠化TE0S材料38,該氮化矽 瞟2 6偁用Μ防ih :在濕式退火期間所產生之氧進入部分 的矽基板10,其為要形成η通道M0SFET元件的部分，即 區3 6 ,換言之，氮化矽層2 6會防止矽溝渠側壁氧化，否 目丨J,此棰氧化會很容易在矽基板中產生不想要的應力和 晶體差排，也就是說t介電質材料38係在氧化的環境中 作退火，以稠化該沈積之介電質材料3δ,而該障壁氮化 碑層2 6會防止溝渠20的側壁部分32氧化，但是，要注意 的是大約沈積在η型導電性井30四周之側壁部分34(即 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------.---.----t· —------訂------^----線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 A7 4184 87 B7_ 五、發明說明（7 ) 要形成P通道MflSFET之區域）沒有氮化矽層26,因此可 W消除ΐ擾P通道MOSFETs的電子來源，此處藉由化學 機槭摁光法（CMP)移除TE0S材料38的上部分，此未圖示， W形成示於第1 F圖之结構。 接著，利用一具有窗口之光阻遮罩，遮住該结構之表 而ί未圖示），其中在該窗口之中係曝露N型井區30,然後 棺Λρ犁導電性摻雜離子，此處為硼，穿透氮化矽層14 和二氣化矽圄1 2的曝露部分，係離子活化退火過後，會 存η犁導電性井30中，形成Ρ型導電性埋人通道區42, 如第1 F圖所示。 其次，移除氮化矽層1 4和二氧化矽層1 2 ,此處係利用 褥式蝕刻法去除，使曝露出矽基板10的表面部分。然後 .參考第〗G匾，以熱氧化法成長一二氧化矽層40,如画 所示，其會進人矽基板10所曝露的表面部分，之後，在 該二氧化矽層40之上，沈積一 η +型導電性摻雜多晶矽層 44,如第ΊΗ圃所示，然後再在該多晶矽層44之上沈積一 導窜層46,此處為鋁，如第U圈所示，將該二氧化矽層 40,揆雜多晶矽暦44,和導電層46製作成用於M0SFET元 件之閘極電極50的圖案，如示於第2和3圖之ρ通道M0SFET 元件54,因此，該Ρ通道M0SFET元件54具有源極和汲極 區60 ,62,此外，該元件54係利用位'在該元件54周邊之介 電質材料38作電性絕緣，另外還需注意：側壁部分34並 沒有被氮化矽層26覆蓋，注意，參考第II圖，在區36中 製作一 n-MOSFET元件60,該區係藉由具有氮化矽層26之 -9- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---------.------------訂—--------- — (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 ' 4 184 87 A7 _B7五、發明說明（J ) Φ 附 所 在 也 例 施 實 的 他 其 而。 , 中 緣圍 絕範 性和 電神 作精 3 的 區圍 與範 ，利 渠專 溝請 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用令國國家標準（CNS)A4規格（210 X 297公釐） B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（9 ) 符號之說明 1 0 . .基 板 12. .二 氧 化 矽 層 14. * * •氮 化 矽 層 16, * * .光 m 層 18. .窗 口 20 . .溝 渠 22 . .壁 24 . •- 氧 化 矽 層 26 . •氮 化 矽 層 28 . 光 咀 層 30 . ,η 型 1ST 電 性 井 32 , 34 .側 壁 部 分 36 . .區 38 . _ TE0S材 料 40 . •二 氧 化 矽 層 42 . .埋 入 通 道 區 44 . •摻 雜 多 晶 矽 層 46 . ，導 電 層 50 . .閘 極 電 極 54 . ,Ρ 通 道 M0SFET元件 60 . •源 極 區 62 . .汲 極 區 -11- ---IM---1 ----I---訂 ------I---- (諳先閱讀背面之泫意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）A7 B7 4 ^ 84 87 V. Description of the Invention (/) Background of the Invention The present invention relates generally to semiconductor devices, especially semiconductor devices having shallow insulation trenches. As is known in the art, a working element formed in a semiconductor integrated circuit is made of a dielectric material for electrical insulation, and the insulating technology of the element formed in a silicon substrate. A silicon dioxide region is formed between the elements. The technology is sometimes called the LOCOS process, in which the silicon exposed areas between the elements will oxidize, forming a field oxidation area. In another technology, there is also a so-called shallow insulation trench (STI) technology. It will form a shallow trench in the silicon exposed area, and then fill it with a dielectric, usually TE0S. Before filling the trench, it must be grown on the surface containing the sidewall of the trench by thermal chlorination. One or two thin layers of siliconized gas, followed by chemical vapor deposition of a thin layer of silicon nitride on the silicon dioxide, and then a TEOS layer was deposited on the silicon nitride, part of which TE0S will fill the trench. Then, during the TE0S thickening process, this structure is usually subjected to wet m fire. The silicon nitride layer uses μ to prevent oxygen from entering the silicon during wet annealing. In other words, nitrogen Siliconization prevents oxidation of silicon trench sidewalls, no This kind of oxidation is easy to generate unwanted stress and crystal difference in silicon, and then remove the upper part of TEOS, and expose the part of the silicon surface adjacent to the STI region, and then use the surface oxidation of silicon as the gate oxidation Finally, doped polycrystalline silicon is formed on the gate oxide, and it is fabricated into a pattern of a gate electrode of a MOSFET device by a lithography process. Another example is the conventional branching technique. There are acquiescent body circuits that use n-channel MOSFETs with p-channels on the n-channel, such as DRAM, memory cell array system-3 _ This paper standard applies to China National Standard (CNS) A4 specifications (210x 297 mm): ^ ----- installation ------- order --------- line (please read the notes on the back before filling this page) Intellectual Property Bureau of the Ministry of Economic Affairs Printed by employee consumer cooperatives. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs. Printed by employee consumer cooperatives. 4 184 BT,--^ --- 一 _ V. Inventions (>) Provided in a certain area of the circuit, and auxiliary rib circuits, such as Address and logic circuits, then I is formed in another area of the circuit, such as around the array area, a pear-shaped DRAM unit contains an M Π SFET connected to a buried or trench capacitor, as described in h If there is no nitride ring along the side wall of the SIT trench, the silicon side of the trench will be oxidized during the wet annealing to thicken TE 0 S. This oxidation will cause stress and differential discharge in the silicon. Therefore, the charge retention time of the Φ DRAM unit is reduced. Therefore, a silicon oxide layer needs to be formed on the side of the insulation trench to protect the K. In addition, when the MOSFETs used in the array are n-FET elements, the auxiliary circuit may include P-FET elements. Furthermore, when the two types of MOSFETs have approximately the same number of operations, in order to make the P- Polycrystalline silicon used for MOSFETs and n-MOSFETs uses the same type of doping. The P-M0SFET device will use the buried channel M0SFET ° invention. Generality _ According to the invention, a method for forming an electrically insulating semiconductor device in the silicon body is provided. In the method, the trench will form a selection area of the body. The barrier material will be deposited on the sidewall of the trench. Part of the barrier material will be removed from the first sidewall portion of the trench. A barrier material above the second side wall portion of the trench. A barrier layer is formed thereon, and a dielectric material is deposited in the trench. A portion of the dielectric material is deposited on the first sidewall portion of the exposed trench. The other part of the deposited dielectric material will be deposited on the barrier material. The dielectric material will be annealed in an oxidizing environment, which will thicken the so-called deposited dielectric material. The barrier layer will prevent the ditch. This paper size is applicable to the Chinese National Standard (CNS) A4 specification (2) 0 X: 297 mm. ------ line < Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 _B7_ V. Description of the invention (4) The two side walls are partially oxidized, many of which are formed on the silicon body In the semiconductor device, the dielectric material in the trench is used as the electrical insulation of the device. According to another special invention of the invention, the forming step of the working element includes: forming a single working element as a P-MOSFET, and forming another working element as an n-MOSFET. According to still another feature of the present invention, the forming step includes: forming an element as a buried channel element. According to still another feature of the present invention, the step of forming a working element includes: forming a working element as a buried channel element adjacent to a first side wall portion of the trench. According to still another feature of the present invention, the step of forming a barrier material includes forming a barrier material of silicon nitride. Based on yet another excitement of the present invention, the semiconductor junction provided by the present invention has a trench in the silicon body, the trench has a side wall portion, and a barrier material is located on the second portion of the side wall. Μ provides a barrier material arranged along the trench test part. As for the first part of the side wall, the barrier material is not painted. A dielectric material is located in the trench. A part of the dielectric material is coated with the dielectric material. The barrier material is in contact with the second part of the side wall of the trench, while the other part of the dielectric material is in contact with the first part of the side of the trench. A pair of working elements are located in the silicon body. Dielectrics work electrically insulated. According to the present invention, one of the still further active working elements is an f > -MOSFET, and the other working element is an n-MOSFET.拫 According to still another feature of the present invention, one of the components is Buried Tong-5 — This paper size applies to the Chinese National Standard (CNS > A4 specification (210 X 297 mm) J. j package ·! --- --Order ---- I ---- line (please read the notes on the back before filling this page) A7 4184 _B7_ V. Description of the invention (*) Pass element. 拫 According to still another feature of the present invention, work One of the components is the buried channel component of the first part of the side of the adjacent ditch. _Style is simple .. said. Friends _ When referring to related drawings, the present invention and other features will become clearer, of which: Figures 1Α-1ί are cross-section rings of the electrically insulating MOSFEh according to the present invention at various stages during manufacturing; Figure 2 is a plan view of the M0SFET shown in Figure II; in Figure II, the horizontal The cross-section is taken as line 11-11 of Fig. 2; and Fig. 3 is a cross-sectional view of the MOSFET shown in Fig. 2, which is taken along the area of Fig. 2 along 矂 3-3. Better. 1. Example .JOI .... 琨 Reference 1A_, which shows a semiconductor body or substrate 10, here is a P-type conductive silicon, which is grown on the surface of the substrate 10 by a thermal oxidation method. The layer of dioxide 12 has a thickness of 50 s here, and a layer of silicon nitride 14 is deposited. Here, a chemical vapor deposition (CVD) method is used, which is deposited on the silicon dioxide layer 12 The thickness range is 250 ° S, as shown by 圔. Next, referring to FIG. 1B, a photoresist layer 16 is deposited on the silicon nitride layer 14. Then, a pattern is formed by a lithography process, as shown in the figure, so that the substrate A window 18 is formed in the optical nozzle layer 16 on the area of 10, which is to form STI. Therefore, as shown in FIG. 1B, the patterned photoresist layer 16 is used as a engraved mask, and then The exposed part of the structure is etched away. Here, the dry silicon type is used to remove the silicon nitride layer exposed through the window 18-6-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) Li) 7 --- Γ ------------ Order ----- ^-ί line (please read the precautions on the back before filling this page) Staff Consumption of Intellectual Property Bureau of the Ministry of Economic Affairs Co-operative printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by the Consumer Cooperative of the employee 4 184 87 A7 _B7___ V. Part of the description of the invention (14), and then the photo calendar 16 is removed, followed by the pattern The nitrided sand garden 14 is used as an etching mask. Here, the exposed portion of the silicon dioxide 12 underneath is removed by dry etching. Therefore, the surface portion of the substrate 10 that can be exposed below can be exposed. Next, the exposed part of the silicon is etched, and dry etching is used here to form a trench 20 in the surface of the silicon substrate 10, as shown in 1C_. Secondly, referring to FIG. 11), the wall 22 of the trench 20 (Figure 1C) On top of the M thermal gasification method, the thickness of the silicon dioxide thin film is 100, and then a barrier material is deposited on the structure. Here is a gasket, or a silicon nitride layer. 26. Here, the silicon nitride rhenium 26 is deposited by a chemical vapor deposition method, and the thickness thereof is approximately 60 $. Secondly, referring to FIG. 1E, a photoresist layer 28 is deposited on the surface of the structure. A pattern is used to make a pattern to provide a mask. Note that the mask provided by Guangyang 28 is exposed. The area is the p-type conductive substrate 10 of the n-type conductive well 30. In addition, it should be noted that the mask provided by the light-emitting layer 28 is located in the trench 20 when the mask has an aperture. On the side wall portion 32, the different side wall portions 34 of the trench 20 are exposed. In particular, for more obvious reasons, the patterned solar layer 28 exposes the side wall portion 34, which is located in the n-type conductive well 30. Zhou Yuan τ However, in this regard, the n-type conductive well 30 will form P in the channel MOSFET element, and in the P-type conductive substrate, the trench 36 using the trench 20 as an electrical insulation will be formed. Among the n-channel MOSFET devices. After making the light layer 28 shown in Figure 1E, the structure is etched. -7- This paper size is applicable to the national standard (CNS) A4 specification (2) 0 X 297 mm. (Please read the back Note for this page, please fill in this page) -------- Order ----- ^ ---- • Line_ A7 4184 87 B7_ V. Description of the Invention (Heart) Here, dry etching is used to remove Except for the portion of the silicon nitride layer 2 6 exposed by the aperture in the photoresist layer 28, as shown in FIG. 1E, note that the etching is to remove the silicon nitride located on the sidewall portion 34 of the trench 20. The part of layer 26, and the part of silicon nitride layer 26 on the side wall portion 32 of the retention trench 20, is also selected. In addition, it should be noted that: the photoresist layer is patterned on the bottom of the trench 20. 28 The exposed portion of the silicon nitride layer 26 will also be removed, and it will be located on the bottom of the trench 20, and the portion of the silicon nitride garden 2 covered by the photoresist layer 28 made in the garden will also be removed. Reserved. Secondly, implant an appropriate ti-type conductive dopant, here, rhenium, or diffuse it into the silicon portion exposed by the patterned optical nozzle layer 23 to manufacture the η-type conductive well 30, such as Figure 1E. Secondly, referring to the first drawing, the photoresist layer 28 is removed, and then the surface of the structure is deposited. A silicon dioxide dielectric material 38 is deposited here, TE0S, and a portion of this TE0S will be deposited in the trench 20, As shown in FIG. 1F, a part of the material 38 will extend on the nitride layer 14. This part is not shown, and then the structure is wet-annealed, and the TE0S material 38 is thickened. The silicon nitride瞟 2 6 偁 Mh ih: the silicon substrate 10 where the oxygen generated during the wet annealing enters part is the part where the n-channel MOSFET element is to be formed, that is, the region 3 6, in other words, the silicon nitride layer 26 will Prevent oxidation of the side walls of silicon trenches. If this is not the case, this oxidation will easily generate unwanted stresses and crystals in the silicon substrate. In other words, the t dielectric material 38 is annealed in an oxidizing environment. The deposited dielectric material 3δ is thickened, and the barrier nitride layer 26 prevents the sidewall portion 32 of the trench 20 from oxidizing. However, it should be noted that the sidewall portion 34 is deposited approximately around the n-type conductive well 30 (That is, this paper size applies to China National Standard (CNS) A4 (210 X 297 mm)) ------.---.--- -t · —------ Order ------ ^ ---- line (Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 4184 87 B7_ V. Description of the invention (7) The region where the P-channel MflSFET is to be formed) has no silicon nitride layer 26, so it can eliminate the electron source that disturbs the P-channel MOSFETs. Here, it is removed by CMP The upper part of the TEOS material 38, which is not shown here, W forms the structure shown in FIG. 1F. Then, a photoresist mask with a window is used to cover the surface of the structure (not shown), in which the N-type well region 30 is exposed, and then the conductive doped ions are deposited. It is boron. It penetrates the exposed part of the silicon nitride layer 14 and the silicon dioxide layer 12. After the ion activation annealing, it will be stored in the η plow conductive well 30 to form a P-type conductive buried channel region 42, As shown in Figure 1 F. Next, the silicon nitride layer 14 and the silicon dioxide layer 12 are removed. Here, the silicon nitride layer 14 and the silicon dioxide layer 12 are removed by a mattress etching method, so that the surface portion of the silicon substrate 10 is exposed. Then, referring to the first plaque G, a silicon dioxide layer 40 is grown by a thermal oxidation method. As shown in the drawing, it will enter the exposed surface portion of the silicon substrate 10, and then, on the silicon dioxide layer 40, A η + -type conductively doped polycrystalline silicon layer 44 is deposited, as shown in the second step, and then a channeling layer 46 is deposited on the polycrystalline silicon layer 44, which is aluminum, as shown in the Uth circle. The silicon dioxide layer 40, the doped polycrystalline silicon wafer 44 and the conductive layer 46 are made into a pattern for the gate electrode 50 of the MOSFET device, such as the p-channel MOSFET device 54 shown in Figs. 2 and 3. Therefore, the p-channel The MOSFET element 54 has source and drain regions 60 and 62. In addition, the element 54 is electrically insulated by a dielectric material 38 located at the periphery of the element 54. It should also be noted that the sidewall portion 34 is not The silicon nitride layer 26 is covered. Note that, referring to FIG. II, an n-MOSFET device 60 is fabricated in the region 36. This region is provided with a silicon nitride layer 26-9. ) A4 specification (210 X 297 mm) ---------.------------ Order —--------- — (Please read the first Please fill in the matters needing attention (This page) Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs' 4 184 87 A7 _B7 V. Description of Invention (J) Φ Attachment is also implemented by others. , Zhongyuanwei's Exorbitant and Electricity Mastery 3's Areas and Fans, Liqu Special Ditch Please (Please read the precautions on the back before filling this page) The Intellectual Property Bureau of the Ministry of Economic Affairs Employee Consumer Cooperatives Print this paper scale Applicable national standard (CNS) A4 specification (210 X 297 mm) B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (9) Explanation of symbols 10... Substrate 12.. Silicon dioxide layer 14. * * • Silicon nitride layer 16, * *. Light m layer 18. Window 20 ... Ditch 22 ... Wall 24 ... Silicon oxide layer 26. Silicon nitride layer 28. Optical nozzle layer 30. , η-type 1ST electrical wells 32, 34. Side wall portions 36 .. Region 38. TEOS material 40. Silicon dioxide layer 42. Buried channel region 44. Doped polycrystalline silicon layer 46. Conductive layer 50. .Gate electrode 54., P channel M0SFET element 60. • Source region 62.. ---- (Please read the notice on the back before filling in this ) This paper scale applicable Chinese National Standard (CNS) A4 size (210 X 297 mm)