TW411614B - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
TW411614B
TW411614B TW088103825A TW88103825A TW411614B TW 411614 B TW411614 B TW 411614B TW 088103825 A TW088103825 A TW 088103825A TW 88103825 A TW88103825 A TW 88103825A TW 411614 B TW411614 B TW 411614B
Authority
TW
Taiwan
Prior art keywords
layer
fuse
fuse layer
virtual
aforementioned
Prior art date
Application number
TW088103825A
Other languages
English (en)
Chinese (zh)
Inventor
Hiroaki Seikikawa
Kakutaro Suda
Hideki Doi
Yasuhiro Ido
Takeshi Iwamoto
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Application granted granted Critical
Publication of TW411614B publication Critical patent/TW411614B/zh

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H01L23/5258Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Recrystallisation Techniques (AREA)
TW088103825A 1998-06-19 1999-03-12 Semiconductor device TW411614B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17312098A JP4390297B2 (ja) 1998-06-19 1998-06-19 半導体装置

Publications (1)

Publication Number Publication Date
TW411614B true TW411614B (en) 2000-11-11

Family

ID=15954519

Family Applications (1)

Application Number Title Priority Date Filing Date
TW088103825A TW411614B (en) 1998-06-19 1999-03-12 Semiconductor device

Country Status (5)

Country Link
US (1) US6259147B1 (enExample)
JP (1) JP4390297B2 (enExample)
KR (1) KR100334598B1 (enExample)
DE (1) DE19912490C2 (enExample)
TW (1) TW411614B (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6562674B1 (en) * 1999-07-06 2003-05-13 Matsushita Electronics Corporation Semiconductor integrated circuit device and method of producing the same
JP3907911B2 (ja) 2000-03-30 2007-04-18 Necエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
DE10026926C2 (de) * 2000-05-30 2002-06-20 Infineon Technologies Ag Halbleiteranordnung mit optischer Fuse
US6784516B1 (en) * 2000-10-06 2004-08-31 International Business Machines Corporation Insulative cap for laser fusing
JP4079600B2 (ja) * 2001-03-06 2008-04-23 株式会社東芝 半導体装置
US6518643B2 (en) * 2001-03-23 2003-02-11 International Business Machines Corporation Tri-layer dielectric fuse cap for laser deletion
JP2003086687A (ja) * 2001-09-13 2003-03-20 Seiko Epson Corp 半導体装置
KR100444722B1 (ko) * 2002-04-08 2004-08-16 아남반도체 주식회사 퓨즈 라인 제조 방법
KR100709434B1 (ko) * 2005-06-27 2007-04-18 주식회사 하이닉스반도체 반도체 소자의 퓨즈 박스
JP5060100B2 (ja) * 2006-10-26 2012-10-31 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
CN119724081B (zh) * 2025-01-15 2025-10-03 闽都创新实验室 一种基于单向截流电流栅调控发光器件驱动方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07263558A (ja) 1994-03-18 1995-10-13 Fujitsu Ltd 半導体装置
JP3256626B2 (ja) * 1994-05-15 2002-02-12 株式会社東芝 半導体装置
TW279229B (en) * 1994-12-29 1996-06-21 Siemens Ag Double density fuse bank for the laser break-link programming of an integrated-circuit
US5589706A (en) 1995-05-31 1996-12-31 International Business Machines Corp. Fuse link structures through the addition of dummy structures
US5636172A (en) * 1995-12-22 1997-06-03 Micron Technology, Inc. Reduced pitch laser redundancy fuse bank structure
JPH09213804A (ja) 1996-01-29 1997-08-15 Mitsubishi Electric Corp ヒューズ層を有する半導体装置
US5851903A (en) * 1996-08-20 1998-12-22 International Business Machine Corporation Method of forming closely pitched polysilicon fuses
US5949323A (en) * 1998-06-30 1999-09-07 Clear Logic, Inc. Non-uniform width configurable fuse structure

Also Published As

Publication number Publication date
DE19912490A1 (de) 2000-01-20
DE19912490C2 (de) 2003-10-16
US6259147B1 (en) 2001-07-10
JP2000012691A (ja) 2000-01-14
KR100334598B1 (ko) 2002-05-02
JP4390297B2 (ja) 2009-12-24
KR20000005616A (ko) 2000-01-25

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Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees