TW409399B - Method for fabricating ferroelectric memory devices capable of preventing volatility of elements in ferroelectric films - Google Patents
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- 239000003990 capacitor Substances 0.000 claims abstract description 23
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- 238000004519 manufacturing process Methods 0.000 claims description 3
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- 229910052762 osmium Inorganic materials 0.000 description 3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
- H01L28/56—Capacitors with a dielectric comprising a perovskite structure material the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
- H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
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- Condensed Matter Physics & Semiconductors (AREA)
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Description
發明說明(1) 領域 本發明和高度積體記憶裝置有關;而更明確地說,a 巧*避免鐵電膜之元素揮發性之鐵電記憶裝置有關。疋和 S前文件之 大體而言,鉑獏已被廣泛使用在高度積體DRAM裝 電極中該dram裝置使用高介電常數物 =低 質,如pzt,在頑磁極化下兩種穩定狀態有數百至數 基於頑磁極化,由鐵磁物質形成的薄膜:本 上用作非揮發性記憶裝置中的電容器。在鐵電膜用^本 發性:憶裝置的例子中,資料是相對於施藉揮 極化方向而耠Q 错控制 '至裝置電谷器而數位信號"〇 n或11 1 ”目卩β 除鉍加的電場藉頑磁極化而儲存。 則疋移 圖1是—側面圖顯示一傳統鐵磁障F 容器的低電極。如圖H : 置有麵膜作為電 由多晶石夕检塞6 — V ’傳統記憶裝置中的電容器是 成。由於_,通一當Λ擴散膜7和一低電極8如麵膜所組 止氧原子擴L^r::;8二不:為障礙膜來防 散膜7,中,夫觸:沾::乳原子攸鉑膜擴散至防止擴 表-場氧化:,3未是觸釋門的口數字1代表半導體基板,2代 而9是鐵電臈、。疋一閘,4疋位元線,5是層間絕緣膜, 膜:=二鈦二廣泛使用作為防止擴散膜7。障礙金属 CVD(化學氣: 用作栓塞的多晶碎膜會從由 、冲礼積)法形成的介電膜跑出來的氣原子激烈
第5頁 五、發明說明(2) ----- ^ Ϊ媒因此,低電極和電晶體活化區間的電力連接中斷。 1鐵電物質沉積溫度的增加,這問題變得更加嚴重。 之一鐵$物質例子中,如^丁,一常用於鐵電電容器物質 C0B(電i =積和結晶所需的溫度非常高。因此,為了在 將鉑低ί極在位元線上)結構上製造鐵電記憶裝置’所以 此結果,電力連接至MOSFET的活化區是非常重要的。如 法。 需要被改善擴散障礙金屬電力特性的其他沉積方 特別來說,帝、、± Α 擴散的氧原子而意鐵電膜的組成能藉揮發性物質和向外 獏,物理沉積而改變。為了生成高品質的鐵電電容器ΡΖΤ 過,在任佃_如射頻電聚錢鍍法可被使用而非CVD ^不 的組成报難和// ,在1^丁沉積後施行熱處理使得ρζτ膜 所致。這些ί U Ϊ t ?揮發性和向外擴散氧造成的空缺 產生空間電荷層而:化二::晶界或區域牆移·,因此而 摘要 向心、化了隨思的極化 因此,太欢 半導f1明的目標是要提供一方 體裝置中Pzτ 去來製造能夠防止在 本發明另一目择曰 缺陷之鐵電電容器。 條件來製造_ & :疋要提供—方法藉控制鐵電物併& # 根據本Ϊ明!善的ΡΖΤ鐵電電容器。 積 電容§1,甘 方面的考里,提供_ 士上 電極i开〃步驟包含:形成—半導雷〜來製造一半導體 電膜上形成—:犋其鐵電暝含蓋一揎| 戈覆盍氧化物祺;對錯街 揮發疋素;在鐵
.電犋和覆蓋氧化物獏施 __409399 _ 五、發明說明(3) 行快速熱製程;然後將鐵電膜冷却,因此在鐵電膜中有較 佳方向排列的原子和區域晶界垂直於提供半導體電容器的 半導體基板。 ™ 圖形的簡要敘述 本發明上述和其他特色會從下面較佳實施例的敘述配合 圖形會變得更加明顯,其中: σ 圖1是側面圖顯示一傳統鐵電記憶裝置其有鉑膜作為— 電容器的低電極;及 圖2Α至2F是側面圖顯示一記憶裝置根據本發明其有一 電膜。 較佳實施例的詳細敘诚 在下文中,一記憶裝置的鐵電電容器會參考附圖來 明。 。 首先,參考圖2Α ,本發明的鐵電記憶裝置包含一平常的 M0SFET(此處未顯示)其由一閘、一源極和沒極($/〇)在_ 半導體基板10内生成,和一鐵電電容器電力耦合至源極和 沒極(S/D)。而且,一用來極化的絕緣膜被被覆在最後結 構上而一曝露半導體基板1 q的部份(源極和汲極)之接觸孔 被形成。接觸孔以用作接觸栓塞1 2的多晶矽膜填滿並電力 連,源極和汲極(S/D)至半導體電容器的低電極'。多晶石夕 膜藉CVD法沉積厚度至5〇〇1至3G(j〇A。 參。考圖2B,鈦膜13在絕緣膜丨1上形成厚度在1〇()至 |00〇A,並與接觸栓塞12保持接觸。_氮化鈦膜“在欽膜 U上形成厚度在20 0至20 0 0《。在形成包含鈦膜13和氛化欽
409398 五、發明說明(4) 膜14的擴散障礙金屬之後,一低電極如鉑膜15在氮化鈦膜 14上形成厚度在1000至5000 Α。藉將翻膜15定型,氮化欽 膜1 4和鉑膜1 5依序形成預定尺寸,一低電極結構丨5 ’就形 成了。 接下來’參考圖2C ’ 一 ΡΖΤ膜形成在絕緣膜11之上,將 低電極結構1 5’覆蓋起來。根據本發明Ρ2Τ膜1 6以射頻電漿 濺鍍法在室溫或低於600 °C下形成厚度在500至200〇ί。 參考圖2D,在形成ΡΖΤ膜16之後,用來作為覆蓋氧化物 臈的SrTi03膜17在ΡΖΤ膜16上形成接著在溫度約450至750 °C下施行快速熱製程3 0至1 2 0秒。而且,一從 BST[Ba(Sr,Ti)〇3](鋇(鏍’鈦)氧化物)所選擇的物質形成 之介電膜可取代SrTi03膜17。在本發明中,用來處理ρζτ 膜16的溫度是以每分鐘超過-30 °C的速率冷却下來以防止 錯揮發。這冷却改變P Z T膜1 6的結構使得p z T膜1 6的較佳方 向和區域晶界垂直於半導體基板1〇(或PZT膜16的沉積表 面)°在本發明中’使用SrT i03膜1 7來防止在ρζτ膜1 6中Pb 錯的揮發之原因是因為SrTi 03膜1 7提供ΡΖΤ膜1 6 —結構穩 定性。亦即,SrTi03膜17在用來ΡΖΤ膜16結晶的快速熱製 裎中會防止鉛的揮發。 ’ 接下來,參考圖2E ’ 一覆蓋膜如矽氧化物膜18在SrTi〇3 膜17之上形成以改善防止鉛揮發的功能,藉選擇蝕刻矽氧 化物膜18和SrTi〇3膜17而曝露出部份的PZT膜16以形.成鐵 電電容器的上層電極。 最後’參考圖2F,上層電極如鉑膜19在曝露的ρζτ膜16
綱 五、發明說明(5) 上形成厚度在5〇〇至2000埃而用作上層 型至預定尺寸。 喈電極的鉑膜19被定 “極:明另一實施例中,在圖2β中被定型的 6和啊膜17生成後可形成。換 ^ t在 順序形成鈦膜13,氮化鈦獏“和㈣5之 極結構15,可藉定❹膜15,I化鈦膜14和 丄d而形成。 冑電電容器的低電極可使用多層結構。例如,多 電容器可由下列步驟形成H㈣厚度在10◦至 、,和形成一二氧化釕或二氧化銥膜厚度在500至 υ川埃。而且,低電極可從金屬膜含鉑,金,銀,鈀, t二釕,銥,銶或它們合金臈中擇一,而更進一步包含傳 氧化物膜,傳導氮化物骐或矽化物骐,其中每一膜包含 釕,銥,銶,鑭,銃或鈷。同理,上層電極可從上述金屬 膜擇一。 如上非常明顯’根據本發明半導體電容器藉防止鉛的揮 發而有保持頑磁極化長時間的效應。而且,本發明藉改變 極化平面方向和區域結構而改善半導體電容器電力特性。 本發明雖僅參考一些特定較佳實施例來說明,但其他修 改和改變可在不偏離本發明的精神和領域内來施行如同在 申凊專利範圍内所敘述。
Claims (1)
- 409399 六、申請專利範圍 1. 一種製造半導體電容器之方法,其步驟包括: 形成半導體電容器的低電極; 形成一鐵電膜在該低電極上,其中第一鐵電膜帶有一 揮發性元件; 形成一覆蓋氧化物膜於鐵電膜之上; 施加一快速熱製程於鐵電膜和覆蓋氧化物膜;及 冷却鐵電膜, 其中在鐵電膜中較佳方向的原子和區域晶界係垂直於 提供半導體電容器的半導體基板。 2. 如申請專利範圍第1項之方法,其中鐵電膜是PZT膜, 藉射頻電漿濺鍍法生成。 3. 如申請專利範圍第2項之方法,其中射頻電漿濺鍍法 是在室溫或低於6 0 0 °C下施行。 4. 如申請專利範圍第3項之方法,其中冷却鐵電膜的步 驟是以每分鐘大於30 °C (-30 °C/min)之速率來施行。 5. 如申請專利範圍第1項之方法,其中該方法更包含在 覆蓋氧化物膜上形成覆蓋膜的步驟。 6. 如申請專利範圍第5項之方法,其中覆蓋氧化物膜是 石夕氧化物膜。 7. 如申請專利範圍第1項之方法,其中覆蓋氧化物膜是 選自 BST[Ba(Sr,Ti )03]材料。 8. 如申請專利範圍第1項之方法,其中低電極是選自包 含顧,金,銀,ίε,斂,釕,銀,棘之金屬膜或其合金 膜。第10頁 409399 :、申請專利範圍 9.如申請專利範圍第8項之方法,其中低電極更包含一 傳導氧化物膜,一傳導氮化物膜或矽化物膜,各包含釕, 銀,鍊,鑛,航或钻。 1 0.如申請專利範圍第8項之方法,其中低電極形成厚度 在1 00至1 0⑽埃。 1 1.如申請專利範圍第1 0項之方法,其中傳導氧化物 膜,傳導氮化物膜或矽化物膜形成厚度在500至5000埃。
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EP1039525A4 (en) * | 1997-11-10 | 2002-02-06 | Hitachi Ltd | DIELECTRIC ELEMENT AND METHOD OF MANUFACTURE |
KR100396879B1 (ko) | 2000-08-11 | 2003-09-02 | 삼성전자주식회사 | 동일 물질로 이루어진 이중막을 포함하는 다중막으로캡슐화된 캐패시터를 구비한 반도체 메모리 소자 및 그의제조 방법 |
WO2002030466A2 (en) * | 2000-10-11 | 2002-04-18 | Purdue Research Foundation | Pharmaceutical applications of hydrotropic agents, polymers thereof, and hydrogels thereof |
KR100389032B1 (ko) * | 2000-11-21 | 2003-06-25 | 삼성전자주식회사 | 강유전체 메모리 장치 및 그의 제조 방법 |
JP2002184951A (ja) * | 2000-12-15 | 2002-06-28 | Mitsubishi Electric Corp | 容量素子を有する半導体装置およびその製造方法 |
KR100451569B1 (ko) * | 2002-05-18 | 2004-10-08 | 주식회사 하이닉스반도체 | 수소배리어막을 구비한 반도체 장치의 제조 방법 |
JP2004179419A (ja) * | 2002-11-27 | 2004-06-24 | Toshiba Corp | 半導体装置及びその製造方法 |
KR100601959B1 (ko) | 2004-07-28 | 2006-07-14 | 삼성전자주식회사 | Ir-Ru 합금 전극 및 이를 하부 전극으로 사용한강유전체 캐패시터 |
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US5614018A (en) * | 1991-12-13 | 1997-03-25 | Symetrix Corporation | Integrated circuit capacitors and process for making the same |
EP0568064B1 (en) * | 1992-05-01 | 1999-07-14 | Texas Instruments Incorporated | Pb/Bi-containing high-dielectric constant oxides using a non-Pb/Bi-containing perovskite as a buffer layer |
US5326721A (en) | 1992-05-01 | 1994-07-05 | Texas Instruments Incorporated | Method of fabricating high-dielectric constant oxides on semiconductors using a GE buffer layer |
US5572052A (en) * | 1992-07-24 | 1996-11-05 | Mitsubishi Denki Kabushiki Kaisha | Electronic device using zirconate titanate and barium titanate ferroelectrics in insulating layer |
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US5471364A (en) * | 1993-03-31 | 1995-11-28 | Texas Instruments Incorporated | Electrode interface for high-dielectric-constant materials |
US5548475A (en) * | 1993-11-15 | 1996-08-20 | Sharp Kabushiki Kaisha | Dielectric thin film device |
US5504330A (en) | 1994-11-22 | 1996-04-02 | Texas Instruments Incorporated | Lead substitured perovskites for thin-film pyroelectric devices |
JP3133922B2 (ja) * | 1995-06-09 | 2001-02-13 | シャープ株式会社 | 強誘電体薄膜被覆基板、その製造方法、及びキャパシタ構造素子 |
JPH0982902A (ja) * | 1995-09-20 | 1997-03-28 | Hitachi Ltd | 強誘電体薄膜の製造方法 |
KR0165484B1 (ko) * | 1995-11-28 | 1999-02-01 | 김광호 | 탄탈륨산화막 증착 형성방법 및 그 장치 |
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US5780886A (en) | 1996-05-30 | 1998-07-14 | Oki Electric Industry Co., Ltd. | Non-volatile semiconductor memory cell and method for production thereof |
US5719417A (en) | 1996-11-27 | 1998-02-17 | Advanced Technology Materials, Inc. | Ferroelectric integrated circuit structure |
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