TW408391B - Etching method for dual layer thin film - Google Patents

Etching method for dual layer thin film Download PDF

Info

Publication number
TW408391B
TW408391B TW88103704A TW88103704A TW408391B TW 408391 B TW408391 B TW 408391B TW 88103704 A TW88103704 A TW 88103704A TW 88103704 A TW88103704 A TW 88103704A TW 408391 B TW408391 B TW 408391B
Authority
TW
Taiwan
Prior art keywords
etching
layer
double
patent application
period
Prior art date
Application number
TW88103704A
Other languages
Chinese (zh)
Inventor
Richard Lai
Joseph Wang
Wuming Chang
Ya-Chi Chang
Original Assignee
Mosel Vitelic Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mosel Vitelic Inc filed Critical Mosel Vitelic Inc
Priority to TW88103704A priority Critical patent/TW408391B/en
Application granted granted Critical
Publication of TW408391B publication Critical patent/TW408391B/en

Links

Landscapes

  • Drying Of Semiconductors (AREA)

Abstract

This invention relates to a method for etching dual layer thin film, said dual layer thin film is composed by a poly-silicon and a silicon oxide, said method comprises the following steps: use a mask to define a pattern on said dual layer thin film, then send it into one etcher; adjust the process recipe of said etcher to a first status, to proceed the etching of said poly-silicon uncovered by said mask; and adjust the process recipe of said etcher to a second status, to proceed the etching of the exposed said poly-silicon.

Description

五、發明說明(1) 408391 發明領域 本案係為一種雙層薄膜之蝕刻方法,尤指應用於由一多晶 矽層與一氧化矽層所構成之該雙層薄膜之蝕刻方法。 發明背景 在半導體元件之結構中,如第一圖(a)所示之矽基板1〇 上’由多晶石夕層ll(p〇lySilicon)與氧化石夕層12(〇xide)所 構成之雙層薄膜(Bi-layei* film)係經常出現,而當吾人 欲於該雙層薄膜(Bi-layer film)上進行一接觸窗姓刻 (contact etching) ’以完成一接觸窗至該矽基板1〇時, 通常係於該多晶矽層ll(p〇lysiHcon)上成長一光阻層13 並定義圖案後(如第一圖(b)所示)’再送入一多晶矽屠蝕 刻機台(Poly si 1 ic〇n etcher )將未被光阻覆蓋之多晶矽爸 去(如第一圖(c)所示),完成後取出再送入另一氧化矽層 蝕刻機台(〇xide etcher)將露出之氧化矽蝕去,進而完治 該接觸窗構造14(如第一圖(d)所示)。 去進而凡片 為上述接觸窗蝕刻過程中,個別於多晶矽層蝕 i數i、,化矽層蝕刻機台進行蝕刻之製程變因(recipe〕 刻Ϊ由ί:由上述分別由兩個㈣機台來完成接觸窗勒 機台、自多ί工操作來完成將晶片送入多晶矽層蝕刻 台 '以及ί:: 刻機台取出、送入氧化矽層蝕刻機 自氧化矽層蝕刻機台取出之動#,因此頗為耗費V. Description of the Invention (1) 408391 Field of the Invention The present invention relates to an etching method of a double-layer thin film, and particularly to an etching method of the double-layer thin film composed of a polycrystalline silicon layer and a silicon oxide layer. BACKGROUND OF THE INVENTION In the structure of a semiconductor device, as shown in the first figure (a), a silicon substrate 10 ′ is composed of a polycrystalline silicon layer 11 (polysilicon) and an oxidized silicon layer 12 (〇xide). Bi-layei * film often appears, and when we want to perform a contact etching on the bi-layer film to complete a contact window to the silicon substrate At 10 o'clock, a photoresist layer 13 is usually grown on the polycrystalline silicon layer 11 (polysilicon) and a pattern is defined (as shown in the first figure (b)). Then, it is sent to a polycrystalline silicon etching machine (Poly si 1 ic〇n etcher) will remove the polycrystalline silicon that is not covered by the photoresist (as shown in the first picture (c)), and then take it out and send it to another silicon oxide layer etching machine (〇xide etcher) to expose the exposed oxide The silicon is etched away to complete the contact window structure 14 (as shown in the first figure (d)). In addition, in the process of etching the contact window described above, the process variation factor (etching) of the polycrystalline silicon layer etching machine and the silicon layer etching machine is etched by: from the above by the two machines To complete the contact window machine, and to complete the process of feeding the wafer into the polycrystalline silicon layer etching table 'and ί :: Take out the engraving machine table, send it to the silicon oxide layer etching machine and take it out from the silicon oxide layer etching machine. #

五、發明說明(2) ' * ' 人工與操作時間,而且亦由於人工之誤動作而出錯,故如 何改善上述習用技術之缺失,係為發展本案之一主要目- 的。 , 多晶矽層蝕刻機台 氧化矽層 触刻機台 製程變因 穩定時段 触刻時段 穩定時段 蝕刻時段 Pressure(mTorr) 300至500 300至500 200至400 200至400 RF Power (W) Top 0 150至300 0 750至950 RF Power(W) Bottom 0 0 0 0 Gap (cm) 0.7 至 1.2 0.7 至 1,2 0.8 至 1.4 0.8 至 1.4 Gas flow (seem) Cl2 50 至 70 50 至 70 He 120至160 120至160 Ar 150至170 150至300 CHF3 20 至 25 2 0 至25 CF4 10 至 20 10 至 20 發明概述 本案係為一種雙層薄膜之蝕刻方法,該雙層薄膜係由 一多晶矽層與一氧化矽層所構成,該方法包含下列步驟: 將該雙層薄膜上以一罩幕(mask)定義出一圖案後送入一钱 刻機台;調整該餘刻機台之製程變因(recipe)至一第一狀 態’用以進行未被該罩幕覆蓋之該多晶矽層之蝕刻;以及V. Description of the invention (2) '*' Labor and operation time, but also errors due to manual errors, so how to improve the lack of conventional techniques is one of the main objectives of the development of this case. , Polycrystalline silicon layer etching machine, silicon oxide layer touching machine, process variation, stable period, touching period, stable period, etching period, Pressure (mTorr) 300 to 500 300 to 500 200 to 400 200 to 400 RF Power (W) Top 0 150 to 300 0 750 to 950 RF Power (W) Bottom 0 0 0 0 Gap (cm) 0.7 to 1.2 0.7 to 1,2 0.8 to 1.4 0.8 to 1.4 Gas flow (seem) Cl2 50 to 70 50 to 70 He 120 to 160 120 To 160 Ar 150 to 170 150 to 300 CHF3 20 to 25 2 0 to 25 CF4 10 to 20 10 to 20 SUMMARY OF THE INVENTION The present invention is an etching method of a double-layered thin film composed of a polycrystalline silicon layer and silicon monoxide. The method includes the following steps: defining a pattern on the double-layer film with a mask, and sending the pattern to a money engraving machine; adjusting the recipe of the remaining engraving machine to (recipe) to A first state 'for etching the polycrystalline silicon layer not covered by the mask; and

_iMasj----- 五、發明說明(3) 調整該蝕刻機台之製程變因(recipe)至一第二狀態’用以 進行露出之該氧化矽層之蝕刻。 根據上述構想,雙層薄膜之蝕刻方法中該第—狀態之 製程變因(recipe)係包含有兩時段之數據,其中該第一時 段之數據係用以使該蝕刻機台達到穩定,而該第二時段之 數據係用以使該蝕刻機台對該多晶矽層進行蝕刻。 根據上述構想,雙層薄膜之蝕刻方法中該第二狀態之 製程變因(recipe)係包含有兩時段之數據,其_該第一時 段之數據係用以使該蝕刻機台達到穩定,而該第二時段之 數據係用以使該蝕刻機台對該氧化矽層進行蝕刻。 根據上述構想,雙層薄膜之蝕刻方法中該罩幕(mask) 係一光阻層。 根據上述構想,雙層薄膜之蝕刻方法中該多晶矽層之 厚度約為2 0 0 0埃。 簡單圖式說明 本案得藉由下列圖式及詳細說明,俾得一更深入之了 解: 第一圖(a)(b)(c)(d) ··其係習用技術用以於該雙層薄膜 (Bi-layer film)上進行一接觸窗蝕刻之示意圖。 第二圖(a) (b)(c):其係本案較佳實施例技術於該雙層薄 膜(Bi-layer film)上進行一接觸窗蝕刻之示意圖。_iMasj ----- 5. Description of the invention (3) Adjust the recipe of the etching machine to a second state 'for etching the exposed silicon oxide layer. According to the above-mentioned concept, in the etching method of the first state of the double-layer film, the recipe of the first state includes two periods of data, wherein the data of the first period is used to make the etching machine stable, and the The data in the second period is used for the etching machine to etch the polycrystalline silicon layer. According to the above concept, the recipe of the second state in the etching method of the double-layer thin film includes two periods of data, and the data of the first period is used to make the etching machine stable, and The data in the second period is used for the etching machine to etch the silicon oxide layer. According to the above conception, the mask in the etching method of the double-layer film is a photoresist layer. According to the above idea, the thickness of the polycrystalline silicon layer in the etching method of the double-layer thin film is about 2000 angstroms. Simple illustration of the case The following drawings and detailed descriptions can be used to gain a deeper understanding: The first picture (a) (b) (c) (d) ·· It is a conventional technology used in the double layer A schematic diagram of performing a contact window etching on a thin film (Bi-layer film). The second figure (a) (b) (c): it is a schematic diagram of a contact window etching on the bi-layer film of the preferred embodiment of the technology.

^08391^ 08391

五、發明說明(4) 本案圖式中所包 矽基板1 0 氧化矽層1 2 接觸窗構造14 多晶妙層2 1 光阻層2 3 含之各元件列示如下: 多晶梦層1 1 光阻層1 3 矽基板20 氧化矽層2 2 接觸窗構造24 較佳實施例說明 請參見第二圖(a),其係矽基板2〇上由多晶矽層 21(p〇Iysilicon)與氧化梦層22(oxide)所構成之雙層薄膜 (Bi-layer filoO,而當吾人欲於此雙層薄膜(Bi_layef film)上進行一接觸窗蝕刻(contact etching),用以完成 一接觸窗至該矽基板20時’通常於該多晶矽層 21(p〇lysilic〇n)上成長一光阻層23為罩幕(mask)並定義 圖案後進行蝕刻(如第二圖(b)所示)。 而由於雙層薄膜(Bi-layer film)中之多晶石夕層 21(p〇lysilicon)結構厚度大約僅有2〇〇〇埃,因此蝕刻率 (etching rate)對於此蝕刻時程之影響不大,且原用以蝕 刻多晶矽層之钱刻機台與蝕刻氧化矽層之蝕刻機台間,僅 射頻功率(RF Power)之規格略有差異,故為能使此類蝕刻 製程之機台單純化’減少晶片之傳輸次數,進而增加產能 且避免人員之誤操作(mis op e rati on),本案係揭露之一較 佳實施例方法係發展出一於同一機台内完成該雙層薄膜 408391 五、發明說明(5) (Bi-layer film)之餘刻方法,請參見第二圖(c)所示,本 案係如圖所示將該定義出圖案之雙層薄膜結構送入原用以 蝕刻氧化矽之蝕刻機台中,然後調整該蝕刻機台之製程變 因(recipe)至一第一狀態(如下表二所示之數據),用以進 行未被該光阻覆蓋之該多晶矽層2 1之蝕刻,而當多晶矽層 2 1蝕刻完成後,不必移出該蝕刻機台而繼續調整該蝕刻機 台之製程變因(recipe)至一第二狀態(如下表二所示之數 據),用以進行露出之該氧化矽層22之蝕刻,進而完成該 接觸窗構造24。 如此一來,本案係將上述雙層薄膜(Bi-layer film) 之蝕刻製程的機台單純化,減少晶片之傳輸次數,進而增 加產能且避免人員之誤操作(misoperation),有效解決習 用技術之缺失,達成發展本案之主要目的。 創作本案得由熟習此技藝之人士任施匠思而為諸般修飾, 然皆不脫如附申請專利範圍所欲保護者。V. Description of the invention (4) The silicon substrate included in the plan of this case 1 0 Silicon oxide layer 1 2 Contact window structure 14 Polycrystalline layer 2 1 Photoresistive layer 2 3 The components included are listed below: Polycrystalline dream layer 1 1 Photoresist layer 1 3 Silicon substrate 20 Silicon oxide layer 2 2 Contact window structure 24 For a description of the preferred embodiment, please refer to the second figure (a). The silicon substrate 20 is composed of a polycrystalline silicon layer 21 (piosilicon) and an oxide. The bi-layer film (Bi-layer filoO) composed of dream layer 22 (oxide), and when we want to perform a contact etching on this bi-layer film (Bi_layef film), to complete a contact window to the When the silicon substrate 20 is used, a photoresist layer 23 is usually grown on the polycrystalline silicon layer 21 (polysilicon) as a mask and a pattern is defined and then etched (as shown in the second figure (b)). Because the thickness of the polysilicon layer 21 in the bi-layer film is only about 2000 angstroms, the etching rate has little effect on this etching duration. In addition, between the money engraving machine used to etch the polycrystalline silicon layer and the etching machine used to etch the silicon oxide layer, only RF power There is a slight difference, so in order to make the machine of this type of etching process simplify and reduce the number of wafer transfers, thereby increasing the production capacity and avoiding mis op e rati on, this case is a preferred embodiment disclosed The method is to develop a method to complete the double-layer film 408391 in the same machine. 5. The remaining method of the description of the invention (5) (Bi-layer film), please refer to the second figure (c). This case is shown in the figure. It is shown that the double-layered thin film structure with the defined pattern is sent to the original etching machine for etching silicon oxide, and then the recipe of the etching machine is adjusted to a first state (data shown in Table 2 below) ) For etching the polycrystalline silicon layer 21 not covered by the photoresist, and after the polycrystalline silicon layer 21 is etched, it is not necessary to remove the etching machine and continue to adjust the recipe of the etching machine. In a second state (data shown in Table 2 below), the exposed silicon oxide layer 22 is etched to complete the contact window structure 24. In this case, the above-mentioned double-layer film (Bi- layer film) The machine is simplistic, reducing the number of wafer transfers, thereby increasing production capacity and avoiding misoperation of personnel, effectively solving the lack of conventional technology, and achieving the main purpose of developing this case. The person who is familiar with this technique can create this case. But for all kinds of modifications, they are not inferior to those who want to protect the scope of patent application.

- 五、發明說明(6) 表二 第一狀態 第二狀態 製程變因 穩定時段 蝕刻時段 穩定時段 蝕刻時段 Pressure (m Torr) 300 至 400 較佳為350 300 至 400 較佳為3 50 200 至 400 較佳為300 200 至 400 較佳為300 RF Power (W) Top 0 200 至 300 較佳為250 0 750 至 950 較佳為850 RF Power(W) Bottom 0 0 0 0 Gap (cm) 0-8至1,4較 佳為1.1 0.8至1.4較 佳為1.1 0.8至1.4較 佳為1.1 0.8至1.4較 佳為1.1 Gas flow (seem) SF6 40至50較 佳為4 5 40至50較 隹為45 Ar 300 至 500 較佳為400 300 至 500 較佳為400 150 至 170 較佳為160 150 至 170 較佳為160 CHF3 40至50較 佳為45 40至50較 佳為4 5 20至25較 佳為22 20至25較 佳為22 CF4 0 0 10至20較 佳為15 10至20較 佳為15 mm-V. Explanation of the invention (6) Table 2 First state Second state Process variation Stable period Etching period Stable period Etching period Pressure (m Torr) 300 to 400 preferably 350 300 to 400 preferably 3 50 200 to 400 300 300 to 400, preferably 300 RF Power (W) Top 0 200 to 300, preferably 250 0 750 to 950, and 850 RF Power (W) Bottom 0 0 0 0 Gap (cm) 0-8 To 1,4 is preferably 1.1 0.8 to 1.4 is preferably 1.1 0.8 to 1.4 is preferably 1.1 0.8 to 1.4 is preferably 1.1 Gas flow (seem) SF6 40 to 50 is preferably 4 5 40 to 50 is more than 45 Ar 300 to 500 preferably 400 300 to 500 preferably 400 150 to 170 preferably 160 150 to 170 preferably 160 CHF 3 40 to 50 preferably 45 40 to 50 preferably 4 5 20 to 25 preferably 22 20 to 25, preferably 22 CF4 0 0 10 to 20, preferably 15 10 to 20, preferably 15 mm

Claims (1)

___408391 六、申請專利範ΐ" ' ' ^二ί雙層薄膜之蝕刻方法,該雙層薄膜係由一多晶矽層 化發層所構成,該方法包含下列步驟: 將該雙層薄膜上以一罩幕(mask)定義出一圖案後送入 一蝕刻機台; 、調整該蚀刻機台之製程變因(recipe)至一第一狀態, 進行未被該罩幕覆蓋之該多晶石夕層之银刻;以及 調整該蝕刻機台之製程變因(recipe)至一第二狀態, 以進行露出之該氧化矽層之蝕刻。 2中如申請專利範圍第1項所述之雙層薄膜之蝕刻方法,其 該第一狀態之製程變因(recipe)係包含有兩時段之數 ^ 其中該第一時段之數據係用以使該蝕刻機台達到穩 疋’而該第二時段之數據係用以使該蝕刻機台對該多晶矽 層進行蝕刻。 3,如申請專利範圍第2項所述之雙層薄膜之蝕刻方法’其 中該第一狀態之製程變因(reCipe)係為下表所列: 第一狀態 製程變因 穩定時段 触刻時段 Pressure (m Torr) 300 至 400 較佳為350 300 至 400 較佳為350 RF Power (W) Top 0 200 至 300 較佳為250___408391 VI. Patent application method "'^ 二 ί Double-layer film etching method, the double-layer film is composed of a polycrystalline silicon layer hair layer, the method includes the following steps: the double-layer film is covered with a mask The mask defines a pattern and sends it to an etching machine; adjusts the recipe of the etching machine to a first state, and performs the polycrystalline stone layer that is not covered by the mask Silver engraving; and adjusting a recipe of the etching machine to a second state to perform etching of the exposed silicon oxide layer. The method for etching a double-layer thin film as described in item 1 of the scope of patent application in 2, wherein the recipe of the first state includes a number of two periods ^ wherein the data of the first period is used to make The etch machine is stable, and the data in the second period is used to make the etch machine etch the polycrystalline silicon layer. 3. The etching method of the double-layer thin film as described in item 2 of the scope of the patent application, wherein the process change factor (reCipe) of the first state is listed in the following table: The first state process change factor is the stable period and the etching period is Pressure. (m Torr) 300 to 400 preferably 350 300 to 400 preferably 350 RF Power (W) Top 0 200 to 300 preferably 250 第10頁 六、申請專利範圍 408391 RF Power(W) Bottom 0 0 Gap (cm) 0_8至1·4較 佳為1.1 0.8至1.4較 佳為1.1 Gas flow (seem) SF6 40至50較 佳為45 40至50較 佳為45 Ar 300 至 500 較佳為400 300 至 500 較佳為400 CHF3 40至50較 佳為4 5 40至50較 佳為45 CF4 0 0 4.如申請專利範圍第1項所述之雙層薄膜之蝕刻方法,其 中該第二狀態之製程變因(recipe)係包含有兩時段之數 據,其中該第一時段之數據係用以使該蝕刻機台達到穩 定,而該第二時段之數據係用以使該蝕刻機台對該氧化矽 層進行姓刻。Page 10 VI. Application patent range 408391 RF Power (W) Bottom 0 0 Gap (cm) 0_8 to 1.4 is preferred 1.1 0.8 to 1.4 is preferred 1.1 Gas flow (seem) SF6 40 to 50 is preferred 45 40 to 50, preferably 45 Ar 300 to 500, preferably 400 300 to 500, preferably 400 CHF 3 40 to 50, preferably 4 5 40 to 50, and preferably 45 CF4 0 0 4. If the scope of patent application is the first item In the method for etching a double-layer film, the process recipe of the second state includes two periods of data, wherein the data of the first period is used to stabilize the etching machine, and the The data of the second period is used for the etching machine to engrav the silicon oxide layer. _4Q8391_ 六、申請專利範圍 5.如申請專利範圍第4項所述之雙層薄膜之蝕刻方法,其 中該第二狀態之製程變因(recipe)係為下表所列: 第二狀態 製程變因 穩定時段 蝕刻時段 Pressure(m Torr) 200 至 400 較佳為300 200 至 400 較佳為300 RF Power (W) Top 0 750 至 950 較佳為850 RF Power(W) Bottom 0 0 Gap (cm) 0.8至1‘4較 佳為1.1 0,8至1.4較 佳為1.1 Gas flow (seem) SF6 Ar 150 至 170 較佳為160 150 至 170 較佳為160 CHF3 20至25較 佳為22 20至25較 佳為22 CF4 10至20較 佳為15 10至20較 佳為15_4Q8391_ VI. Scope of patent application 5. The etching method of the double-layer thin film as described in item 4 of the scope of patent application, wherein the recipe of the second state is listed in the following table: Process of the second state Steady Period Etching Pressure (m Torr) 200 to 400, preferably 300 200 to 400, preferably 300 RF Power (W) Top 0 750 to 950, preferably 850 RF Power (W) Bottom 0 0 Gap (cm) 0.8 1 to 4 is preferably 1.10, 8 to 1.4 is preferably 1.1 Gas flow (seem) SF6 Ar 150 to 170 is preferably 160 150 to 170 is preferably 160 CHF3 20 to 25 is preferably 22 20 to 25 Preferably 22 CF4 10 to 20, preferably 15 10 to 20, preferably 15 第12頁 408391 六、申請專利範圍 6. 如申請專利範圍第1項所述之雙層薄膜之蝕刻方法,其 中該罩幕(mask)係一光阻層。 7. 如申請專利範圍第1項所述之雙層薄膜之蝕刻方法,其, 中該多晶矽層之厚度約為2 0 0 0埃。Page 12 408391 6. Scope of patent application 6. The etching method of the double-layer film as described in item 1 of the scope of patent application, wherein the mask is a photoresist layer. 7. The method for etching a double-layer thin film according to item 1 of the scope of patent application, wherein the thickness of the polycrystalline silicon layer is about 2000 angstroms. 第13頁Page 13
TW88103704A 1999-03-10 1999-03-10 Etching method for dual layer thin film TW408391B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW88103704A TW408391B (en) 1999-03-10 1999-03-10 Etching method for dual layer thin film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW88103704A TW408391B (en) 1999-03-10 1999-03-10 Etching method for dual layer thin film

Publications (1)

Publication Number Publication Date
TW408391B true TW408391B (en) 2000-10-11

Family

ID=21639924

Family Applications (1)

Application Number Title Priority Date Filing Date
TW88103704A TW408391B (en) 1999-03-10 1999-03-10 Etching method for dual layer thin film

Country Status (1)

Country Link
TW (1) TW408391B (en)

Similar Documents

Publication Publication Date Title
TWI220266B (en) Semiconductor device and method for forming transistors having a reduced pitch
WO2019041858A1 (en) Etching method, method for manufacturing thin film transistor, processing equipment, and display device
JP2005197640A (en) Flash memory element manufacturing method
KR100714287B1 (en) Method for forming a pattern of semiconductor device
TW408391B (en) Etching method for dual layer thin film
US5902133A (en) Method of forming a narrow polysilicon gate with i-line lithography
JP2001230233A (en) Method for manufacturing semiconductor device
JP2907314B2 (en) Method for manufacturing semiconductor device
JP3080400B2 (en) Semiconductor device
KR960012630B1 (en) Fine pattern forming method of semiconductor device
JPH07321091A (en) Etching and wiring forming method
JP2002141328A (en) Semiconductor device and its manufacturing method
JP2008159717A (en) Etching method
JPH03125427A (en) Manufacture of semiconductor device
KR100312973B1 (en) Method for forming metal electrode in memory device
JPH09181077A (en) Semiconductor device and manufacturing method thereof
JP2001237420A (en) Method of forming gate electrode of semiconductor device
JPH11354523A (en) Manufacture of semiconductor device
JPS63257248A (en) Manufacture of semiconductor device
JP2004235297A (en) Method of manufacturing semiconductor device
JPH0338034A (en) Manufacture of semiconductor device
JPH01244636A (en) Manufacture of semiconductor device
KR20000045433A (en) Method for fabricating gate electrode
KR20020083279A (en) Method for Forming pattern in Semiconductor Device
JPH0479321A (en) Production of semiconductor device

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees