Λ' [Γ 五、發明説明（/ ) 發明領域： 請先閲讀背而之注&4Ϊ,項#填寫本ΤΓ 本發明係關於一種積體電路中金屬結構間隔離的製作 方法，特別是關於一種在積體電路之動態隨機存取記憶體 (DRAM)製程中，位元線(bit line)與電容節點(capacitance node)間隔離的製作方法。 發明背景： T -5 坡 典型的堆疊式動態隨機存取記憶體是在矽半導體晶圓 上(Silicon Semiconductor Wafer)製造一個金氧半場效電 晶體（Metal Oxide Semiconductor Field Effect Transistor ; MOSFET)與電容器(Capacitor)，並利用所述場 效電晶體的汲極（Drain)來連接電容器的電荷儲存電極 (Storage Node)以形成動態隨機存取記憶體的記憶元 (Memory Cell)。數目龐大的記憶元聚集成爲記憶元陣列 (Cell Array)。另一方面，在記憶元陣列的附近則有其它電 路圍繞，例如感測放大器(Sense Amplifier)等電路，這些 外部電路，稱爲週邊電路區域(Peripheral Circuit)。 經淹部中央標準局员工消费合作社印製 最近幾年來，動態隨機存取記憶體的集積密度(Packing Density)快速增加，目前已進入記憶元尺寸1.5平方微米 之六仟四佰萬位元的量產，日本半導體公司NEC更在1995 年宣稱已經有十億位元動態隨機存取記憶體(1GB DRAM)的原 型樣品問世(Prototype)，因此，自動對準技術於高集積密 度製程就更加重要，而光罩對不準所造成之問題的解決，亦 是高集積密度製程中重要的課題之一。 請參考圖一之習知DRAM製程中製作位元線與電容節點 本紙張尺度適用中國國家標準（CNS ) (210x29' i ΙΓ 五、發明説明（A ) 間隔離之製程剖面圖’其中以位元線製作中發生光罩對不準 誤差爲例。於圖一 A中顯示一具有MOS電晶體、第一氧化層 20、後續電容製作所需之複晶矽接觸墊81、第二氧化層30、 及複晶矽位元線結構62的基板1〇，其中MOS電晶體包含源 極(未標示出）、汲極D、及閘極結構(包括閘氧化層9〇、複 晶矽層61、氮化矽側壁71及氮化矽覆蓋層72)，而複晶矽 接觸墊81與汲極D相接觸。 接著，請參考圖一 B，沉積第三氧化層40，再定義出 後續電容製作所需之電容節點接觸窗的光阻圖案50 ;接著， 進行蝕刻移除未被光阻50覆蓋之第三氧化層40及第二氧化 層30以開啓接觸窗。 經濟部中央標糸局負工消费合作社印裝 (請A閱讀背面之：'--念-:項再填巧太頁 丁 、-0 線 再接著，請參閱圖一 C，於接觸窗側壁形成具有隔離導 電層功用之氮化砍墊層(liner)73，其製作步驟是先進行氮 化矽沉積，再進行氮化矽垂直均向性蝕刻。由於在高集積密 度製程中，常發生光罩對不準現象，位元線位置的偏差使氮 化矽墊層無法完全覆蓋住位元線62(圖中A處顯示部份複晶 矽位元線之裸露）。因此，在圖一 D中，當電容節點接觸窗 中之複晶矽插塞(poly plug)82形成後，A處將發生位元線 與電容節點短路之漏電情形，且複晶矽插塞82與接觸墊81 的接觸面積將減少。 因此，爲提高DRAM產品品質及良率’解決上述之問題 爲本案發明之重要目的。 發明之概述： 本發明之主要目的是提供一種積體電路中金屬結構間Λ '[Γ V. Description of the invention (/) Field of the invention: Please read the back note & 4Ϊ, item # to fill out this TΓ The present invention relates to a method for manufacturing isolation between metal structures in integrated circuits, especially about A manufacturing method for isolation between a bit line and a capacitor node in a dynamic random access memory (DRAM) process of an integrated circuit. Background of the Invention: The typical stacked dynamic random access memory of T-5 slope is to manufacture a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and a capacitor (Silicon Semiconductor Wafer) on a silicon semiconductor wafer (Silicon Semiconductor Wafer). Capacitor), and the drain of the field effect transistor is used to connect a charge storage electrode (Storage Node) of a capacitor to form a memory cell of a dynamic random access memory. A large number of memory cells are aggregated into a cell array. On the other hand, there are other circuits around the memory cell array, such as circuits such as sense amplifiers. These external circuits are called peripheral circuits. Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Flooding in recent years, the packing density of dynamic random access memory (Packing Density) has increased rapidly, and has now entered the memory cell size of 1.5 square micrometers, which is 64.4 million bits. Japan ’s semiconductor company NEC announced in 1995 that a prototype of a billion-bit dynamic random-access memory (1GB DRAM) prototype was available. Therefore, auto-alignment technology is even more important in high-density-density processes. The photomask's solution to the problems caused by inaccuracy is also one of the important issues in the high-density process. Please refer to Figure 1 for the fabrication of bit lines and capacitor nodes in the conventional DRAM manufacturing process. The paper dimensions are applicable to the Chinese National Standard (CNS) (210x29 'i ΙΓ) 5. Sectional view of the process of isolation between the invention description (A)' As an example, a mask misalignment error occurs during line production. In Figure 1A, a MOS transistor, a first oxide layer 20, and a polycrystalline silicon contact pad 81, a second oxide layer 30, And the substrate 10 of the polycrystalline silicon bit line structure 62, wherein the MOS transistor includes a source (not shown), a drain D, and a gate structure (including a gate oxide layer 90, a polycrystalline silicon layer 61, nitrogen The silicon sidewall 71 and the silicon nitride cover layer 72), and the polycrystalline silicon contact pad 81 is in contact with the drain D. Next, please refer to FIG. 1B, deposit a third oxide layer 40, and define the subsequent capacitor manufacturing requirements The photoresist pattern 50 of the contact window of the capacitive node; then, etching is performed to remove the third oxide layer 40 and the second oxide layer 30 that are not covered by the photoresist 50 to open the contact window. Printing (please read A on the back: '--Read-:' and then fill in the page too, 0 Next, referring to FIG. 1C, a nitride liner 73 having an isolation conductive layer function is formed on the sidewall of the contact window. The manufacturing step is to first deposit silicon nitride, and then perform vertical vertical alignment of the silicon nitride. In high-density process, mask misalignment often occurs. The deviation of the bit line position prevents the silicon nitride pad layer from completely covering the bit line 62. (Part A is shown in the figure at A The silicon bit line is exposed). Therefore, in Figure 1D, after the polycrystalline silicon plug 82 in the contact window of the capacitor node is formed, a short circuit of the bit line and the capacitor node will occur at A. The contact area between the polycrystalline silicon plug 82 and the contact pad 81 will be reduced. Therefore, in order to improve the quality and yield of DRAM products, it is an important object of the present invention to solve the above problems. Summary of the invention: The main object of the present invention is to Provide a metal structure in integrated circuit
夂甙張尺度適別士國國1： :、.:S 1 五、發明説明（；？） 隔離的製作方法，以防止金屬結構間之短路現象。 本發明的次要目的是提供一種積體電路之DRAM製程 中’位元線與電容節點間隔離的製作方法，以防止位元線與 電容節點間之短路現象。 本發明是利用下列技術手段來達到上述之各項目的：首 先，提供一半導體基板，所述半導體基板上包含已製作完成 之MOS電晶體、第一介電層、後續電容製作所需之接觸墊 (contact pad)、及第二介電層；接著，形成一具有雙層結 構之覆蓋終止層(cap stopping layer)於所述第二介電層之 上；然後，以微影蝕刻技術形成複晶矽位元線；再接著，形 成第三介電層，並利用光阻於所述第三介電層上定義出後續 電容製作所需之電容節點接觸窗的光阻圖案；隨後，進行蝕 刻，依序移除未被光阻覆蓋之所述第三介電層及所述覆蓋終 止層的上層、未被光阻覆蓋之複晶矽位元線、未被光阻覆蓋 之所述覆蓋終止層的下層及第二介電層，而完成電容節點接 觸窗的開啓；移除光阻後，於電容節點接觸窗的側壁形成具 有隔離導電層功用之墊層(liner);最後，於電容節點接觸 窗中形成複晶砂插塞(poly plug)。 圖式簡要說明： 圖一 A〜D爲習知技藝之DRAM製程中，位元線與電容 節點間隔離之製程剖面圖。 圖二A〜D爲本發明實施例之DRAM製程中，位元線與 電容節點間隔離之製程剖面圖。 圖號說明： {讀先閱讀背而之as事項得填寫本Η 表-- 丁 、\>·5 經濟部中央標汍局Μ工消费合作社印製 本紙張尺度適用中國國家標隼（CNS ) Λ4ΑΊ ( ΙΓ 五、發明説明（4) ΙΓ 10- 基板 20- 第一氧化層 30 - 第二氧化層 40- 第三氧化層 50- 光阻 61- 第一複晶矽層 62- 第二複晶矽層 71- 第一氮化矽側壁 72- 氮化矽覆蓋層 73- 第二氮化矽側壁 81- 複晶矽接觸墊 82- 複晶矽插塞 90- 閛氧化層 100- 基板 200-第一氧化層 210-閘氧化層 300-第二氧化層 410-終止層之矽化物層 420-終止層之氧化物層 500-第三氧化層 600-光阻 710- 第一複晶砍層 720-第二複晶矽層 810-第一氮化矽側壁 820-氮化矽覆蓋層 830-第二氮化矽側壁 910-複晶矽接觸墊 .920-複晶砂插塞 Α- 裸露之位元線 D- 汲極 (請先閲讀背而之.';±念事項再填"本頁 ^、τ 經濟部中央標浓局Η工消f合作社印裝 發明詳細說明： 以下利用積體電路DRAM製程中之位元線與電容節點間 隔離的製作方法爲具體實施例，來詳細說明本發明。首先， 請參閱圖二A，提供一半導體基板1QG，所述半導體基板1〇〇 上包含已製作完成之MOS電晶體、第一氧化層20G、後續電 容製作所需之接觸墊(contact pad)91G、及第二氧化層 300，其中M0S電晶體包含源極(未標示出）、汲極D、及閘 極結構(包括閘氧化層210、複晶矽層710、氮化矽側壁81〇 及氮化矽覆蓋層820)，而複晶矽接觸墊910與汲極D相接 本紙張尺度適用中國國家標準（CN’S ) 規诒：210,x2W:Mi.· ' A" ΙΓ 五、發明説明（/) 觸；另外，所述第一氧化層200可爲四乙氧基矽烷(TEOS)， 而第二氧化層3G0可爲硼磷矽玻璃，以增進平坦化的效果。 接下來的步驟爲本發明之重點所在，且爲習知技藝中所 沒有的。請再次參閱圖二A，於晶片表面沉積一覆蓋終止層 (cap stopping layer)，所述覆蓋終止層具有雙層結構，其 下層410可爲氮化矽層或氧化氮化矽(oxynitride)層，厚度 係介於50埃到200埃之間，而上層420爲氧化層，其厚度 係介於50埃到150埃之間。然後，以習用微影蝕刻技術形 成複晶矽位元線(bit 1 ine)72G於所述覆蓋終止層上。 接著，請參閲圖二B，形成第三氧化層50Q，並利用光 阻於所述第三介電層500上定義出後續電容製作所需之電容 節點接觸窗的光阻圖案600 ;隨後進行蝕刻，以移除未被光 阻覆蓋之所述第三氧化層500及所述覆蓋終止層的上層 420(亦即氧化層），而此蝕刻將停止於覆蓋終止層的下層 410(即氮化物）。此時，因光罩對不準誤差，將可能使部份 位元線720裸露出來。 因此，本發明的下一步驟就是進行複晶矽垂直均向性乾 蝕刻，將未被光阻覆蓋而裸露出的複晶矽位元線720移除， 如圖二C中所示。接著，請參考圖二D，再度進行蝕刻，以 穿透移除未被光阻覆蓋之所述覆蓋終止層的下層410，再接 著蝕刻第二氧化層300，而完成電容節點接觸窗的開啓。 請再參閱圖二D，移除光阻後’於電容節點接觸窗的側 壁形成具有隔離導電層功用之墊層(1 iner)830，其中步驟包 括先沉積一層氮化矽，再進行氮化矽垂直均向性乾蝕刻，即 {請先閱讀背面之注S事磧再填·:5¾本頁 衣. 訂 經消部中央標嗥局貞工消费合作社印製 本纸張尺度適用中國國家標準（CNS ) Λ4規丨δ :The scale of glucoside is suitable for the country of Bristol 1: 1:,.: S 1 V. Description of the invention (;?) Isolation production method to prevent short circuit between metal structures. A secondary object of the present invention is to provide a manufacturing method of isolation between a bit line and a capacitor node in a DRAM manufacturing process of an integrated circuit, so as to prevent a short circuit between the bit line and the capacitor node. The present invention uses the following technical means to achieve the above-mentioned objects: First, a semiconductor substrate is provided. The semiconductor substrate includes a completed MOS transistor, a first dielectric layer, and contact pads required for subsequent capacitor fabrication. (contact pad), and a second dielectric layer; then, a cap stopping layer having a double-layer structure is formed on the second dielectric layer; and then, a polycrystal is formed by a lithographic etching technique A silicon bit line; then, a third dielectric layer is formed, and a photoresist pattern on the third dielectric layer is used to define a photoresist pattern of a capacitor node contact window required for subsequent capacitor production; subsequently, etching is performed, Sequentially remove the third dielectric layer not covered by photoresist and the upper layer of the cover termination layer, the polycrystalline silicon bit line not covered by photoresist, and the cover termination layer not covered by photoresist. The lower layer of the capacitor and the second dielectric layer are used to complete the opening of the contact window of the capacitor node. After removing the photoresist, a liner having the function of isolating the conductive layer is formed on the sidewall of the contact window of the capacitor node; finally, the capacitor node is contacted Window shape Sand plug polycrystalline (poly plug). Brief description of the drawings: Figures A ~ D are cross-sectional views of the process of isolating the bit lines from the capacitor nodes in the DRAM process of the conventional art. FIG. 2A to D are cross-sectional views of a process for isolating a bit line from a capacitor node in a DRAM process according to an embodiment of the present invention. Description of drawing number: {Read this first and then read the “as” matter to fill in this form-Ding, \ > · 5 Printed on the paper standard of China National Standards (CNS) Λ4ΑΊ (ΙΓ 5. Description of the invention (4) ΙΓ 10- substrate 20- first oxide layer 30-second oxide layer 40- third oxide layer 50- photoresist 61- first polycrystalline silicon layer 62- second polycrystalline Silicon layer 71- first silicon nitride sidewall 72- silicon nitride cover layer 73- second silicon nitride sidewall 81- polycrystalline silicon contact pad 82- polycrystalline silicon plug 90- hafnium oxide layer 100- substrate 200- An oxide layer 210-a gate oxide layer 300-a second oxide layer 410-a silicide layer of a termination layer 420-an oxide layer of a termination layer 500-a third oxide layer 600-a photoresist 710-a first polycrystalline layer 720- The second polycrystalline silicon layer 810-the first silicon nitride sidewall 820-the silicon nitride cover layer 830-the second silicon nitride sidewall 910-the polycrystalline silicon contact pad. 920-the polycrystalline sand plug A-the exposed bit Line D- Drain (please read the other side first. '; ± read the matter and then fill in this page ^, τ, the Ministry of Economic Affairs, Central Standards Bureau, the Ministry of Industry, Fong Cooperative Co., Ltd., printed invention detailed description: The manufacturing method of bit line and capacitor node isolation in the integrated circuit DRAM manufacturing process is a specific embodiment to explain the present invention in detail. First, referring to FIG. 2A, a semiconductor substrate 1QG is provided, and the semiconductor substrate 1 is provided. 〇It includes the completed MOS transistor, the first oxide layer 20G, the contact pad 91G required for subsequent capacitor production, and the second oxide layer 300. The MOS transistor includes a source (not shown) , Drain D, and gate structure (including gate oxide layer 210, polycrystalline silicon layer 710, silicon nitride sidewall 81, and silicon nitride cover layer 820), and the polycrystalline silicon contact pad 910 is connected to the drain D This paper scale applies Chinese National Standard (CN'S) regulations: 210, x2W: Mi. 'A " ΙΓ 5. Description of the invention (/); In addition, the first oxide layer 200 may be tetraethoxysilane ( TEOS), and the second oxide layer 3G0 may be borophosphosilicate glass to enhance the planarization effect. The next steps are the focus of the present invention and are not found in the conventional art. Please refer to FIG. 2A again , Depositing a capping stop layer on the wafer surface (cap stopping l ayer), the cover stop layer has a double-layer structure, and the lower layer 410 may be a silicon nitride layer or an oxynitride layer, and the thickness is between 50 angstroms and 200 angstroms, while the upper layer 420 is an oxide layer. Its thickness is between 50 Angstroms and 150 Angstroms. Then, a polycrystalline silicon bit line 72G is formed on the cover stop layer by a conventional lithography etching technique. Next, referring to FIG. 2B, a third oxide layer 50Q is formed, and a photoresist is used to define a photoresist pattern 600 of a capacitor node contact window required for subsequent capacitor production on the third dielectric layer 500; subsequently, Etching to remove the third oxide layer 500 and the upper layer 420 (ie, the oxide layer) that are not covered by the photoresist, and the etching will stop at the lower layer 410 (ie, the nitride) that covers the stop layer. ). At this time, due to the misalignment of the mask, part of the bit lines 720 may be exposed. Therefore, the next step of the present invention is to perform vertical isotropic dry etching of the polycrystalline silicon to remove the polycrystalline silicon bit lines 720 that are not exposed by the photoresist, as shown in FIG. 2C. Next, referring to FIG. 2D, etching is performed again to penetrate and remove the lower layer 410 of the cover stop layer not covered by the photoresist, and then the second oxide layer 300 is etched to complete the opening of the capacitor node contact window. Please refer to FIG. 2D again. After removing the photoresist, a spacer layer (1 iner) 830 having an isolation conductive layer function is formed on the sidewall of the contact window of the capacitor node. The steps include depositing a silicon nitride layer and then performing silicon nitride Vertical isotropic dry etching, that is, {please read the Note S on the back, and then fill in :: 5¾ page cover. Ordered by the Central Standards Bureau of the Ministry of Consumer Affairs, Zhengong Consumer Cooperative, this paper is printed in accordance with Chinese standards CNS) Λ4 gauge 丨 δ:
五、發明説明（) 可形成可完整遮蓋住位元線720的側壁的墊層結構830 ;最 後，沉積一層複晶矽層以填充該接觸窗，並附隨一複晶矽回 蝕步驟’以完成電容節點接觸窗中複晶矽插塞（poly plug)920的製作。 縱上所述’本發明利用一覆蓋終止層(SiN/oxide或 SiON/oxide)的製作，分兩階段開啓接觸窗，在兩階段蝕刻 之間處理可能裸露出的複晶矽位元線720，如此即可藉由氮 化矽墊層結構830，使該具導電功用的複晶矽插塞920與位 元線720有效地並完全地隔絕，而不再有發生短路的可能， 並且，複晶矽插塞920與複晶矽接觸墊910的接觸面將更容 易被控制而減少面積的損失，因而達到本發明之目的。 以上所述係利用較佳實施例詳細說明本發明，而非限制 本發明的範圍，且本發明亦可推廣應用到積體電路中任何導 電結構間之隔離，因此熟知此技藝的人士應能明瞭，適當而 作些微的改變與調整，仍將不失本發明之要義所在，亦不脫 離本發明之精神和範圍，故都應視爲本發明的進一步實施狀 況。謹請貴審查委員明鑑，並祈惠准，是所至禱。 !卜 — _.----------—訂^------鎳 一对先間讀背而之注念f項"填^本".) 經濟部中央標"局K工消費合作.社印製 &及適用中國國家榡準（CNS )八4叱诂.（210.01^.公.V. Description of the invention () A cushion structure 830 that can completely cover the side walls of the bit line 720 can be formed; finally, a polycrystalline silicon layer is deposited to fill the contact window, and a polycrystalline silicon etch-back step is attached to The fabrication of a poly plug 920 in the contact window of the capacitor node is completed. As mentioned above, the present invention utilizes the production of a cover stop layer (SiN / oxide or SiON / oxide), opens the contact window in two stages, and processes the polycrystalline silicon bit line 720 that may be exposed between the two stages of etching. In this way, the silicon nitride pad structure 830 can effectively and completely isolate the conductive polycrystalline silicon plug 920 from the bit line 720 without the possibility of a short circuit, and the polycrystalline silicon The contact surface of the silicon plug 920 and the polycrystalline silicon contact pad 910 will be more easily controlled to reduce the area loss, thus achieving the purpose of the present invention. The above description uses the preferred embodiments to describe the present invention in detail, but does not limit the scope of the present invention, and the present invention can also be applied to the isolation between any conductive structures in integrated circuits, so those skilled in the art should be able to understand Changes and adjustments that are appropriate and appropriate still will not lose the essence of the invention, nor deviate from the spirit and scope of the invention, so they should be regarded as further implementation of the invention. I would like to ask your reviewers to make a clear reference and pray for your sincere prayer. ! Bu — _.------------ Order ^ ------ Nickel reads the f item in advance and commemorates item f " Fill in ^ this ".) Central standard of the Ministry of Economic Affairs " Bureau of Industrial and Consumer Cooperation. Printing & and applicable China National Standards (CNS) 8 4 叱 诂. (210.01 ^. public.