522524 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（） 發明領域： 本發明係有關於動態隨機存取記憶體（Dynamic Random Access Memory ; DRAM)之製造方法，特別是有關 於具位元線下電容器（CaPacitor-Under-Bit Line ; CUB)之 DRAM的製造方法。 發明背景： 動態隨機存取記憶體是一種廣泛應用的積體電路元 件，尤其在今日資訊電子產業中更佔有極重要的地位。隨 著製程技術的演進，目前生產線上常見的動態隨機存取記 憶單元（DRAM cell)大多是由一電晶體τ和一電容器c所 構成，如第1圖的電路圖所示者。基本上，電晶體T的 源極（Source)係連接到一對應的位元線（Bit Une)BL，汲 極（Drain)連接到電容器c的儲存電極（Storage Electrode)，而閘極（Gate)則連接到一對應的字元線（word Line)WL，電容器C的相對電極（〇pp〇sed Electr〇de)係連 接到一固疋電壓源’而在儲存電極和相對電極之間則設置 一介電質層。 近年來由於各類電子元件均朝高積集度及高速率運作 及微小化的方向發展。對於DRAM的記憶單元來說，在積 本紙張尺度顧中國國家標準（CNS)A4規格(21〇729?^^" (請先閱讀背面之注意事項再填寫本頁) 裝 •^- 522524 A7 B7 五、發明說明（） 體化後’因為電容電極接觸面積變小，造成電容量下降， 因此目月ϋ有溝槽型（Trench-type)、堆疊型（Stacked-type)以 及冠型（Cr〇wn-type)等三種增加電容電極接觸面積方法，使 得電容量的提昇。另外，具位元線下電容器（CUB)之動態隨 機存取#己憶體係為用來改善dram元件密度的方法之一， 可利用自動對準（Self-Align)之方法來製造CUB DRAM中 的位元線位置，有助於縮小積體電路尺寸的製程改善。積 體電路製造朝向縮小線寬的方向發展，線寬縮小可使積體 電路的水平尺寸縮小，但是垂直尺寸方面仍由於縱橫比 (Aspect Ratio)的增大，而增加了製程難度。例如，在CUB DRAM結構中，多層接觸開口所需的微影蝕刻製程，係為 縮小CUB DRAM尺寸的一大瓶頸。 經濟部智慧財產局員工消費合作社印製 ------:!11·11 幸裝 i — (請先閱讀背面之注意事項再填寫本頁) 第2圖所緣示為習知具位元線下電容器之動態隨機存 取記憶體之結構剖面圖。其中，介電層1 〇 6位在具有數個 淺溝渠隔離102的基材1〇〇上，在介電層ι〇6間，並有數 個字元線104與插塞108。另外，位於介電層丨〇6上的另 一介電層11〇中，並具有數個電容器結構，其中電極112 係為此些電容器之下電極結構，複晶矽層丨丨4係為電容器 之上電極結構。而以介電層1 1 6與電容器結構絕緣，並與 基材100上之一插塞108連接的便是位元線118。 第3圖所繪示為發生微影製程之對準誤差時，習知具 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公t ) 522524 A7 ^--------— B7 ____ 五、發明說明（） 位70線下電容器之動態隨機存取記憶體之結構剖面圖。請 對照第2圖與第3圖，其中，由於微影製程的對準不佳， 使原有的位元線U 8位置朝左方偏移，使位元線1 1 8與插 塞108之一的接觸不良，而造成如第3圖中的缺陷12〇。 另外’位元線11 8的位置朝左方偏移，有可能與電容器結 構的上電極’亦即複晶矽層1 1 4接觸而造成短路現象，如522524 A7 B7 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention () Field of the invention: The present invention relates to a manufacturing method of Dynamic Random Access Memory (DRAM), especially to Method for manufacturing DRAM of CaPacitor-Under-Bit Line (CUB). Background of the invention: Dynamic random access memory is a widely used integrated circuit element, and it occupies a very important position in today's information electronics industry. With the evolution of process technology, the dynamic random access memory cells (DRAM cells) commonly used in current production lines are mostly composed of a transistor τ and a capacitor c, as shown in the circuit diagram in Figure 1. Basically, the source of the transistor T is connected to a corresponding bit line BL, the drain is connected to the storage electrode of the capacitor c, and the gate is It is connected to a corresponding word line WL. The opposite electrode (〇pp〇sed Electrode) of the capacitor C is connected to a fixed voltage source 'and a storage electrode is provided between the storage electrode and the opposite electrode. Dielectric layer. In recent years, various types of electronic components have developed in the direction of high accumulation, high-speed operation, and miniaturization. For the DRAM memory unit, the Chinese paper standard (CNS) A4 specification (21〇729? ^^ " (Please read the precautions on the back before filling out this page) on the paper size. • 522-524 A7 B7 V. Description of the invention () After the integration, 'the capacitance decreases because the contact area of the capacitor electrode becomes smaller, so Trench-type, stacked-type, and crown-type (Cr 〇wn-type) and other three methods to increase the contact area of the capacitor electrode, which improves the capacitance. In addition, the dynamic random access #CUB with bit-line capacitors (##) memory system is a method to improve the density of the dram element. First, the self-align method can be used to manufacture the bit line position in the CUB DRAM, which helps to improve the manufacturing process of reducing the size of the integrated circuit. The integrated circuit manufacturing is developing in the direction of reducing the line width. The width reduction can reduce the horizontal size of the integrated circuit, but the vertical size still increases the difficulty of the process due to the increase of the aspect ratio. For example, in the CUB DRAM structure, the lithography required for multilayer contact openings Etching This is a major bottleneck for reducing the size of CUB DRAM. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ------ :! 11 · 11 Fortunately i — (Please read the precautions on the back before filling this page The edge of Figure 2 is a structural cross-sectional view of a conventional dynamic random access memory with bit-line capacitors. The dielectric layer 106 is located on a substrate 1 with a plurality of shallow trench isolations 102. There are several word lines 104 and plugs 108 between the dielectric layers ι0. In addition, another dielectric layer 11 is located on the dielectric layer 〇6 and has several capacitor structures. Among them, the electrode 112 is the electrode structure below these capacitors, and the polycrystalline silicon layer 丨 4 is the electrode structure above the capacitor. The dielectric layer 1 16 is insulated from the capacitor structure and is one of the substrate 100. The plug 108 is connected to the bit line 118. When the alignment error in the lithography process occurs as shown in Figure 3, it is known that the paper size is applicable to the Chinese National Standard (CNS) A4 (210 x 297 mm) ) 522524 A7 ^ --------— B7 ____ V. Description of the invention () Dynamic random access record for capacitors below 70 lines Cross-sectional view of the structure of the body. Please refer to Figure 2 and Figure 3. Among them, due to the poor alignment of the lithography process, the original bit line U 8 is shifted to the left and the bit line 1 1 The contact between 8 and one of the plugs 108 is bad, which causes defect 12 as shown in Figure 3. In addition, the position of bit line 11 8 is shifted to the left, which may be the same as the upper electrode of the capacitor structure. Crystal silicon layer 1 1 4 contact and cause short circuit phenomenon, such as
缺陷122。上述因微影製程之對準誤差容易使得CUB DRAM 的產品良率下降，並且由於微影製程的困難度而無法使元 件尺寸縮小。 發明目的及概述： 雲於上述之發明背景中，習知縮小CUB DRAM尺寸之 製ie方法係受限於微影製程，尤其在位元線之圖案化時， 谷易造成對準上的誤差。因此，本發明之目的係在提供一 種CUB DRAM之製造方法，係利用等向性蝕刻來增加位元 線接觸開口的製程窗，如此可避免後續製造位元線之微影 製程的對準誤差，有助於CUB DRAM元件的尺寸縮小化。 本發明的再一目的係提供一種利用氫氧化銨之濕蝕刻 製程’藉以去除部分做為電容器之上電極層的非晶矽層而 增加位疋線接出開口的製程窗，係利用氫氧化銨溶液對介 電層與氮化層的高蝕刻選擇比，以避免破壞Dram或電容 本紙張尺度適用中國國家標準(CNSM4規格（2ι〇χ 297公爱） -----1!---:丨丨#-裝·！ (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 522524 A7 __________B7___ 五、發明說明（） 器結構，如此可提高DRAM元件生產的良率。 根據以上所述之目的，本發明提供一種動態隨機存取 記憶體之製造方法，係用來製造具位元線下電容器之動態 隨機存取記憶體，其製造方法至少包括：提供一基材；形 成第一介電層於基材上，其中，在第一介電層中係具有數 個字元線與數個插寨結構；接著，形成第二介電層於第一 介電層上，其中，在第二介電層中係具有數個電容器結構 之下電極；形成上電極層以覆蓋下電極與第二介電層；定 義上電極層以形成第一開口區，並暴露出部分之第二介電 層；隨後，進行等向性餘刻步驟，使第一開口區擴大為第 二開口區；形成第三介電層以覆蓋上電極層與第二開α 區；最後，形成位元線。 經濟部智慧財產局員工消費合作社印製 ------------1 --- (請先閱讀背面之注意事項再填寫本頁) 本發明動態隨機存取記憶體之製造方法中，上述之等 向性蝕刻可利用濕蝕刻步驟’更可利用氫氧化銨溶液。因 此，本發明動態隨機存取記憶體之製造方法更可包括：提 供已形成數個淺溝渠隔離的基材；形成數個字元線於基材 上；接著，形成第一介電層，並再定義出數個插塞結構在 第一介電層中；隨後，形成第二介電層於第一介電層上， 並圖案化第二介電層’以形成數個第一開口區於第二介電 層中，其中，上述第一開口區係用以在後續步驟形成數個 電容器結構；隨後，形成數個下電極以覆蓋上述第一開口 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 522524 A7 B7 五、發明說明（） ------^---^丨秦-裝—— (請先閱讀背面之注意事項再填寫本頁) 區，再形成上電極層以覆蓋上述下電極與第二介電層；隨 後，定義上電極層以形成第二開口區，並暴露出部分之第 二介電層；利用氫氧化銨溶液進行濕蝕刻步驟，使第二開 口區擴大為第三開口區；最後，形成第三介電層以覆蓋上 電極層與第三開口區，並圖案化第三介電層以形成第四開 口區，再形成位元線以覆蓋第四開口區。 本發明動態隨機存取記憶體之製造方法，更包括在形 成該些下電極步驟之後，形成數個半球形矽晶粒（Hemi_ Spherical Grain ; HSG)於下電極之表面。另外，亦可在形 成半球形矽晶粒步驟之後，形成第四介電層以覆蓋半球形 矽晶粒與下電極。 本發明之一實施例中，係利用以摻雜之非晶矽層來做 為電容器結構之上電極層，其較佳厚度約在15〇〇a_25〇〇a 經濟部智慧財產局員工消費合作社印製 之間，以配合氫氧化銨溶液的濕蝕刻製程。上述濕姓刻步 驟中使用的氫氧化銨溶液之較佳濃度係為氫氧化銨與水的 重量比例約為1.5: 1 00(45t下），並浸泡該氫氧化銨溶液 約670秒。另外，上述之第二介電層可由硼磷矽玻璃 (BPSG)、或電漿加強式之四乙基磷矽酸鹽（pETE〇s)所構 成，第四介電層可由氮化矽/氧化矽（N〇）所構成。 圖式簡單說明： 本紙張尺度適用中國國家標準（CNSM4規格（210 X 297公餐） 經濟部智慧財產局員工消費合作社印製 522524 A7 _B7_ 五、發明說明（） 本發明的較佳實施例將於往後之說明文字中輔以下列 圖形做更詳細的闡述，其中： 第1圖所繪示為習知動態隨機儲存記憶單元之電路 圖； 第2圖所繪示為習知具位元線下電容器之動態隨機存 取記憶體之結構剖面圖； 第3圖所繪示為發生微影製程之對準誤差時，習知具 位元線下電容器之動態隨機存取記憶體之結構剖面圖；以 及 第4圖至第9圖所繪示為本發明具位元線下電容器之 動態隨機存取記憶體之製造流程圖。 圖號對照說明： 100 基 材 102 淺 溝 渠 隔 離 104 字 元 線 106 介 電 層 108 插 塞 1 10 介 電 層 1 12 電 極 1 14 複 晶 矽 層 1 16 介 電 層 1 18 位 元 線 120 缺 陷 122 缺 陷 200 基 材 202 淺 溝 渠 隔 離 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） #-裝. * 訂------- # (請先閱讀背面之注意事項再填寫本頁) 522524 A7 B7 五、發明說明（ 204 字元線 206 介電層 208 插塞 210 介電層 212 下電極 214 半球形石夕晶粒 216 上電極層 216a 上電極層 216b 上電極層 218 光阻 220 開口 220a 開口 222 介電層 222a 介電層 224 光阻 226 開口圖案 227 開口 228 位元線 T 電晶體 C 電容器 WL 字元線 BL 位元線 X 姓刻方向 Y 姓刻方向 發明詳細說明： ---丨丨·*裝--------訂· (請先閱讀背面之沒意事項再填寫本頁) 3白知縮小CUB DRAM尺寸的製程係受限於微影製程， 尤其微影製程的對準正確性方面，容易造成CUB DRAM結 構中位το線位置的誤差，而使動態隨機存取記憶體的品質 良率下降。 第4圖至第9圖所繪示為本發明具位元線下電容器之 動態隨機存取記憶體之製造流程圖。請參照第4圖，其中 係提供一已形成數個淺溝渠隔離2〇2的基材200，並在基 本紙張尺度適用中國國家標準（CNSM4規格（210 χ 297公^7 雜 經濟部智慧財產局員工消費合作社印製 522524 經濟部智慧財產局員工消費合作社印製 A7 ________B7 _ _ 五、發明說明（） 材200上形成數個字元線2〇4。接著，形成介電層2〇6以 覆蓋基材200與字元線204，並在介電層206中形成數個 插塞208°隨後，形成介電層21〇於介電層206上，並定 義出電容器結構的位置，再形成電容器結構之下電極2 i 2 於其中。接著’形成數個半球形矽晶粒（HSG)214於下電極 2 1 2之表面’並形成介電層（未繪出）以覆蓋該些半球形矽晶 粒214與下電極212。隨後，形成上電極層216以覆蓋半 球形矽晶粒2 1 4、下電極2 1 2與介電層2 1 0。其中，上述之 介電層210可由硼磷矽玻璃、或電漿加強式之四乙基磷矽 酸鹽所構成。另外’上述覆蓋在半球形矽晶粒2 1 4之介電 層（未繪出）可由氮化矽/氧化矽（N〇)所構成。值得注意的 疋，本發明形成半球形石夕晶粒2 1 4係用來增加電容器之電 極表面積，如不製造此半球形矽晶粒2 1 4亦可完成本發明 之製造方法，本發明不限於此。 請參照第5圖，利用光阻2 1 8以定義第4圖之上電極 層216,並進行蝕刻步驟以形成開口 22〇與上電極層216a， 並暴露出部分之介電層210，此開口 22〇係用來做為後續 位元線形成之位置。接著，請參照第6圖，進行等向性之 触刻步驟’利用X姓刻方向與γ蚀刻方向等姓刻速率之特 性，形成厚度較薄的上電極層2丨6b，並使原來的開口 22〇 擴大為開口 220a，如第7圖所示。 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公餐） ----“丨丨」丨丨#.裝--------訂. (請先閱讀背面之注意事項再填寫本頁) # 五、發明說明（） 在本發明之一實祐 、+，地 例中，係利用濕蝕刻製程來做為上 述之專向性姓刻步驟 ---------— ^ · M i — (請先閱讀背面之注意事項再填寫本頁) W ’另外，本發明更可利用氫氧化銨溶 液來做為濕蝕刻製尹 <餘刻劑’此氫氧化銨溶液之蝕刻劑 溫度約在30。(：至7(rr叫 υ L間，而氫氧化銨與水的重量比例在 1 ·· 200 至 1 : 50 間 1 里 白可’較佳的氫氧化銨溶液濃度為氫氧 化錄與水的重量比例 為1.5 : 100(451下）。為配合氫氧 化銨溶液之蝕刻製链 ^ % ’本發明之一較佳實施例中，係利用 已摻雜之非晶矽層來 1又馬電谷态結構之上電極層，因此， 由於氫氧化銨溶液可斟 野#日日矽層、介電層（BPS(}與PETEOS) 與ΪΙ化層間有高钱刻選 擇比，因此不會造成對介電層210 與半球形矽晶粒2 1 4 u ^ 上的NO結構有傷害，非常適用於本 發明之製造方法。复由 卜择 “甲’虱乳化銨溶液對非晶矽/BPSG、與 非晶碎/PEiTElOS的L、 蚀幻選擇比分別為5 〇 · 8及8 3.7，另外， 由於氫氧化録溶汸料# β ^ 卜 夜對虱化層之蝕刻選擇比應較氧化層為 南由上述氫氧化銨溶液對氧化層（BpSG與PETE〇s)的姓 刻選擇比可知其對氮化層亦有非常高之蝕刻選擇比。 經濟部智慧財產局員工消費合作社印製 利用已摻雜之非晶矽層來做為電容器結構之上電極層 216,其較佳厚度約在ι5〇〇Α-25〇〇Α之間，再利用光阻218 疋義出寬度約為〇.3#m至〇.6#m的開口 220。接著，利 用上述較佳之氫氧化銨溶液做為蝕刻劑，進行非等向性蝕 刻步驟’經過約670秒之浸泡後，可使開〇 220的寬度增 加約500A至2000A間，而形成開口 220a。值得注意的是， 10 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公t ) 522524Defect 122. Due to the alignment error of the lithography process, the product yield of CUB DRAM is easily reduced, and the size of the component cannot be reduced due to the difficulty of the lithography process. Object and summary of the invention: In the above background of the invention, the conventional manufacturing method of reducing the size of CUB DRAM is limited by the lithography process, especially when the bit line is patterned, the valley is liable to cause alignment errors. Therefore, the object of the present invention is to provide a manufacturing method of CUB DRAM, which uses isotropic etching to increase the process window of the bit line contact opening, so as to avoid the alignment error of the lithography process for subsequent fabrication of the bit line. Helps reduce the size of CUB DRAM components. Yet another object of the present invention is to provide a process window using ammonium hydroxide wet etching process to remove a portion of the amorphous silicon layer which is used as an electrode layer on a capacitor and increase a ridge line connection opening, and use ammonium hydroxide The high etching selection ratio of the solution to the dielectric layer and the nitride layer to avoid damaging the ram or capacitor. The paper size is applicable to the Chinese national standard (CNSM4 specification (2ι〇χ 297 public love) ----- 1! ---:丨 丨 #-装 ·! (Please read the precautions on the back before filling out this page) Order printed by the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs to print 522524 A7 __________B7___ 5. Description of the invention () device structure, so as to improve the production of DRAM components According to the above-mentioned object, the present invention provides a method for manufacturing a dynamic random access memory, which is used to manufacture a dynamic random access memory with a bit-line capacitor. The manufacturing method at least includes: providing a A substrate; forming a first dielectric layer on the substrate, wherein the first dielectric layer has a plurality of word lines and a plurality of insert structures; and then, a second dielectric layer is formed on the first dielectric layer Layer, Among them, the second dielectric layer has a plurality of lower electrodes with a capacitor structure; an upper electrode layer is formed to cover the lower electrode and the second dielectric layer; an upper electrode layer is defined to form a first opening region, and a part of it is exposed A second dielectric layer; subsequently, an isotropic post-etching step is performed to expand the first opening region into a second opening region; forming a third dielectric layer to cover the upper electrode layer and the second open alpha region; and finally, forming a bit Yuan line. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ------------ 1 --- (Please read the precautions on the back before filling this page) The dynamic random access memory of the present invention In the manufacturing method, the above isotropic etching can use a wet etching step, and moreover, an ammonium hydroxide solution can be used. Therefore, the manufacturing method of the dynamic random access memory of the present invention can further include: providing a plurality of shallow trench isolations that have been formed. Forming a plurality of word lines on the substrate; then, forming a first dielectric layer, and further defining a plurality of plug structures in the first dielectric layer; subsequently, forming a second dielectric layer on On the first dielectric layer and patterning the second dielectric layer 'to A plurality of first opening regions are formed in the second dielectric layer, wherein the first opening regions are used to form a plurality of capacitor structures in subsequent steps; subsequently, a plurality of lower electrodes are formed to cover the first openings. China National Standard (CNS) A4 specification (210 X 297 mm) 522524 A7 B7 V. Description of the invention () ------ ^ --- ^ 丨 Qin-installation-(Please read the precautions on the back first Fill in this page) area, and then form an upper electrode layer to cover the above lower electrode and the second dielectric layer; then, define the upper electrode layer to form a second open area and expose a part of the second dielectric layer; using hydroxide The ammonium solution is subjected to a wet etching step to expand the second opening area into a third opening area; finally, a third dielectric layer is formed to cover the upper electrode layer and the third opening area, and the third dielectric layer is patterned to form a fourth In the opening area, a bit line is formed to cover the fourth opening area. The method for manufacturing a dynamic random access memory of the present invention further comprises, after the steps of forming the lower electrodes, forming a plurality of hemispherical silicon grains (Hemi_Spherical Grain; HSG) on the surface of the lower electrode. Alternatively, after the step of forming the hemispherical silicon grains, a fourth dielectric layer may be formed to cover the hemispherical silicon grains and the lower electrode. In one embodiment of the present invention, a doped amorphous silicon layer is used as the electrode layer on the capacitor structure, and its preferred thickness is about 15000a-2500a. In order to match the wet etching process of ammonium hydroxide solution. The preferred concentration of the ammonium hydroxide solution used in the above-mentioned wet lasting step is that the weight ratio of ammonium hydroxide to water is about 1.5: 100 (at 45t), and the ammonium hydroxide solution is soaked for about 670 seconds. In addition, the above-mentioned second dielectric layer may be composed of borophosphosilicate glass (BPSG), or plasma-enhanced tetraethylphosphosilicate (pETE0s), and the fourth dielectric layer may be made of silicon nitride / oxide. Silicon (N〇). Brief description of the drawing: This paper size applies the Chinese national standard (CNSM4 specification (210 X 297 meals) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 522524 A7 _B7_ V. Description of the invention () The preferred embodiment of the present invention will be The following descriptions are supplemented by the following figures for more detailed explanation, where: Figure 1 shows the circuit diagram of the conventional dynamic random storage memory unit; Figure 2 shows the conventional offline capacitor with bit A cross-sectional view of the structure of the dynamic random access memory; FIG. 3 is a cross-sectional view of the structure of the dynamic random access memory of the bit line capacitor when the alignment error of the lithography process occurs; and Figures 4 to 9 show the manufacturing flow chart of the dynamic random access memory of the bit-line capacitors of the present invention. Comparison of drawing numbers: 100 substrate 102 shallow trench isolation 104 word line 106 dielectric Layer 108 plug 1 10 dielectric layer 1 12 electrode 1 14 polycrystalline silicon layer 1 16 dielectric layer 1 18 bit line 120 defect 122 defect 200 substrate 202 shallow trench From this paper size, the Chinese National Standard (CNS) A4 specification (210 X 297 mm) is applicable. #-装. * Order ------- # (Please read the precautions on the back before filling this page) 522524 A7 B7 V. Description of the invention (204 word line 206 dielectric layer 208 plug 210 dielectric layer 212 lower electrode 214 hemispherical stone grain 216 upper electrode layer 216a upper electrode layer 216b upper electrode layer 218 photoresist 220 opening 220a opening 222 Dielectric layer 222a Dielectric layer 224 Photoresist 226 Opening pattern 227 Opening 228 Bit line T Transistor C Capacitor WL Word line BL Bit line X Surname engraving direction Y Surname engraving direction Detailed description of the invention: --- 丨 丨 · * Installation -------- Order · (Please read the unintentional matter on the back before filling in this page) 3 Bai Zhi's process of reducing the size of CUB DRAM is limited by the lithography process, especially the alignment of the lithography process In terms of correctness, it is easy to cause an error in the position of the bit το line in the CUB DRAM structure, which will reduce the quality of the dynamic random access memory. Figures 4 to 9 show the bit-line capacitors of the present invention. Manufacturing flow chart of dynamic random access memory. Please refer to Figure 4 , Which is to provide a base material 200 that has formed several shallow trenches to isolate 200, and apply the Chinese national standard (CNSM4 specification (210 x 297 g ^ 7) printed on the consumer paper of the Intellectual Property Bureau of the Ministry of Economic Affairs at the basic paper size. 522524 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 ________B7 _ _ V. Description of the Invention () Several character lines 204 are formed on the material 200. Next, a dielectric layer 206 is formed to cover the substrate 200 and the word line 204, and a plurality of plugs 208 are formed in the dielectric layer 206. Subsequently, a dielectric layer 21 is formed on the dielectric layer 206, and The position of the capacitor structure is defined, and the electrodes 2 i 2 below the capacitor structure are formed therein. Next, a plurality of hemispherical silicon grains (HSG) 214 are formed on the surface of the lower electrode 2 1 2 and a dielectric layer (not shown) is formed to cover the hemispherical silicon grains 214 and the lower electrode 212. Subsequently, an upper electrode layer 216 is formed to cover the hemispherical silicon crystal grains 2 1 4, the lower electrode 2 1 2 and the dielectric layer 2 1 0. Wherein, the above-mentioned dielectric layer 210 may be made of borophosphosilicate glass or plasma-reinforced tetraethylphosphosilicate. In addition, the above-mentioned dielectric layer (not shown) covering the hemispherical silicon grains 2 1 4 may be composed of silicon nitride / silicon oxide (N0). It is worth noting that the formation of hemispherical stone crystal grains 2 1 4 in the present invention is used to increase the electrode surface area of the capacitor. The manufacturing method of the present invention can be completed without manufacturing the hemispherical silicon crystal grains 2 1 4. Limited to this. Referring to FIG. 5, a photoresist 2 1 8 is used to define the upper electrode layer 216 in FIG. 4, and an etching step is performed to form an opening 22 and an upper electrode layer 216 a, and a part of the dielectric layer 210 is exposed. This opening 22〇 is used as the position for the subsequent formation of bit lines. Next, please refer to FIG. 6 and perform the isotropic touch step 'using the characteristics of the X-engraving direction and the γ-etching direction to form a thin upper electrode layer 2 6b, and make the original opening 220 is enlarged into the opening 220a, as shown in FIG. This paper size applies to China National Standard (CNS) A4 specification (210 X 297 meals) ---- "丨 丨" 丨 丨 # .Packing -------- Order. (Please read the note on the back first (Please fill in this page again for details) # V. Description of the invention () In one of the inventions, +, in the example, the wet etching process is used as the above-mentioned specific surname engraving step ------- --- ^ · M i — (Please read the precautions on the back before filling out this page) W 'In addition, the present invention can also use ammonium hydroxide solution as a wet etching Yin < Etchant ' this hydroxide The temperature of the etchant of the ammonium solution is about 30 ° C. (: To 7 (rr is called υ L, and the weight ratio of ammonium hydroxide to water is between 1 ·· 200 to 1: 50 between 1 and 50 liters. The preferred concentration of ammonium hydroxide solution is that of hydroxide and water. The weight ratio is 1.5: 100 (at 451). In order to match the etching chain with ammonium hydroxide solution, ^% 'In a preferred embodiment of the present invention, a doped amorphous silicon layer is used to form a silicon wafer. The electrode layer above the state structure, therefore, because the ammonium hydroxide solution can pour the # silicon layer, the dielectric layer (BPS ( The electric layer 210 and the NO structure on the hemispherical silicon grain 2 1 4 u ^ are harmful, which is very suitable for the manufacturing method of the present invention. The compound "A 'lice emulsified ammonium solution for amorphous silicon / BPSG, The crystallization / PEiTElOS L and etch selectivity ratios are 5 0 · 8 and 8 3.7, respectively. In addition, because of the oxidative selectivity of the oxidized layer by the hydroxide solution # β ^ Bu Ye should be souther than the oxide layer It can be seen that the ammonium hydroxide solution has a very high etching selection ratio for the oxide layer (BpSG and PETE0s). The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed a doped amorphous silicon layer as the electrode layer 216 on the capacitor structure, and its preferred thickness is between ι 500 and 25 〇Α. A photoresist 218 is used to define an opening 220 having a width of about 0.3 # m to 0.6 # m. Then, using the above-mentioned preferred ammonium hydroxide solution as an etchant, an anisotropic etching step is performed 'after about After soaking for 670 seconds, the width of Kai 220 can be increased by about 500A to 2000A to form an opening 220a. It is worth noting that 10 paper sizes are applicable to China National Standard (CNS) A4 (210 X 297 g) 522524
五、發明說明（ 以上僅為本發明較佳實施例之舉例，並非用以 之範圍。 發明 接著，請參照第8圖，形成介電層222以覆蓋第7圖 之結構，再利用具有開口圖案226的光阻以定義出位天 線⑵之開口 227。最後’形成位元線⑶於上述之開： 227位置’其結構如第9圖所示。本發明的特點在於利用 非等向性之㈣步驟’使開σ 22Q增大，使後續利用光阻 224定義位元線228位置時，有較大的製程窗可減少對準 誤差，並可避免上電極216b與位元線228之短 本發明利用#向性姓刻來加大後續製造位it線的接觸 開口’如此可減少習知利用帛5圖之光阻218與第8圖之 光阻224的微影製程，而必須考慮的對準與誤差問題。當 增加開α 220的尺寸，可減少電容器之上電極層與位元線 之短路機率，後續利用光阻224之微影製程以製造位元線 228時，其製程窗也較寬廣，如此，有助於cub drΑΜ元 件的尺寸縮小化。 ----卜！ l#i·! (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 本發明利用氫氧化鐘溶液的向餘刻選擇性來做為濕餘 刻製程之蝕刻劑，以去除部分做為電容器之上電極層，如 非晶矽層，並可避免破壞周遭的DRAM或電容器結構，如 此可提高DRAM元件生產的良率。 11 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 522524 A7 _B7_ 五、發明說明（) 如熟悉此技術之人員所瞭解的，以上所述僅為本發明 之較佳實施例而已，並非用以限定本發明之申請專利範 圍；凡其它未脫離本發明所揭示之精神下所完成之等效改 變或修飾，均應包含在下述之申請專利範圍内。 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）V. Description of the invention (The above is only an example of the preferred embodiment of the present invention, and is not intended to be used in scope. Next, please refer to FIG. 8 to form a dielectric layer 222 to cover the structure of FIG. 7, and then use an opening pattern. The photoresistor of 226 defines the opening 227 of the bit antenna. Finally, the bit line ⑶ is formed at the above opening: 227 position. Its structure is shown in Figure 9. The present invention is characterized by the use of non-isotropic Step 'Increase the opening σ 22Q, so that when the position of the bit line 228 is defined by the photoresist 224 in the future, a larger process window can reduce the alignment error and avoid the shortness of the upper electrode 216b and the bit line 228 The use of # 向性 surname engraving to increase the contact opening of the it line in the subsequent manufacturing position 'can reduce the conventional lithography process using the photoresist 218 in FIG. 5 and the photoresist 224 in FIG. 8, and the alignment that must be considered And the error problem. When the size of the open α 220 is increased, the short circuit probability of the electrode layer and the bit line on the capacitor can be reduced. When the photolithography process of photoresist 224 is used to manufacture the bit line 228, the process window is also wider , So that helps the cub drΑΜ components Reduced size. ——Bu! L # i ·! (Please read the notes on the back before filling out this page) Order by the Intellectual Property Bureau Staff Consumer Cooperative of the Ministry of Economic Affairs to print the present invention using the hydroxide solution Selectively used as an etchant in the wet after-etching process to remove a portion as an electrode layer on the capacitor, such as an amorphous silicon layer, and avoid damaging the surrounding DRAM or capacitor structure, which can improve the yield of DRAM device production . 11 This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) 522524 A7 _B7_ V. Description of the invention () As understood by those skilled in the art, the above is only the best of the present invention. The examples are not intended to limit the scope of patent application of the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention should be included in the scope of patent application described below. (Please read first Note on the back, please fill in this page again.) The paper printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs is compliant with China National Standard (CNS) A4 (210 X 297 mm).