4 1 9 81 7 ·' ^ a? B7 經濟部智慧財產局員工消費合作杜印製 五、發明説明（） 發明頜域： 本發明與一種半導體製程之動態隨機存取記憶胞 (DRAM cell)有關，特別是一種藉著淸除在化學機械硏磨 程序中所產生污染微粒以提高良率之高密度動態隨機存 取記億胞其製作方法。 潑明背暑： 在積體電路的發展過程中，動態隨機存取記憶體 (DRAM)元件一直受到極廣泛的應用。對一個典型的動態 隨機存取記憶體（DRAM)而言，其內部往往具有許多的記 憶胞（memory cell)，且其記憶胞通常由電容器與電晶體 所構成。因此在製造DRAM記憶胞時*往往也包含了電 晶體與電容之製程，並藉著電容器與電晶體之電性接觸* 將數位資訊儲存在電容器中。再藉由金氧半場效電晶體 (MOSFETs)、位元線（bit line)、字語線（word line)陣歹丨j 來對電容器進行數位資料之存取。然而，隨著超大型積體 電路（ULSI)的發展，爲了滿足高積集度積體電路之設計趨 勢，動態隨機存取記億胞（DRAM cell)之尺寸亦隨著降至 次微米以下。而且由於元件不斷的縮小，促使DRAM中 電容的尺寸也隨之減少，故其儲存載子之性能亦相對降 低。是以對動態隨機存取記憶體（DRAM)中之記憶胞 (memory cell)而言，所面臨的最大問題是如何在元件尺 寸趨向於縮小且積集度持續提高之情形下，提昇電容的儲 (請先閲讀背面之注$項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4规格（2丨0X297公釐） 4 1 9 8 ί 7 w Α7 _Β7_ 五、發明説明（） 存能力，並增加電容的可靠度，以避免電容器在讀取資料 時受雜質影響{如α粒子）而產生軟記錯（soft errors)，或 是電容的“再補充（refresh)”頻率增加等等。 爲了解決上述之問題，在電容器的製造上，往往朝 著增加電容表面積之方向而努力，並由此陸續發展出溝渠 式電容與皇冠型電容。近來更藉著在電容的底部電極表面 上形成半球狀結晶顆粒（Hemispherica卜grain)，以便進 一步提昇電容之儲存能力。一般而言，典型的多重指狀電 容器之製程如第一圖所示，首先提供一單晶矽底材12, 且形成場氧化區域11於半導體底材12之上，以做爲元 件間絕緣之用。接著，以習知技術依序形成字語線 (wordlines)13、以及位於字語線13側壁上之側壁間隙 (sidewall spacers)14，再以離子植入方式形成汲極/源 極摻雜區15。接著在該半導體底材12上形成介電層 16,並形成阻障層22於該介電層16上。再對阻障層22 與介電層16進行蝕刻程序，以分別形成導通底部電極之 接觸孔17A與導通位元線（未顯示於圖中）之接觸孔 17B。隨後，運用傳統技術分別形成導通底部電極之導電 插塞（plugs)18A與導通位元線之導電插塞18B。 經濟部智慧財產局員工消资合作社印製 .-nn ^n. I - JH I. - - ml —^ϋ ^^1 1^1 (請先閲讀背勤之注意事項苒填寫本頁) 接著請參照第二圖，隨後形成介電層25於阻障層 22與導電插塞18A及18B之上。再藉由蝕刻技術形成 開口 32於介電層25上以曝露導電插塞18A之上表面， 並做爲後續形成電容底部電極之用。隨後如第三圖所示1 形成一非晶砂層（amorphous silicon)41以覆蓋介電層 本紙張尺度適用中國國家標準（CNS) A4说格（210X297公釐） 4 J S 8 Γ7 .. Λ7 Α7 Β7 經濟部智慧財產局W工消費合作社印製 五、發明説明（） 25以及導電插塞18A之上表面。並在該非晶矽層41之 表面，形成半球狀顆粒（HSG)矽結晶以增加電容底部電極 之表面積。其中値得注意的是該非晶矽層41具有位於介 電層25上表面之水平部份42。接著如第四圖所示，藉 .由化學機械硏磨（CMP)程序移除該非晶矽層41位於介電 層25上表面之水平部份42，再藉著運用傳統技術之蝕 刻技術移除介電層25，如此可得到電容器之底部電極 51，且該底部電極51之表面具有上述之半球狀顆粒（.HSG) 矽結晶61。接著請參照第五圖，在於該半導體底材12 之上表面形成一薄介電層81以覆蓋該阻障層22與底部 電極51之上表面。再於該薄介電層81之上表面形成作 爲電容頂部電極之導電層82。 然而如同上述，在進行化學硏磨程序以移除該非晶 矽層41位於介電層25上表面之水平部份42時，如第 六圖所示，往往會產生數量極多之污染微粒84,且該污 染微粒84往往會掉落並聚集於電容的皇冠型結構中，亦 即所產生之污染微粒84會陷落於非晶矽層41之表面 上，其中污染微粒除了由於對非晶矽層41進行硏磨所產 生之矽粒子外，更包括了在進行化學機械硏磨製程中所加 入之硏漿微粒'如此一來，導致後續進行淸除污染微粒程 序產生極大之因難。特別是爲了增加電容底部電極之表面 積，在電容的底部電極表面如同上述|往往具有半球狀顆 粒結晶表面，是以經常會導致化學硏磨製程中之硏漿粒子 陷於該半球狀顆粒結晶之縫隙中而難以加以淸除，由此降 ----^------^------tr------§,. (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中固a家搮準（CNS ) A4規格（210 X 297公釐} C 〇 A7 B7 經濟部智蒽財產局員工消費合作社印製 五、發明説明（） 低了後續形成薄介電層81之可靠性。 爲了避免上述之污染微粒問題，如第七圖所示，亦 可藉著在該半導體底材12上形成一光阻層86,以覆蓋 做爲電容底部電極之非晶矽層41，且塡入由非晶矽層41 .所形成之皇冠型結構。隨後，對該光阻層86以及非晶矽 層41之水平部份42進行化學硏磨程序。隨後，再移除 位於皇冠型結構中之光阻層86，亦即將位於非晶矽層4 1 表面上之光阻層86移除。然而如此一來，在進行移除皇 冠型結構中之光阻層86步驟時，仍無法有效的避免污染 微粒掉入皇冠型結構中，是以在完成移除光阻層86之程 序後，依舊會有污染微粒陷落於非晶矽層41之上表面。 發明日的及槪沭： 本發明之目的在提供一種積體電路電容之製作方 法。 本發明之另一目的在提供一種可有效淸除在化學 機械硏磨程序中所產生污染微粒之積體電路電容製造方 法。 本發明之方法包含了下列步驟。首先，依序形成位 元線於半導體底材上，並形成氧化層於位元線與半導體底. 材之上表面，再形成氮化層於氧化層之上。接著，蝕刻氧 化層與氮化層以形成接觸孔於半導體底材上，並形成導電 插塞以塡滿該接觸孔。隨後，形成硼磷矽玻璃（BPSG)於 氮化層與導電插塞之上表面，再蝕刻該硼磷矽玻璃以形成 ---------4^-- -- - (請先閲讀背面之注項再填寫本頁) I11 ίΑ丨 * 本紙張尺度適用中國固家棣準（CNS ) Α4規格（2丨ΟΧ297公釐）4 1 9 81 7 · '^ a? B7 Consumption cooperation by employees of the Intellectual Property Bureau of the Ministry of Economic Affairs. Print 5. Invention description () Inventive jaw area: The invention relates to a dynamic random access memory cell (DRAM cell) for a semiconductor process. In particular, it is a high-density dynamic random access memory method for improving yield by removing contaminated particles generated in a chemical mechanical honing process, and a method for manufacturing the same. Summer in the Ming Dynasty: In the development of integrated circuits, dynamic random access memory (DRAM) components have been widely used. For a typical dynamic random access memory (DRAM), there are often many memory cells inside it, and the memory cells are usually composed of capacitors and transistors. Therefore, when manufacturing DRAM memory cells *, the process of transistor and capacitor is often included, and the digital information is stored in the capacitor through the electrical contact between the capacitor and the transistor. Digital capacitors are accessed by the metal-oxide-semiconductor field-effect transistors (MOSFETs), bit lines, and word line arrays. However, with the development of ultra large integrated circuits (ULSI), in order to meet the design trend of high integrated integrated circuits, the size of dynamic random access memory (DRAM cells) has also fallen below sub-microns. In addition, due to the continuous shrinking of the components, the size of the capacitor in the DRAM is also reduced, so the performance of the stored carrier is also relatively reduced. In terms of memory cells in dynamic random access memory (DRAM), the biggest problem is how to increase the storage capacity of capacitors when the component size tends to shrink and the accumulation level continues to increase. (Please read the note on the back before filling in this page.) This paper size applies Chinese National Standard (CNS) A4 specification (2 丨 0X297 mm) 4 1 9 8 ί 7 w Α7 _Β7_ V. Description of the invention () Storage capacity , And increase the reliability of the capacitor to avoid the capacitor from being affected by impurities {such as alpha particles) when reading data, resulting in soft errors, or the "refresh" frequency of the capacitor, and so on. In order to solve the above problems, in the manufacture of capacitors, efforts are often made in the direction of increasing the surface area of the capacitor, and thus trench-type capacitors and crown-type capacitors have been gradually developed. Recently, hemispherica grains have been formed on the bottom electrode surface of the capacitor in order to further improve the storage capacity of the capacitor. Generally speaking, the typical multi-finger capacitor manufacturing process is shown in the first figure. First, a single-crystal silicon substrate 12 is provided, and a field oxide region 11 is formed on the semiconductor substrate 12 as a component insulation. use. Next, word lines 13 and sidewall spacers 14 on the sidewalls of the word lines 13 are sequentially formed by conventional techniques, and then a drain / source doped region 15 is formed by ion implantation. . A dielectric layer 16 is then formed on the semiconductor substrate 12, and a barrier layer 22 is formed on the dielectric layer 16. Then, the barrier layer 22 and the dielectric layer 16 are etched to form a contact hole 17A for conducting the bottom electrode and a contact hole 17B for the conducting bit line (not shown). Subsequently, conventional technology is used to form conductive plugs 18A for conducting the bottom electrode and conductive plugs 18B for conducting the bit line, respectively. Printed by the Intellectual Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. -Nn ^ n. I-JH I.--ml — ^ ϋ ^^ 1 1 ^ 1 (Please read the precautions for back office first and fill in this page) Then please Referring to the second figure, a dielectric layer 25 is then formed on the barrier layer 22 and the conductive plugs 18A and 18B. Then, an opening 32 is formed on the dielectric layer 25 by an etching technique to expose the upper surface of the conductive plug 18A, and is used for the subsequent formation of the bottom electrode of the capacitor. Subsequently, as shown in the third figure, an amorphous silicon layer 41 is formed to cover the dielectric layer. The paper size is applicable to the Chinese National Standard (CNS) A4 grid (210X297 mm) 4 JS 8 Γ7 .. Λ7 Α7 Β7 Printed by the Wisdom Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economy V. Invention Description (25) and the upper surface of the conductive plug 18A. On the surface of the amorphous silicon layer 41, hemispherical grain (HSG) silicon crystals are formed to increase the surface area of the bottom electrode of the capacitor. It should be noted that the amorphous silicon layer 41 has a horizontal portion 42 on the upper surface of the dielectric layer 25. Then, as shown in the fourth figure, the horizontal portion 42 of the amorphous silicon layer 41 on the upper surface of the dielectric layer 25 is removed by a chemical mechanical honing (CMP) process, and then removed by an etching technique using a conventional technique. The dielectric layer 25 can thus obtain the bottom electrode 51 of the capacitor, and the surface of the bottom electrode 51 has the aforementioned hemispherical grain (.HSG) silicon crystal 61. Referring to the fifth figure, a thin dielectric layer 81 is formed on the upper surface of the semiconductor substrate 12 to cover the upper surfaces of the barrier layer 22 and the bottom electrode 51. A conductive layer 82 is formed on the upper surface of the thin dielectric layer 81 as a capacitor top electrode. However, as described above, when a chemical honing process is performed to remove the horizontal portion 42 of the amorphous silicon layer 41 located on the upper surface of the dielectric layer 25, as shown in the sixth figure, an extremely large number of contaminating particles 84 are often generated. And the pollution particles 84 tend to fall and collect in the crown structure of the capacitor, that is, the generated pollution particles 84 will fall on the surface of the amorphous silicon layer 41. In addition to the silicon particles produced during honing, the particles of the pulp added during the chemical mechanical honing process are also included, which causes great difficulties in the subsequent process of removing contaminated particles. In particular, in order to increase the surface area of the bottom electrode of the capacitor, the surface of the bottom electrode of the capacitor is as described above | It often has a hemispherical particle crystal surface, so that the slurry particles in the chemical honing process often trap in the gap of the hemisphere particle crystal. It is difficult to eliminate it, which reduces ---- ^ ------ ^ ------ tr ------ § ,. (Please read the precautions on the back before filling this page) This paper size is applicable to Zhonggu a home standard (CNS) A4 specification (210 X 297 mm) C 〇A7 B7 Printed by the employee consumer cooperative of the Zhithan Property Bureau of the Ministry of Economic Affairs 5. Description of the invention () Low subsequent formation of thin dielectric Reliability of layer 81. In order to avoid the above-mentioned problem of contaminating particles, as shown in the seventh figure, a photoresist layer 86 can also be formed on the semiconductor substrate 12 to cover the amorphous silicon as the bottom electrode of the capacitor. Layer 41, and is inserted into the crown structure formed by the amorphous silicon layer 41. Subsequently, a chemical honing process is performed on the photoresist layer 86 and the horizontal portion 42 of the amorphous silicon layer 41. Subsequently, it is removed again The photoresist layer 86 in the crown structure, that is, the light on the surface of the amorphous silicon layer 4 1 The resist layer 86 is removed. However, in the process of removing the photoresist layer 86 in the crown structure, it is still impossible to effectively prevent the pollution particles from falling into the crown structure, so that the removal of the photoresist layer is completed. After the procedure of 86, there will still be contaminated particles falling on the surface of the amorphous silicon layer 41. The invention and the invention: The purpose of the present invention is to provide a method for manufacturing integrated circuit capacitors. Another object of the present invention is to Provided is a method for manufacturing an integrated circuit capacitor capable of effectively removing contaminated particles generated in a chemical mechanical honing process. The method of the present invention includes the following steps. First, bit lines are sequentially formed on a semiconductor substrate and formed. An oxide layer is formed on the surface of the bit line and the semiconductor substrate. A nitride layer is formed on the oxide layer. Next, the oxide layer and the nitride layer are etched to form a contact hole on the semiconductor substrate and a conductive plug is formed. The contact hole is filled. Then, a borophosphosilicate glass (BPSG) is formed on the upper surface of the nitride layer and the conductive plug, and then the borophosphosilicate glass is etched to form --------- 4 ^- ---(Please read the back Items and then Complete this page) I11 ίΑ Shu * This paper applies China scale quasi-solid family Di (CNS) Α4 specification (2 Shu ΟΧ297 mm)
經濟部智慧財產局员工消费合作社印R 4 1 981 7 w A7 _B7___五、發明説明（） 開口於硼磷矽玻璃上且曝露該導電插塞之上表面。然後， 形成第一導電層以覆蓋該硼磷矽玻璃與該導電插塞之表 面，且形成光阻層於該第一導電層上，以塡滿該開口。接 著，進行化學機械硏磨程序以移除光阻層與第一導電層至 該硼磷政玻璃爲止。接著，使用由氫氧化錢（ammo uium hydroxide, NH4OH) ' 雙氧水（hydrogen peroxide, H202)、以及水溶液調配而成APM溶液來淸除在化學機械 硏磨程序中所產生之污染微粒。隨後，依序移除殘餘光阻 層與硼磷矽玻璃，並形成介電層於該第一導電層、該氮化 層之上表面，且形成第二導電層於該介電層之上表面。 圖式簡單說明： 藉由以下詳細之描述結合所附圖示，將可輕易的了 解上述內容及此項發明之諸多優點，其中： 第一圖爲半導體晶片之截面圖，顯示根據傳統技術 在半導體底材上定義電容器其接觸孔與形成導電插塞之 步驟； 第二圖爲半導體晶片之截面圖，顯示根據傳統技術 在半導體底材上形成第二介電層之步驟： 第三圖爲半導體晶片之截面圖，顯示根據傳統技術 在半導體底材上形成第一導電層之步驟； 第四圖爲半導體晶片之截面圖，顯示根據傳統技術 進行化學機械硏磨程序與形成電容器底部電極之步驟； 第五圖爲半導體晶片之截面圖，顯示根據傳統技術 (請先閱讀背面之注意事項再填寫本頁) 本紙浪尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） 經濟部智慧財產局®工消費合作社印製 4 19 817 , A7 ___B7 五、發明説明（） 形成第三介電層於半導體底材上之步驟； 第六圖爲半導體晶片之截面圖，顯示根據傳統技術 進行化學機械硏磨程序後產生之污染微粒； 第七圖爲半導體晶片之截面圖，顯示根據傳統技術 形成光阻層以降低進行化學機械硏磨程序之微粒污染； 第八圖爲半導體晶片之截面圖，顯示根據本發明在 半導體底材上定義電容器其接觸孔與形成導電插塞之步 驟： 第九圖爲半導體晶片之截面圖，顯示根據本發明在 半導體底材上形成第二介電層且定義電容器底部電極之 步驟； 第十圖爲半導體晶片之截面圖，顯示根據本發明在 半導體底材上形成第一導電層與光阻層之步驟； 第十一圖爲半導體晶片之截面圖，顯示根據本發明 進行化學機械硏磨程序與淸除污染微粒之步騾；+ 第十二圖爲半導體晶片之截面圖，顯示根據本發明 移除殘餘光阻層之步驟；及 第十三圖爲半導體晶片之截面圖，顯示根據本發明 形成第三介電層與第二導電層於半導體底材上之步驟。 發明詳細說明： 本發明提供一個新方法用以製造高密度動態隨機 存取記憶胞。其中，藉著使用APM水溶液來淸除在進行 化學機械硏磨製程中所產生之污染微粒，可以避免污染微 本紙張尺度適用中國國家橾準（CNS ) A4規格（2丨0X297公釐） f---------k------訂------妗 1 -** (請先閲讀背面之注意事項再填寫本頁) 87 _ A7 經濟部智慧財產局員工消費合作社印製Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs R 4 1 981 7 w A7 _B7___ V. Description of the invention () Open on borophosphosilicate glass and expose the upper surface of the conductive plug. Then, a first conductive layer is formed to cover the surfaces of the borophosphosilicate glass and the conductive plug, and a photoresist layer is formed on the first conductive layer to fill the opening. Next, a chemical mechanical honing process is performed to remove the photoresist layer and the first conductive layer up to the borophospho glass. Next, ammonium hydroxide (NH4OH), hydrogen peroxide (H202), and an aqueous solution were used to prepare an APM solution to remove contaminated particles generated during the chemical mechanical honing process. Subsequently, the residual photoresist layer and borophosphosilicate glass are sequentially removed, a dielectric layer is formed on the upper surface of the first conductive layer and the nitride layer, and a second conductive layer is formed on the upper surface of the dielectric layer. . Brief description of the drawings: The above-mentioned content and many advantages of this invention can be easily understood through the following detailed description combined with the attached drawings, where: The first figure is a cross-sectional view of a semiconductor wafer, showing the The steps of defining the capacitor's contact hole and forming a conductive plug on the substrate; the second figure is a cross-sectional view of a semiconductor wafer, showing the steps of forming a second dielectric layer on a semiconductor substrate according to conventional techniques: the third figure is a semiconductor wafer A cross-sectional view showing a step of forming a first conductive layer on a semiconductor substrate according to a conventional technique; a fourth diagram is a cross-sectional view of a semiconductor wafer showing a step of performing a chemical mechanical honing process and forming a capacitor bottom electrode according to a conventional technique; Figure 5 is a cross-sectional view of a semiconductor wafer, showing that according to traditional technology (please read the precautions on the back before filling out this page) The paper scale is applicable to the Chinese National Standard (CNS) Α4 specification (210 × 297 mm) Printed by the Consumer Cooperative 4 19 817, A7 ___B7 V. Description of the invention () Forming a third dielectric layer in half Steps on a conductor substrate; Figure 6 is a cross-sectional view of a semiconductor wafer, showing contaminated particles produced by a chemical mechanical honing process according to traditional technology; Figure 7 is a cross-sectional view of a semiconductor wafer, showing photoresist formation according to conventional technology Layer to reduce particle contamination during the CMP process; Figure 8 is a cross-sectional view of a semiconductor wafer, showing the steps for defining a capacitor's contact hole and forming a conductive plug on a semiconductor substrate according to the present invention: Figure 9 is a semiconductor A cross-sectional view of a wafer showing a step of forming a second dielectric layer on a semiconductor substrate and defining a capacitor bottom electrode according to the present invention; a tenth view is a cross-sectional view of a semiconductor wafer showing the formation of a first on the semiconductor substrate according to the present invention The steps of the conductive layer and the photoresist layer; Figure 11 is a cross-sectional view of a semiconductor wafer, showing the steps of performing chemical mechanical honing procedures and removing contaminated particles according to the present invention; + Figure 12 is a cross-sectional view of a semiconductor wafer , Showing a step of removing the residual photoresist layer according to the present invention; and FIG. 13 is a cross-sectional view of a semiconductor wafer A third step of displaying a second dielectric layer and a conductive layer formed on the semiconductor substrate according to the present invention. Detailed description of the invention: The present invention provides a new method for manufacturing high-density dynamic random access memory cells. Among them, by using the APM aqueous solution to eliminate the pollution particles generated in the chemical mechanical honing process, the pollution can be avoided. The micro paper size is applicable to the Chinese National Standard (CNS) A4 specification (2 丨 0X297 mm) f- -------- k ------ Order ------ 妗 1-** (Please read the notes on the back before filling out this page) 87 _ A7 Employee Consumption of Intellectual Property Bureau, Ministry of Economic Affairs Printed by a cooperative
五、發明説明（） 粒掉落至皇冠型電容器之底部電極上。如此可有效的提昇 所形成皇冠型電容器之良率，從而確保所生產之高密度動 態隨機存取記億胞之效能與操作壽命。有關本發明之詳細 說明如下所述。 請參照第八圖，在一較佳之具體實施例中，提供 一具<100>晶向之單晶矽底材112，且形成場氧化區域 111於該半導體底材112之上，以做爲元件間絕緣之用。 接著，以習知技術依序形成字語線（wordlines) 113、以 及位於字語線113側壁上之側壁間隙（sidewall spacers) 114，再以離子植入方式形成汲極/源極摻雜區 115。接著在該半導體底材112上形成第一介電層116, 其中該第一介電層116可以合適的氧化物之化學組合及 程序來形成。例如，該第一介電層116可以是使用化學氣 相沈積法所形成之二氧化矽，該化學氣相沈積法是以正矽 酸乙酯（TEOS)在溫度600至800 °C間且壓力約0.1至 lOtorr時形成，其中並加入硼、磷原子以增加第一介電 層116之流動性。接著，在該第一介電層116上形成形成 氮化層122，以做爲後續製程之蝕刻阻障層。隨後，對該 第一介電層11 6與氮化層12 2進行蝕刻製程，以曝露該半 導體底材112之上表面且分別形成導通底部電極之第一 接觸孔117A與導通位元線（未顯示於圖中）之第二接觸孔 1 1 7B。在一最佳實施例中’該蝕刻程序是以電漿蝕刻術 來完成，且用來去除二氧化矽之蝕刻劑爲CC12F2、 CHF3/CF4 ' CHF" 〇2、CH3CHF2、CF4/〇2，氮化矽貝IJ ^ .¾.ITI (請先閲讀背面之注意事項再填寫本頁〕 本紙張尺度適用中國國家標率（CNS ) A4规格（2t〇X297公釐> 7 7 經濟部智慧財產局異工消費合作社印製 A7 _ B7 五、發明説明（） 藉由cf4/h2、 chf3或（^3〇^^2去除。隨後，使用傳 統技術分別形成導通底部電極之第一導電插塞 (plugs) 1 18A與導通位元線之第二導電插塞118B。其中 該第一導電插塞118A與第二導電插塞118B所使用之材 料可選擇摻雜多晶矽（doped polysilicon)或是同步摻雜 多晶砂（in-situ doped poly silicon)，此外如銘 '銅、鎢、 白金或鈦等金屬亦可做爲第一導電插塞11 8A與第二導電 插塞1 1 8B之材料。 接著請參照第九圖，形成第二介電層125於阻障層 122之上。其中該第二介電層125可使用硼磷矽玻璃 (borophosphosilicate, BPSG}來力口以形成。隨後，對第 二介電層125進行蝕刻程序，以曝露第一導電插塞11 8A 之上表面，並形成開口 132於第二介電層125上，並做 爲後續形成電容底部電極之用。隨後如第十圖所示，形成 第一導電層141以覆蓋第二介電層125以及導電插塞 118A之上表面。其中，在一較佳實施例中，該第一導電 層141可爲一非晶砂層（amorphous silicon)141。並且 在該非晶矽層141之表面，形成半球狀顆粒（HSG)矽結 晶161以增加電容底部電極之表面積。其中値得注意的 是該第一導電層141具有位於第二介電層125上表面之 水平部份142。接著形成一光阻層186以覆蓋於該第一 導電層141之上表面，且塡入開口 132中。 接著如第十一圖所示，使用化學機械硏磨（CMP)程 序移除光阻層186，且同時移除該第一導電層141位於 本紙張尺度適用中國國家標準（CNS)八4規格（210X297公釐） I—r-------------^------^ 1 (請先閲讀背面之注意事項再填寫本頁} 經濟部智慧財產局S工消費合作社印製 4 ,㈣7 、 A7 B7___五、發明説明（） 第二介電層125上表面之水平部份142,其中該移除程 序是以該第二介電層125之上表面作爲停止層。隨後， 使用APM溶液來淸除位於該光阻層186、第二介電層 125、以及第一導電層141上表面之污染微粒以及殘留 硏漿粒子。其中所使用之APM溶液在一較佳實施例中， 可使用 14%的氫氧化錢（ammouium hydroxide， NH4OH)、14% 的雙氧水（hydrogen peroxide, H2O2)、 以及72%水溶液加以調配而成。如此可有效的淸除在化 學機械硏磨製程中所產生之污染微粒。 接著，如第十二圖所示，再使用習知蝕刻技術移除 位於開□ 132中之殘餘光阻層186。然後，對第二介電 層125進行回蝕程序，其中該回蝕程序是以上述阻障層 122作爲蝕刻停止層。在一較佳實施例中，可使用稀釋之 HF溶液、BOE(阻障氧化層蝕刻）溶液或其他類似的溶液 將殘留之氧化層移除。如此可得到電容器之底部電極 151，且該底部電極151之表面具有上述之半球狀顆粒 (HSG)矽結晶161。 接著請參照第十三圖，在於該半導體底材112之上 表面形成一薄介電層181以覆蓋該阻障層122與底部電 極151之上表面。一般而言，此薄介電層181可以利用 Ν/0、0/Ν/0之複合薄膜或是利用高介電値之薄膜如 Ta2〇5、BST、PZT、PLZT等加以形成。然後，再於該 薄介電層181之上表面形成導電層182以作爲電容器之 頂部電極。至於該導電層1 82則可以化學氣相沈積法所 ---^---^----^------訂------^ I (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國圏家標準（CMS > A4规格（210X297公釐） 4 19 817 A7 B7 _五、發明説明（） 形成之多晶矽層來構成，例如可使用摻雜多晶矽（doped polysiliconj或是同步撥雜多晶砍（in-situ doped poly silicon)，此外如銘、銅、鶴、白金或駄等金屬亦可 做爲導電層182之材料。 本發明具有超越先前技術之優點。藉著運用APM溶 液來淸除在進行化學機械硏磨製程中所產生之污染微粒 與硏漿粒子，可有效避免污染微粒在後續製程中掉入底部 電極所形成之皇冠型結構，並陷入半球狀顆粒矽結晶之縫 隙中。進而提昇後續形成薄介電層之良率，並有效避免所 製造之皇冠型電容產生缺陷。如此不但可以提高電容器之 使用壽命，更可在電容器尺寸日趨縮小的同時，確保所生 產之電容依舊具有極佳之效能。 本發明雖以一較佳實例闡明如上|然其並非用以限 定本發明精神與發明實體，僅止於此一實施例爾。對熟悉 此領域技藝者，在不脫離本發明之精神與範圍內所作之修 改，均應包含在下述之申請專利範圍內》 I n ^— <* (請先閲讀背面之注^^項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4洗格（210X297公釐}5. Description of the invention () The particles fall to the bottom electrode of the crown capacitor. This can effectively improve the yield of the crown-type capacitors formed, thereby ensuring the performance and operating life of the high-density dynamic random access memory cells. A detailed description of the present invention is as follows. Referring to FIG. 8, in a preferred embodiment, a single crystal silicon substrate 112 with a < 100 > crystal orientation is provided, and a field oxide region 111 is formed on the semiconductor substrate 112 as a Insulation between components. Next, word lines 113 and sidewall spacers 114 on the sidewalls of the word lines 113 are sequentially formed by conventional techniques, and then a drain / source doped region 115 is formed by ion implantation. . A first dielectric layer 116 is then formed on the semiconductor substrate 112, wherein the first dielectric layer 116 can be formed by a suitable chemical combination and procedure of an oxide. For example, the first dielectric layer 116 may be silicon dioxide formed using a chemical vapor deposition method. The chemical vapor deposition method is based on ethyl orthosilicate (TEOS) at a temperature of 600 to 800 ° C and a pressure of It is formed at about 0.1 to 10 Torr, and boron and phosphorus atoms are added to increase the fluidity of the first dielectric layer 116. Next, a nitride layer 122 is formed on the first dielectric layer 116 as an etching barrier layer in a subsequent process. Subsequently, an etching process is performed on the first dielectric layer 116 and the nitride layer 12 2 to expose the upper surface of the semiconductor substrate 112 and to form a first contact hole 117A and a conductive bit line (not shown) for conducting a bottom electrode, respectively. (Shown in the figure) the second contact hole 1 1 7B. In a preferred embodiment, 'the etching process is performed by plasma etching, and the etchant used to remove silicon dioxide is CC12F2, CHF3 / CF4' CHF " 〇2, CH3CHF2, CF4 / 〇2, nitrogen Chemical Silicon IJ ^ .¾.ITI (Please read the notes on the back before filling in this page) This paper size applies to China's National Standards (CNS) A4 specification (2t〇X297 mm > 7 7 Intellectual Property Bureau of the Ministry of Economic Affairs A7 _ B7 printed by different consumer cooperatives V. Description of the invention () Removed by cf4 / h2, chf3, or (^ 3〇 ^^ 2. Then, the first conductive plugs that connect the bottom electrodes are formed using conventional techniques. ) 1 18A and the second conductive plug 118B of the conducting bit line. The materials used for the first conductive plug 118A and the second conductive plug 118B can be doped polysilicon or synchronously doped polysilicon. Crystal sand (in-situ doped poly silicon). In addition, metals such as copper, tungsten, platinum, or titanium can also be used as the material of the first conductive plug 11 8A and the second conductive plug 1 1 8B. In the ninth figure, a second dielectric layer 125 is formed on the barrier layer 122. The dielectric layer 125 can be formed by using borophosphosilicate glass (BPSG). Subsequently, an etching process is performed on the second dielectric layer 125 to expose the upper surface of the first conductive plug 118A and form an opening. 132 is on the second dielectric layer 125 and is used for subsequent formation of the capacitor bottom electrode. As shown in the tenth figure, a first conductive layer 141 is formed to cover the second dielectric layer 125 and the conductive plug 118A. Surface. In a preferred embodiment, the first conductive layer 141 may be an amorphous silicon layer 141. On the surface of the amorphous silicon layer 141, hemispherical grain (HSG) silicon crystals 161 are formed. In order to increase the surface area of the bottom electrode of the capacitor, it should be noted that the first conductive layer 141 has a horizontal portion 142 located on the upper surface of the second dielectric layer 125. A photoresist layer 186 is formed to cover the first conductive layer. The upper surface of the layer 141 is inserted into the opening 132. Then, as shown in FIG. 11, the photoresist layer 186 is removed using a chemical mechanical honing (CMP) process, and the first conductive layer 141 is also removed. Paper size applies to China Standard (CNS) 8 4 specifications (210X297 mm) I—r ------------- ^ ------ ^ 1 (Please read the precautions on the back before filling in this page} Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 4, 47, A7, B7___ 5. Description of the invention () Horizontal part 142 on the upper surface of the second dielectric layer 125, wherein the removal process is based on the second dielectric The upper surface of the layer 125 serves as a stop layer. Subsequently, an APM solution is used to remove contaminated particles and residual paste particles on the upper surfaces of the photoresist layer 186, the second dielectric layer 125, and the first conductive layer 141. In a preferred embodiment, the APM solution used therein can be prepared by using 14% ammouium hydroxide (NH4OH), 14% hydrogen peroxide (H2O2), and 72% aqueous solution. This can effectively remove contaminated particles generated during the honing process of chemical machinery. Then, as shown in FIG. 12, the conventional photoetching technique is used to remove the residual photoresist layer 186 in the opening 132. Then, an etch-back process is performed on the second dielectric layer 125, wherein the etch-back process uses the above-mentioned barrier layer 122 as an etch stop layer. In a preferred embodiment, the residual oxide layer can be removed by using a diluted HF solution, a BOE (Barrier Oxide Layer Etching) solution or other similar solutions. In this way, the bottom electrode 151 of the capacitor can be obtained, and the surface of the bottom electrode 151 has the aforementioned hemispherical grain (HSG) silicon crystal 161. Referring to FIG. 13, a thin dielectric layer 181 is formed on the upper surface of the semiconductor substrate 112 to cover the upper surface of the barrier layer 122 and the bottom electrode 151. Generally speaking, the thin dielectric layer 181 can be formed by using a composite film of N / 0, 0 / N / 0, or a film of a high dielectric film such as Ta205, BST, PZT, PLZT, and the like. Then, a conductive layer 182 is formed on the upper surface of the thin dielectric layer 181 as a top electrode of the capacitor. As for the conductive layer 182, you can use the chemical vapor deposition method --- ^ --- ^ ---- ^ ------ order ------ ^ I (Please read the precautions on the back first Please fill in this page again) This paper size is in accordance with Chinese standard (CMS > A4 specification (210X297mm) 4 19 817 A7 B7 _V. Description of the invention () Polycrystalline silicon layer formed, for example, doped polycrystalline silicon ( doped polysiliconj or in-situ doped poly silicon, in addition, metals such as Ming, copper, crane, platinum or rhenium can also be used as the material of the conductive layer 182. The present invention has advantages over the prior art By using APM solution to eliminate the pollution particles and slurry particles generated during the chemical mechanical honing process, it can effectively prevent the pollution particles from falling into the crown-shaped structure formed by the bottom electrode in the subsequent process and falling into the hemisphere. In the gap between the grain-like silicon crystals. This further improves the yield of subsequent thin dielectric layers and effectively avoids defects in the crown-type capacitors manufactured. This not only improves the life of the capacitor, but also reduces the size of the capacitor at the same time ,make sure The capacitor produced still has excellent performance. Although the present invention is explained as above with a preferred example, it is not intended to limit the spirit and the invention of the present invention, but only to this embodiment. For those skilled in the art, Modifications made without departing from the spirit and scope of the present invention should be included in the scope of the following patent applications "I n ^ — < * (Please read the note ^^ on the back before filling out this page) Wisdom of the Ministry of Economic Affairs The paper size printed by the Employees' Cooperative of the Property Bureau applies the Chinese National Standard (CNS) A4 Washing (210X297mm)