425704 A7 B7 啉_7日修4丨 ' % I > '補允| 五、發明説明（） 發明領域： 本發明與一種動態隨機存取記憶胞（DRAM cell)之半 導體製程有關’特別是一種具有皇冠型結構（crown)與垂直 纏狀結構（vertical fins)之電容其製作方法。 經濟部智慧財產局員工消費合作社印製 發明背景： 隨著半導體工業持續的進展，動態隨機存取記憶體 (DRAM)元件已廣泛的應用於積體亀路中。一般而言，動態 隨機存取記憶體（DRAM)具有許多記憶胞（memory cell)，且 其記憶胞通常由電容器與電晶體所構成，用以儲存一位元 (bit)之訊號。其中，電晶體之汲極或源極與電容之一端連 接，而電容之另一端則與參考電位連接，至於電晶體之另一 端及閘極則分別與位元線（bit line)及字語線（word line)連 接。因此在製造DRAM記憶胞時，往往也包含了電晶體與 電容器之製程，並藉著電容器與電晶體之源極區或汲極區之 電性接觸，將數位資訊儲存在電容器中，再藉由金氧半場效 電晶體（MOSFETs)、位元線（bit line)、字語線（word line)陣 列來存取電容器之數位資料》 然而，隨著超大型積體電路（ULSI)的發展，爲了符合 高密度積體電路之設計趨勢，動態隨機存取記憶胞（dram cell)之尺寸亦隨著降至次微米以下》而且由於元件不斷的縮 小，促使dram中電容的尺寸也隨之減少，故其儲存載子 (請先聞讀背面之注意事項再填寫本頁) 本紙浪尺度通用中國國家梯準（CNS ) A4規格（2I0X2?7公釐） 425704 Α7 Β7 五、發明説明（） (請先閲讀背面之注意事項再填寫本頁) 之性能亦相對降低。是以對動態隨機存取記憶體（dram)中 之記憶胞（memory cell)而言，所面臨的最大問題是如何在元 件尺寸趨向於縮小且積集度持續提高之情形下，提昇電容的 儲存能力，並增加電容的可靠度。 爲了解決上述之問題，在電容器的製造上，朝著增加 電容底部電極表面積之方向而努力，並由此健續發展出溝渠 式電容與堆疊式電容。其中除了利用高介電値薄膜作爲電容 器介電層外，更藉著形成如皇冠型結構、鰭狀結構、開展結 構（spread)、圓柱結構（cylinder)等底部電極，以便在有限的 空間中提供較佳的導電性與電荷儲存能力。然而，隨著半導 體工業所設計之記憶體儲存容量增加爲256 Μ位元至1 G位 元，傳統製程中所製造之電容結構往往無法提供足夠有效的 儲存能力。特別是如同上述，隨著半導體元件積集度的持續 提昇，元件所佔據之空間愈趨狹窄，且所製造元件之尺寸愈 趨縮小。在此種情形下，使用傳統半導體製程所提供之方 法，來定義電容器底部電極之圖案時，往往會受制於微影技 術之解析度，而無法在有限的空間中形成所需的鰭狀結構、 開展結構等圖案。如此一來，往往導致所製造電容器其良率 與儲存能力大幅降低》 經濟部智毪財產局員工消費合作社印製 發明目的及槪沭= 本發明之目的爲一種可增加電容底部電極表面積之 本紙張又度逍用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部智慧財產局員工消资合作社印製 4257 04 f 辟.i::: a? '；：. _____Β7_1 ?iv]/Oj 五、發明説明（） 積體電路電容製造方法。 本發明之再一目的爲一種使用半球狀矽晶粒來定義 底部電極其垂直鰭狀結構之積體電路電容製造方法。 本發明提供一種積體電路電容之製作方法，該方法包 含了下列步驟。首先，形成氧化矽層於一半導體底材上，且 形成氮化矽層於該氧化矽層上。接著，微影蝕刻氧化矽層與 氮化矽層，以形成一接觸孔於氧化矽層與氮化矽層上，且曝 露出部份半導體底材之上表面。再形成第一導電層於氮化矽 層上表面且塡充於接觸孔之中然後，回蝕刻第一導電層， 直至抵達氮化矽層上表面爲止，以形成導電插塞於接觸孔 中。接著，形成一介電層於氮化矽層與導電插塞之上表面， 且微影蝕刻該介電層以形成一開口於介電層上，並曝露出導 電插塞與部份氮化矽層之上表面，用以定義皇冠型圖案。再 形成複數個半球狀政晶粒（rugged poly silicon)於介電層上表 面與開口側壁上，且形成於導電插塞與氮化矽層之上表面， 其中兩個相鄰半球狀矽晶粒間之距離S 1 500埃。以半球狀 矽晶粒作爲蝕刻罩冪，蝕刻介電層以形成複數個洞穴於介電 層上表面，且形成第二導電層於介電層、氮化矽層與導電插 塞之表面，以覆蓋複數個半球狀矽晶粒，並塡充於複數個洞 穴中以形成複數個籍狀結構（fin shaped structure)，其中該 複數個鰭狀結構之寬度約$1500埃。然後，移除位於介電 層上之部份半球狀矽晶粒與部份第二導電層，以定義該電容 本紙張尺度速用t國國家搮準（CNS ) Α4規格（210Χ297公釐） ^ ,1τ^ I - (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 425 7 04 豹"丨/7:.:.:. _ __ _ ；； 五、發明説明（） _——^ 之底部電極。在移除殘餘之介電層後，形成電容介電層於第 二導電層、半球狀矽晶粒與氮化矽層之表面上，且形成第三 導電層於電容介電層之表面以作爲電容之頂部電極。 其中値得注意的是該電容底部電極之結構包括了第 一水平柱狀物，經由導電插塞電性連結至半導體底材；且兩 個垂直柱狀物，分別連接於第一水平柱狀物之兩端，並自第 一水平柱狀物之兩端向上延伸；另外，兩個第二水平柱狀 物，分別連接於雨個垂直柱狀物之頂端，且自兩個垂直柱狀 物之頂端向外延伸；並且複數個垂直鰭狀結構，分別連接於 兩個第二水平柱狀物之下表面，且自兩個第二水平柱狀物之 下表面向下延伸。値得注意的是上述第一水平柱狀物與兩個 垂直柱狀物構成了皇冠型結構（crown shaped structure)，而 兩個第二水平柱狀物則自該皇冠型結構上方向外延伸，且上 述垂直鰭狀結構則連接於第二水平柱狀物之下表面。 齓式簡單說明上 藉由以下詳細之描述結合所附圖示’將可輕易的了解 上述內容及此項發明之諸多優點’其中： 第一圖爲半導體晶片之截面圖，顯示根據傳統技術在 底材上形成所需各式元件之步驟； 第二圖爲半導體晶片之截面圖，顯示根據本發明在底 材上形成介電層與半球狀矽晶粒之步驟： 本紙張尺度通用中國圃家捸準（CNS ) A4规格< 2丨〇X297公兼> ----------^------1T------^ (请先聞讀背面之注意ί項再填寫本頁) 4 25 7 04 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（〉 第三圖爲半導體晶片之截面圖，顯示根據本發明使用 半球狀矽晶粒作爲罩冪蝕刻該介電層之步驟； 第四圖爲半導體晶片之截面圖，顯示根據本發明形成 第一導電層於該半球狀矽晶粒上且塡充於微細洞穴中之步 驟； 第五圖爲半導體晶片之截面圖 > 顯示根據本發明蝕刻 部份半球狀矽晶粒與部份第一導電層以定義電容器底部電 極之步驟； 第六圖爲半導體晶片之截面圖，顯示根據本發明形成 電容介電層與電容器頂部電極之步驟；及 第七圖爲半導體晶片之截面圖，顯示根據本發明所形 成電容器之結構圖。 發明詳細說明= 本發明所揭示爲一種在半導體底材上製造電容器之 方法。藉著利用不連續之半球狀矽晶粒來定義底部電極其垂 直指狀結構，可大幅提昇所製造底部電極之表面積，以提高 所生產電容器之儲存能力。並且使用不連續之半球狀矽晶粒 所製造垂直指狀結構其尺寸，遠小於傳統製程中使用微影蝕 刻技術所能達到之極限，是以藉著運用本發明所提供之方 法，可在整個電容器底部電極所佔之面積減小的情形下，仍 有效增加底部電極之表面積，並提高儲存電荷之能力。有關 本紙張尺度適用令國國家標準（CNS)A4規格（210x297公釐） ---------^---------^ (請先閱讀背面之注意事項再填寫本頁) 425704 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（） 本發明之詳細說明如下所述。 請參閱第一圖，提供一晶向爲< 1 0 0 >之單晶矽做爲 底材2，一場氧化區域4形成於底材2之上，其中該場氧化 區域4可以使用LOCOS或是其他相關之場氧化絕緣技術形 成於該底材2上，以做爲元件間絕緣之用。一般而言，可藉 由微影與蝕刻技術蝕刻氮化矽及氧化矽複合層，再以氧化製 程形成場氧化區域4於底材2上，完成後以熱磷酸去除殘餘 之氮化矽層，以氫氟酸去除氧化矽層，場氧化區域4之厚度 約爲3000-8000埃之間《接著，在底材2上形成氧化矽層6, 以做爲閘極氧化層，在一較佳之具體實施例中，該閘極氧化 層6是由在溫度約750至110 0°C之氧蒸氣環境中形成的氧 化矽所構成，且該閘極氧化層6之厚度大約是30-100埃。 仍請參閱第一圖，一多晶矽層8沈積於閘極氧化層6、及場 氧化層4上，以一實施例而言此多晶矽層8是以化學氣相沈 積法（CVD)形成，且厚度約在1〇〇〇至5000埃之間。接著以 習知技術形成字語線10、位元線丨2、具有保護層14之閘極 結構' 以及側壁間隙1 6，然後以離子植入方式形成摻雜區’ 由於上述製程並非本發明之重點，因此在此不加以詳述。 接著，如第一圖所示，一做爲絕緣層使用之氧化砂層 18形成於上述之閘極結構、場氧化層4、以及底材2之上。 以較佳實施例而言，該氧化矽層18爲利用正矽酸乙酯 (TE0S)形成厚度約爲埃之二氧化矽。然後，形 本紙張尺度適用+ 0國家標準（CNS)A4規格（210 X 297公釐） . Γ ^ ^ ^--------- (請先間讀背面之注意事項再填寫本頁) 4 25 7 0 4 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（） 成厚度約5 00至1500埃之氮化矽層20於上述氧化矽層18 之上，以做爲後續進行移除程序之停止層。接著，蝕刻氧化 矽層18與氮化矽層20以形成接觸孔22於底材2之上。其 中在一實施例中可藉著形成一光阻層於該氮化矽層20上， 以定義一區域作爲製造接觸孔22之用。至於該蝕刻程序則 可使用電漿蝕刻技術來進行，且其中用來去除二氧化矽之蝕 亥[J 劑爲 cci2f2、chf3/cf4、chf3/o2、ch3chf:、cf4/〇2 > 氮化矽則藉由CF4/H2、 CHF3或0113(：1^2去除。 請參照第二圖，在形成接觸孔22於底材2上後，接 著形成導電插塞24於該接觸孔22中。其中在一較佳實施例 中，可先沉積一摻雜多晶矽層（未顯示於圖中）於氮化矽層20 上表面且塡充於該接觸孔22中，接著再對該摻雜多晶矽層 進行回蝕刻程序直至抵達該氮化矽層20爲止，如此可以在 該接觸孔22中形成導電插塞24» —般而言，上述導電插塞 可以是摻雜多晶矽（doped poly silicon)或是同步摻雜多晶矽 (in-situ doped polysilicon)’此外如絕、銅、鶴、白金或舍太 等金靨亦可做爲上述導電插塞之材料。至於在上述回蝕刻多 晶矽以形成導電插塞24之步驟中，用來蝕刻多晶矽之蝕刻 劑則爲 SiCl4/Cl2、BCl3/Cl2、HBr/Cl2/〇2、ΗΒι702' Br2/ SF 6或SF〆 在形成導電插塞24後，接著形成介電層26於該氮化 矽層20與導電插塞24之上表面。一般而言，可以使用化學 本纸張尺度適用中國國家標準（CNS)A4規格（2〗0X 297公釐） I. V 裝--------訂---------線· (靖先閱讀背面之注意事項再填寫本頁) 425704 A7 Β7 五、發明說明（） 氣相沈積法（CVD)，以四乙基矽酸鹽（TEOS)在溫度約600至 800。C，壓力約0.1至ltorr間，形成厚度約5000至10000 埃之氧化矽層來作爲上述之介電層26。然後’如第二圖所 示，形成一開口於介電層26之上以定義出皇冠型圖案’且 曝露出導電插塞24與部份氮化矽層20之上表面。其中在一 較佳實施例中，可先形成一光阻層於該介電層26之上’再 藉著相關之微影製程定義圖案於光阻層上，接著使用該光阻 層作爲蝕刻罩幕，對介電層26進行蝕刻程序以形成皇冠型 圖案。其中用來蝕刻氧化矽之蝕刻劑可選擇CC1J2、 CHF,/CF, ' CHF3/02、CH3CHF,或 CF4/0:。 接著，形成複數個不連續之半球狀矽晶粒（discrete rugged poly)28於介電層26、氮化砂層20與導電插塞24之 表面上。在一較佳實施例中，該複數個半球狀砂晶粒28之 形成步驟首先爲沉積一非晶矽（amorPhous silicon)薄膜’再 形成矽晶種（nuclei)於該非晶矽薄膜上，例如可應用含砂的 氣體、如SiH4或Si2H6等來加以形成，其中製程之溫度約爲 53 0t至5 60°C之間、壓力約爲至托耳之間；接著 於高真空度的環境之下進行熱回火的製程’其溫度約爲530 °C至560°C之間、壓力則約爲至ΐπ9托耳之間。如此可 以得到如第二圖中所示不連續且分離之複數個半球狀砂晶 粒2 8。在一較佳實施例中，該複數個半球狀矽晶粒2 8具有 500至2 000埃之尺寸，且相鄰半球狀矽晶粒28間之距離約 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） J裝---- <請先閱讀背面之注意事項再填寫本頁) 訂· _ --線. 經濟部智慧財產局員工消費合作社印製 425704 A7 B7 細月曰 五、發明説明（） 修.士.丨揽充| 經濟部智慧財產局員工消費合作社印製 爲500至1500埃。425704 A7 B7 Porphyrin_7Day Repair 4 丨 '% I >' Supply Allowance | V. Description of the Invention () Field of the Invention: The present invention relates to a semiconductor process for a dynamic random access memory cell (DRAM cell). A capacitor having a crown structure and a vertical fins structure and a method for manufacturing the capacitor. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economics Background of the Invention: With the continuous progress of the semiconductor industry, dynamic random access memory (DRAM) components have been widely used in integrated circuits. Generally speaking, dynamic random access memory (DRAM) has many memory cells, and its memory cells are usually composed of capacitors and transistors to store a bit signal. The drain or source of the transistor is connected to one end of the capacitor, and the other end of the capacitor is connected to the reference potential. The other end of the transistor and the gate are connected to the bit line and the word line, respectively. (Word line) connection. Therefore, when manufacturing DRAM memory cells, the process of transistor and capacitor is often included, and the digital information is stored in the capacitor through the electrical contact between the capacitor and the source region or the drain region of the transistor. Metal Oxide Half-Field-Effect Transistors (MOSFETs), bit line, word line arrays to access digital data of capacitors "However, with the development of ultra large integrated circuits (ULSI), In line with the design trend of high-density integrated circuits, the size of dynamic random access memory cells (dram cells) has also fallen below submicron ", and due to the continuous shrinking of components, the size of capacitors in dram has also decreased, so Its storage carrier (please read the precautions on the back before filling out this page) The standard of this paper is General China National Standard (CNS) A4 (2I0X2? 7mm) 425704 Α7 Β7 V. Description of the invention () (please first Please read the notes on the back and fill in this page). For the memory cells in the dynamic random access memory (dram), the biggest problem is how to increase the storage capacity of the capacitor when the component size tends to shrink and the accumulation level continues to increase. Capacity and increase the reliability of the capacitor. In order to solve the above-mentioned problems, in the manufacture of capacitors, efforts are made to increase the surface area of the bottom electrode of the capacitor, and from this, trench-type capacitors and stacked capacitors have been developed steadily. In addition to using a high-dielectric rhenium film as the capacitor dielectric layer, bottom electrodes such as a crown structure, a fin structure, a spread structure, and a cylindrical structure are formed in order to provide in a limited space. Better conductivity and charge storage capacity. However, as the memory storage capacity designed by the semiconductor industry increases from 256 Mbits to 1 Gbits, the capacitor structure manufactured in the traditional process often cannot provide sufficient effective storage capacity. In particular, as mentioned above, as the degree of accumulation of semiconductor elements continues to increase, the space occupied by the elements becomes narrower, and the size of the manufactured elements becomes smaller. In this case, when the method provided by the traditional semiconductor manufacturing process is used to define the pattern of the bottom electrode of the capacitor, it is often restricted by the resolution of the lithography technology, and the required fin-like structure cannot be formed in a limited space. Carry out patterns such as structure. As a result, the yield and storage capacity of the capacitors produced are often greatly reduced. Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs and the purpose of the invention 槪 沭 = The purpose of the present invention is to increase the surface area of the bottom electrode of the capacitor. Again using the Chinese National Standard (CNS) A4 specification (210X297 mm) Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4257 04 f ..i ::: a? ';:. _____ Β7_1? Iv] / Oj 5 2. Description of the invention () Integrated circuit capacitor manufacturing method. Yet another object of the present invention is a method for manufacturing an integrated circuit capacitor using a hemispherical silicon crystal grain to define a vertical fin structure of a bottom electrode. The present invention provides a method for manufacturing an integrated circuit capacitor. The method includes the following steps. First, a silicon oxide layer is formed on a semiconductor substrate, and a silicon nitride layer is formed on the silicon oxide layer. Then, the lithography etches the silicon oxide layer and the silicon nitride layer to form a contact hole on the silicon oxide layer and the silicon nitride layer, and exposes a part of the upper surface of the semiconductor substrate. A first conductive layer is formed on the upper surface of the silicon nitride layer and filled in the contact hole. Then, the first conductive layer is etched back until it reaches the upper surface of the silicon nitride layer to form a conductive plug in the contact hole. Next, a dielectric layer is formed on the upper surface of the silicon nitride layer and the conductive plug, and the lithographic etching is performed on the dielectric layer to form an opening in the dielectric layer, and the conductive plug and a part of the silicon nitride are exposed. The top surface of the layer to define the crown pattern. Then a plurality of rugged poly silicon grains are formed on the upper surface of the dielectric layer and the opening sidewall, and are formed on the upper surface of the conductive plug and the silicon nitride layer, of which two adjacent hemisphere silicon grains The distance between S 1 500 Angstroms. Hemispherical silicon grains are used as an etching mask to etch the dielectric layer to form a plurality of holes on the upper surface of the dielectric layer, and to form a second conductive layer on the surface of the dielectric layer, the silicon nitride layer and the conductive plug, It covers a plurality of hemispherical silicon grains and fills a plurality of caves to form a plurality of fin shaped structures, wherein the width of the plurality of fin structures is about $ 1500 angstroms. Then, remove a part of the hemispherical silicon crystal grains and a part of the second conductive layer on the dielectric layer to define the capacitance of the paper. The national standard (CNS) A4 specification (210 × 297 mm) ^ , 1τ ^ I-(Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 425 7 04 Leopard " 丨 / 7:.:.:. _ __ _ ； Description of the invention () _—— ^ bottom electrode. After removing the remaining dielectric layer, a capacitor dielectric layer is formed on the surface of the second conductive layer, hemispherical silicon grains and silicon nitride layer, and a third conductive layer is formed on the surface of the capacitor dielectric layer as The top electrode of the capacitor. It should be noted that the structure of the bottom electrode of the capacitor includes a first horizontal pillar, which is electrically connected to the semiconductor substrate through a conductive plug; and two vertical pillars, which are respectively connected to the first horizontal pillar. The two horizontal pillars extend upward from the two ends of the first horizontal pillar; in addition, the two second horizontal pillars are respectively connected to the tops of the vertical pillars and from the two vertical pillars; The top ends extend outward; and a plurality of vertical fin structures are respectively connected to the lower surfaces of the two second horizontal pillars, and extend downward from the lower surfaces of the two second horizontal pillars. It should be noted that the first horizontal pillar and the two vertical pillars form a crown shaped structure, and the two second horizontal pillars extend outward from the crown structure. The vertical fin structure is connected to the lower surface of the second horizontal pillar. In the simple description of the formula, the following detailed description is combined with the accompanying diagrams, 'the above content and the many advantages of this invention will be easily understood'. The first figure is a cross-sectional view of a semiconductor wafer, showing The second step is a cross-sectional view of a semiconductor wafer, showing the steps for forming a dielectric layer and a hemispherical silicon grain on a substrate according to the present invention: This paper is a standard Chinese garden furniture. Standard (CNS) A4 Specifications < 2 丨 〇X297 公 兼 > ---------- ^ ------ 1T ------ ^ (Please read the note on the back first Please fill in this page again) 4 25 7 04 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (> The third figure is a cross-sectional view of a semiconductor wafer, showing the use of a hemispherical silicon die as a cover according to the present invention The step of power etching the dielectric layer; The fourth figure is a cross-sectional view of a semiconductor wafer, showing the steps of forming a first conductive layer on the hemispherical silicon grains and filling in a fine cavity according to the present invention; the fifth figure is Cross-sectional view of a semiconductor wafer > showing etching according to the present invention A step of defining a hemispherical silicon grain and a portion of a first conductive layer to define a capacitor bottom electrode; a sixth diagram is a cross-sectional view of a semiconductor wafer showing a step of forming a capacitor dielectric layer and a capacitor top electrode according to the present invention; and a seventh The figure is a cross-sectional view of a semiconductor wafer, showing the structure of a capacitor formed according to the present invention. Detailed description of the invention = The present invention discloses a method for manufacturing a capacitor on a semiconductor substrate. By using discontinuous hemispherical silicon crystal grains To define the vertical finger structure of the bottom electrode, the surface area of the manufactured bottom electrode can be greatly increased to improve the storage capacity of the capacitor. And the size of the vertical finger structure made of discontinuous hemispherical silicon grains is much smaller than The limit that can be reached by using the lithographic etching technology in the traditional process is that by using the method provided by the present invention, the surface area of the bottom electrode of the entire capacitor can be effectively increased while the area occupied by the bottom electrode of the capacitor is reduced. And improve the ability to store electric charges. The national standard (CNS) A4 applicable to this paper size Grid (210x297 mm) --------- ^ --------- ^ (Please read the precautions on the back before filling this page) 425704 A7 B7 Employee Consumer Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs Printing 5. Description of the invention () The detailed description of the present invention is as follows. Please refer to the first figure, and provide a single crystal silicon with a crystal orientation of < 1 0 0 > On the substrate 2, the field oxidation region 4 can be formed on the substrate 2 using LOCOS or other related field oxidation insulation technology for insulation between components. In general, micro- The photolithography and etching technology is used to etch the silicon nitride and silicon oxide composite layer, and then the field oxidation region 4 is formed on the substrate 2 by the oxidation process. After the completion, the residual silicon nitride layer is removed by hot phosphoric acid, and the silicon oxide layer is removed by hydrofluoric acid. The thickness of the field oxidation region 4 is about 3000-8000 angstroms. Then, a silicon oxide layer 6 is formed on the substrate 2 as a gate oxide layer. In a preferred embodiment, the gate oxide is Layer 6 is composed of silicon oxide formed in an oxygen vapor environment at a temperature of about 750 to 110 ° C, and the gate The thickness of layer 6 of about 30-100 Angstroms. Still referring to the first figure, a polycrystalline silicon layer 8 is deposited on the gate oxide layer 6 and the field oxide layer 4. According to an embodiment, the polycrystalline silicon layer 8 is formed by chemical vapor deposition (CVD) and has a thickness Between about 1000 and 5000 Angstroms. Next, the word line 10, the bit line 2 and the gate structure 14 with the protective layer 14 and the sidewall gap 16 are formed by conventional techniques, and then a doped region is formed by ion implantation. Because the above process is not the invention The important points are not described in detail here. Next, as shown in the first figure, an oxide sand layer 18 used as an insulating layer is formed on the gate structure, the field oxide layer 4, and the substrate 2 described above. In a preferred embodiment, the silicon oxide layer 18 is formed of silicon dioxide with a thickness of about 50 angstroms by using TEOS. Then, the size of the paper is applicable to the +0 National Standard (CNS) A4 specification (210 X 297 mm). Γ ^ ^ ^ --------- (Please read the precautions on the back before filling in this page ) 4 25 7 0 4 A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention () A silicon nitride layer 20 with a thickness of about 500 to 1500 angstroms is formed on the above silicon oxide layer 18 as Subsequent removal of the stop layer of the process. Next, the silicon oxide layer 18 and the silicon nitride layer 20 are etched to form a contact hole 22 on the substrate 2. In one embodiment, a region can be defined as a contact hole 22 by forming a photoresist layer on the silicon nitride layer 20. As for the etching process, plasma etching technology can be used to remove the silicon dioxide etch [J agent is cci2f2, chf3 / cf4, chf3 / o2, ch3chf :, cf4 / 〇2 > Nitriding Silicon is removed by CF4 / H2, CHF3 or 0113 (: 1 ^ 2. Please refer to the second figure. After forming the contact hole 22 on the substrate 2, a conductive plug 24 is formed in the contact hole 22. Among them, In a preferred embodiment, a doped polycrystalline silicon layer (not shown) may be deposited on the upper surface of the silicon nitride layer 20 and filled in the contact hole 22, and then the doped polycrystalline silicon layer is processed. The etch-back process is performed until the silicon nitride layer 20 is reached, so that a conductive plug 24 »can be formed in the contact hole 22. Generally, the conductive plug can be doped poly silicon or synchronously doped poly silicon. In-situ doped polysilicon 'In addition, gold, such as insulation, copper, crane, platinum, or Shetai can also be used as the material of the conductive plug. As for the step of etching back the polycrystalline silicon to form the conductive plug 24 , The etchant used to etch polycrystalline silicon is SiCl4 / Cl2, BCl3 / Cl 2. HBr / Cl2 / 〇2, ΗΒι702 'Br2 / SF 6 or SF〆 After forming the conductive plug 24, a dielectric layer 26 is then formed on the silicon nitride layer 20 and the upper surface of the conductive plug 24. Generally, In other words, it is possible to use the paper size of this chemistry to apply the Chinese National Standard (CNS) A4 specification (2〗 0X 297 mm) I. V. -------- Order --------- Line · (Jing first read the precautions on the back before filling this page) 425704 A7 B7 V. Description of the invention () Vapor deposition (CVD), using tetraethyl silicate (TEOS) at a temperature of about 600 to 800 ° C, pressure Between about 0.1 to ltorr, a silicon oxide layer having a thickness of about 5000 to 10,000 angstroms is formed as the above-mentioned dielectric layer 26. Then, as shown in the second figure, an opening is formed on the dielectric layer 26 to define a crown type Pattern 'and expose the upper surface of the conductive plug 24 and a portion of the silicon nitride layer 20. In a preferred embodiment, a photoresist layer may be formed on the dielectric layer 26 first, and then related by The lithography process defines a pattern on the photoresist layer, and then uses the photoresist layer as an etching mask to perform an etching process on the dielectric layer 26 to form a crown-shaped pattern. The etching agent for silicon oxide can be selected from CC1J2, CHF, / CF, 'CHF3 / 02, CH3CHF, or CF4 / 0 :. Then, a plurality of discontinuous discrete rugged poly 28 silicon dielectrics are formed in the dielectric. Layer 26, nitrided sand layer 20 and conductive plug 24. In a preferred embodiment, the step of forming the plurality of hemispherical sand grains 28 is to deposit an amorPhous silicon film A silicon seed (nuclei) is formed on the amorphous silicon thin film. For example, a sand-containing gas such as SiH4 or Si2H6 can be used to form the silicon seed. The process temperature is about 53 0 to 5 60 ° C and the pressure is about To Torr; followed by thermal tempering in a high vacuum environment, the temperature is about 530 ° C to 560 ° C, and the pressure is about 约为 π9 Torr. In this way, a plurality of discontinuous and separated sand crystal grains 28 as shown in the second figure can be obtained. In a preferred embodiment, the plurality of hemispherical silicon crystal grains 28 have a size of 500 to 2 000 Angstroms, and the distance between adjacent hemispherical silicon crystal grains 28 is about this paper size and the Chinese National Standard (CNS) is applied. A4 size (210 X 297 mm) J Pack ---- < Please read the precautions on the back before filling this page) Order _ --line. Printed by the Intellectual Property Bureau Staff Consumer Cooperatives of the Ministry of Economy 425704 A7 B7 Fine The fifth month of the invention, description of invention () Xiu Shi. 丨 Lan Chong | Intellectual Property Bureau of the Ministry of Economic Affairs, the consumer cooperatives printed 500 to 1500 Angstroms.
然後，請參照第三圖，使用所形成之半球狀矽晶粒28 作爲蝕刻罩冪，對介電層26進行蝕刻程序，以形成複數個洞 穴（cavity)29於介電層26之上表面。在一較佳實施例中，可 使用反應離子餓刻程序（reactive ion etching method, RIE) 來對介電層26進行蝕刻程序。其中用來蝕刻'介電層26之蝕刻 劑爲 CH、CHl/CF.、CHF./CL 接著，如第四圖所示，形成第一導電層3 0於該半導 體底材2之上，以覆蓋上述半球狀矽晶粒28，且塡充於複 數個洞穴29中。其中塡充於該複數個洞穴29中之第一導電 層30可形成複數個垂直鰭狀結構（fin shaped structure)，且 該垂直鰭狀結構具有500至15 00埃之寬度，而兩個相鄰垂 直鰭狀結構間之距離約爲500至2000埃。在一較佳實施例 中’可在溫度540~5 80°C之環境下，形成同步摻雜多晶矽層 來作爲上述第一導電層30。此外，如鋁、銅、鎢、白金或 鈦等金屬亦可做爲導電層之材料。然後，形成一光阻層32 於該第一導電層30之表面上，以定義後續所形成電容器其 底部電極之圖案> 請參照第五圖，在形成摻雜多晶矽層來作爲第一導電 層30之後，再使用該光阻層32作爲罩冪> 對第一導電層 3〇與半球狀矽晶粒28進行移除程序》其中可使用反應離子 蝕刻術（RIE)對未被光阻層32所遮蔽之第一導電層30與半 本紙張尺度適用中國國家棣準（CNS ) A4规格（210X297公釐） 1 ! ί !「.I I I n n I n n ] I n 線 {請先閲讀背面之注意事項再填寫本頁) CF ./0 CH CHF 3 /1.25 7 Ο Α7 Β7 ；^ι/ -7；;；, 經濟部智慧財產局員工消費合作社印¾ 五、發明説明（ 球狀矽晶粒28進行蝕刻程序，且使用介電層26作爲蝕刻程 序之停止層，如此可定義出電容器底部電極圖案·' 請參照第六圖，在移除光阻層32後，接著移除介電 層26·' —般而言，可使用濕蝕刻程序對介電層26進行蝕刻， 且藉著利用氮化矽層20作爲蝕刻停止層，以有效淸除介電 層26。一般而言，可使用HF溶液、BOE (緩衝氧化層蝕刻） 溶液或其他類似的溶液將介電層26移除》如此可以得到由 半球狀矽晶粒28與第一導電層3〇所構成之底部電極結 構。 然後，沿著上述底部電極結構之表面形成一薄電容介 電層33。一般而言，此電容介電層33可以利用高介電値之 薄膜如Ta 2 0 5 、 BST、 PZT、 PLZT等力D以形成。然後，在該 電容介電層33表面上形成第二導電層34,以作爲電容之頂 部電極。該第二導電層34之材料可選擇摻雜多晶矽（doped polysilicon)或是同步撥雜多晶砍（in-situ doped polysilicon)，此外如鋁、銅、鎢、白金或鈦等金屬亦可做爲 上述第二導電層之材料。 請參照第七圖，該圖所顯示爲使用本發明所提供方法 製造之電容器其截面結構圖。其中該電容器之底部電極包括 第一水平柱狀物36，且該第一水平柱狀物36經由導電插塞 24電性連結至半導體底材2;並且兩個垂直柱狀物38分別自 該第一水平柱狀物36之兩端向上延伸；另外，兩個第二水平 本紙張尺度適用中國囷家揉準（CNS ) A4说格（210X297公釐） ----„--------^------ΐτ------0 (請先閲讀背面之注意事項再填寫本頁) 1$ 1$ 補/c>」 d257 04 A7 B7 五、發明説明（） 柱狀物40分別自上述兩個垂直柱狀物3 8之頂端向外延伸； 複數個垂直鰭狀結構（fin shaped structure)42自該第二水平 柱狀物40之下表面向下延伸。 値得注意的是上述第一水平柱狀物3 6、垂直柱狀物38 與第二水平柱狀物4〇皆是由複數個拱門結構連結所構成， 其中每一個拱門結構皆包括了一半球狀矽晶粒28與包覆於 該半球狀矽晶粒28上表面之第一導電層30,並且上述垂直 鰭狀結構42連接於第二水平柱狀物40上任兩個相鄰拱門 結構其接點之下表面。其中在一較佳實施例中，上述垂直鰭 狀結構具有5 00至15 00埃之寬度，且兩個相鄰垂直鰭狀結 構間之距離約爲500至2000埃。 另外，該第一水平柱狀物30與第二水平柱狀物40皆 具有由拱門結構所構成不平坦（uneven)之上表面；而上述兩 垂直柱狀物之內側表面（即彼此面對之表面）亦由於拱門結 構而產生不平坦之表面。並且上述兩垂直柱狀物38自該第 一水平柱狀物36之兩端向上沿伸，而構成一皇冠型結構 (c r 〇 w n s h a p e d s t r u c t u r e〉。此外，一電容介電層3 3形成於 上述底部電極之表面上，並且一頂部電極34形成於該電容 介電層33上表面。 本發明相較於先前技術具有極大的優點。其中藉著使 用不遲續之半球狀矽晶粒來定義洞穴，再形成導電層以塡充 於洞穴中，可定義出垂直鰭狀結構以增加電容器底部電極的 本紙張尺度逍用中國國家橾準（CNS ) A4規格（210X297公釐） 1 ϋ t— 装 1訂 線 (請先W读背面之注意事項再填寫本頁) 經濟部智慧財產局貝工消費合作社印製 Z1257 0 ^ A7 B7 修 五、發明説明（） I 補元丨 表面積。並且使用不連續之半球狀矽晶粒所製造垂直鰭狀結 構其尺寸，遠小於傳統製程中使用微影蝕刻技術所能達到之 極限。是以對於元件尺寸持續縮小之電容器而言，藉著使用 本發明所提供之方法，仍可有效的定義出電容器底部電極之 圖案。並且如同上述，第一水平柱狀物'垂直柱狀物、第二 水平柱狀物均由複數個拱門結構所構成，是.以由拱門結構所 造成不平坦之表面將可大幅提昇底部電極之表面積，且有效 提昇電容之儲存能力。 本發明雖以一較佳實例闉明如上，然其並非用以限定 本發明精神與發明實體，僅止於此一實施例爾。對熟悉此領 域技藝者，在不脫離本發明之精神與範圍內所作之修改，均 應包含在下述之申請專利範圍內。 {請先閲讀背面之注項再填寫本頁) r % 绖濟部智慧財產局員工消費合作社印製 本紙張尺度通用中國國家樣隼（CNS ) A4见格（210X297公釐）Then, referring to the third figure, an etching process is performed on the dielectric layer 26 using the formed hemispherical silicon crystal grains 28 as an etching mask to form a plurality of cavities 29 on the upper surface of the dielectric layer 26. In a preferred embodiment, a reactive ion etching method (RIE) can be used to perform the etching process on the dielectric layer 26. The etchant used to etch the dielectric layer 26 is CH, CHl / CF., CHF./CL. Then, as shown in the fourth figure, a first conductive layer 30 is formed on the semiconductor substrate 2 to The semi-spherical silicon crystal grains 28 are covered and filled in a plurality of caves 29. The first conductive layer 30 filled in the plurality of caves 29 can form a plurality of vertical fin structures, and the vertical fin structures have a width of 500 to 1 500 Angstroms, and two adjacent The distance between the vertical fin structures is about 500 to 2000 angstroms. In a preferred embodiment, a synchronously doped polycrystalline silicon layer can be formed as the above-mentioned first conductive layer 30 under an environment of a temperature of 540 to 580 ° C. In addition, metals such as aluminum, copper, tungsten, platinum or titanium can be used as the material of the conductive layer. Then, a photoresist layer 32 is formed on the surface of the first conductive layer 30 to define the pattern of the bottom electrode of the capacitor to be formed later. Please refer to the fifth figure, and form a doped polycrystalline silicon layer as the first conductive layer. After 30, the photoresist layer 32 is used as a mask. ≫ The first conductive layer 30 and the hemispherical silicon crystal grains 28 are removed. The reactive ion etching (RIE) can be used to remove the non-photoresist layer. The first conductive layer shaded by 32 and the size of half the paper are applicable to China National Standards (CNS) A4 specifications (210X297 mm) 1! Ί! 「.III nn I nn] I n line {Please read the note on the back first Please fill in this page again for the matter) CF ./0 CH CHF 3 /1.25 7 〇 Α7 Β7; ^ ι / -7 ;;, printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Ⅴ 5. Description of the invention (Spherical silicon crystal grains 28 The etching process is performed, and the dielectric layer 26 is used as the stop layer of the etching process, so that the bottom electrode pattern of the capacitor can be defined. Please refer to the sixth figure, after removing the photoresist layer 32, then remove the dielectric layer 26. 'In general, the dielectric layer 26 can be etched using a wet etch process, By using the silicon nitride layer 20 as an etch stop layer, the dielectric layer 26 is effectively wiped out. Generally, the dielectric layer 26 can be moved using an HF solution, a BOE (buffered oxide etch) solution, or other similar solutions. In this way, a bottom electrode structure composed of hemispherical silicon crystal grains 28 and a first conductive layer 30 can be obtained. Then, a thin capacitor dielectric layer 33 is formed along the surface of the above bottom electrode structure. Generally speaking, this The capacitor dielectric layer 33 can be formed by using a high dielectric film such as Ta 2 0 5, BST, PZT, PLZT, etc. Then, a second conductive layer 34 is formed on the surface of the capacitor dielectric layer 33 as a result. The top electrode of the capacitor. The material of the second conductive layer 34 can be doped polysilicon or in-situ doped polysilicon, in addition to aluminum, copper, tungsten, platinum or titanium. Metal can also be used as the material of the above-mentioned second conductive layer. Please refer to the seventh figure, which is a cross-sectional structure diagram of a capacitor manufactured using the method provided by the present invention. The bottom electrode of the capacitor includes a first horizontal columnar shape. Thing 36, and the first horizontal pillar 36 is electrically connected to the semiconductor substrate 2 via the conductive plug 24; and two vertical pillars 38 extend upward from both ends of the first horizontal pillar 36, respectively; The two second-level paper standards are applicable to the Chinese standard of Chinese family (CNS) A4 (210X297 mm) ---- „-------- ^ ------ ΐτ --- --- 0 (please read the precautions on the back before filling this page) 1 $ 1 $ make up / c > ”d257 04 A7 B7 V. Description of the invention () The pillars 40 are from the above two vertical pillars 3 The top of 8 extends outward; a plurality of vertical fin shaped structures 42 extend downward from the lower surface of the second horizontal pillar 40. It should be noted that the above-mentioned first horizontal pillar 36, vertical pillar 38, and second horizontal pillar 40 are all composed of a plurality of arch structures, each of which includes a half ball The shaped silicon grains 28 are connected to the first conductive layer 30 covering the upper surface of the hemispherical silicon grains 28, and the vertical fin structure 42 is connected to any two adjacent arch structures on the second horizontal pillar 40. Click below the surface. In a preferred embodiment, the vertical fin structure has a width of 500 to 15 00 angstroms, and a distance between two adjacent vertical fin structures is about 500 to 2000 angstroms. In addition, the first horizontal pillar 30 and the second horizontal pillar 40 each have an uneven upper surface formed by an arch structure; and the inner surfaces of the two vertical pillars (that is, facing each other) Surface) also produces an uneven surface due to the arch structure. And the two vertical pillars 38 extend upward from both ends of the first horizontal pillar 36 to form a crown-shaped structure. In addition, a capacitor dielectric layer 33 is formed on the bottom electrode. On the surface, and a top electrode 34 is formed on the upper surface of the capacitor dielectric layer 33. The present invention has great advantages compared to the prior art. The cavity is defined by the use of non-continuous hemispherical silicon grains, and then A conductive layer is formed to fill the cave, and a vertical fin structure can be defined to increase the paper size of the bottom electrode of the capacitor. Use of China National Standard (CNS) A4 specification (210X297 mm) 1 ϋ t — binding 1 (Please read the precautions on the reverse side before filling out this page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, Z1257 0 ^ A7 B7 Revision 5. Description of the invention () I Supplementary element 丨 Surface area. And use discontinuous hemisphere The size of the vertical fin structure made by silicon grains is far smaller than the limit that can be achieved by lithographic etching technology in the traditional process. In other words, by using the method provided by the present invention, the pattern of the bottom electrode of the capacitor can still be effectively defined. And as mentioned above, the first horizontal pillars, the vertical pillars, and the second horizontal pillars are all composed of a plurality of The arch structure is formed. The uneven surface caused by the arch structure can greatly increase the surface area of the bottom electrode and effectively increase the storage capacity of the capacitor. Although the present invention is illustrated above with a preferred example, it is not It is used to define the spirit and the entity of the present invention, and it is limited to this embodiment. Modifications made by those skilled in the art without departing from the spirit and scope of the present invention should be included in the scope of patent application described below. . (Please read the note on the back before filling out this page) r% Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Paper Size Common Chinese National Sample (CNS) A4 (210X297 mm)