408491 3069twfl ,doc/002 ^ 87113971 A7 B7 五、發明‘說明（b ) 經濟部智慧財產局員工消費合作社印製 10、 20 ： 半導體基底 12、 23 ： 閘極氧化層 13 ： 鬧極 層 14、 29 ： 源/汲極區 22 ： 場氧 化層 24、 240 、340 :摻雜 多晶矽層 26、 260 :矽化鎢層 28 ' 48 ： 氮化矽層 30、 50 ： 間隙壁 32 ： 位元線的接觸窗 □ 34 ： 接點的接觸窗口 36 ： 第一 絕緣層 38 ' 40 ： 金屬鎢插塞 42 ： 第二 絕緣層 44 ： A-A-——- 弟一 接觸窗口 46 ： 金屬 鶴層 52 ： 位元 線 54 ： 第三 絕緣層 56 ： 光阻 58 ： 第四 接觸窗口 60 ： 下電 極 62 ： 介電 層 64 ： 上電 極 300 :多晶较插塞 (諳也閲讀背面之生意事項再填寫本頁) 修裝---- 訂----------緯 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 3069twf.doc/008 4i0849i A7 _B7__ 五、發明説明（·（） 本發明是有關於一種動態隨機存取記憶體（dynamic random access memory ;以下簡稱 DRAM)之電容（capacitor) {請先閱讀背面之注意事項再填寫本頁) 的製造方法，且特別是有關於一種以金屬鎢爲上下電極之 電容器的製造方法。 本發明利用形成金屬鎢插塞（tungsten PluS)以連接矽 基底之源極/汲極區，並以金屬鎢做爲電容器之上下電極° 其中，化學氣相沈積法（chemical vapor deposition;以下簡 稱CVD)所形成之下電極的金屬鎢層具有粗糙的表面，可以 增加表面積；此外，利用具有極佳之介電常數的五氧化二 钽做爲介電層，亦可有效增加電容量。 經濟部中央標準局員工消費合作社印製 DRAM是一廣泛使用的積體電路元件，尤其在今曰資 訊電子產業中更佔有不可或缺的地位。請參照第1圖，爲 一 DRAM元件的一記億單元之電路示意圖。如圖所示，一 個記憶單元是由一轉移電晶體T和一儲存電容C組成。轉 移電晶體T的源極（scnnxe)係連接到一對應的位元線（bit line ; BL)，汲極（drain)連接到一儲存電容C的一儲存電極 (storage electrode)6，而鬧極（gate)則連接到一對應的字元 線（word line ; WL)。儲存電容C的一相對電極（opposed electrode)8係連接到一固定電壓源，而在儲存電極6和相 對電極8之間則設置一介電層7。如熟習此藝者所知，儲 存電容C是用來儲存電子資料的，其應具有足夠大的電容 量，以避免資料的流失。 在傳統少於一百萬位元（1MB)的DRAM製程中，一般 多利用二度空間的電容元件來儲存資料，亦即泛稱的平坦 3 本紙張尺度適用中國國家;^準（CNS ) A4規格（210X297公釐） 3069twf,doc/008 6491 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（> ) 型電容(planar-type capacitor)。請參照第2圖，在一半導體 基底10上形成場氧化層11，以界定出主動區（active region);接著，依序形成閘極氧化層12、閘極層13、以及 源/汲極區I4，構成一轉移電晶體T ;之後，在半導體基底 10表面上鄰近汲極那側形成一介電層7及一導電層8，上 述二者與半導體基底10相連接的部分6便構成一儲存電容 C。很明顯地，平坦型電容需佔用基底一相當大的面積來 形成儲存電容C，以提供足夠的電容量，故並不適用於曰 益高度積集化之DRAM元件的製程要求。 通常，高度積集化的DHAM，例如大於4MB的儲存容 量者，需要利用三度空間的電容結構來實現，例如所謂的 堆疊狀（stack type)或溝槽型(trench type)電容元件。 請參照第3圖，爲習知疊層型電容結構的剖面.圖，在 一半導體基底10上依序形成場氧化層11，閘極氧化層12， 閘極層13，以及源/汲極區14，構成一轉移電晶體T。接 著，形成一絕緣層I5，並在源/汲極區Η之上蝕刻出接觸 窗口（contact opening)。然後依序在接觸窗口上形成一第二 多晶矽層6(當作儲存電極），一介電層7,以及一導電層8(當 作相對電極）。如此，便完成具疊層型電容C之動態隨機存 取記憶體的記憶單元，其可在元件尺寸縮小的情況下，仍 能提供足夠大的電容量，以確保元件性質。然而，當記憶、 元件再進入更高度的積集化時’例如製造64MB以上儲存 容量的DRAM，上述單純的疊層形電容結構已不符所需。 請參照第4圖’顯示習知溝槽型電容結構的剖面圖。 4 適用中國國家榡準(匚呢）八4规格（210父297公釐> (請先閲讀背面之注意事項再填窝本頁)408491 3069twfl, doc / 002 ^ 87113971 A7 B7 V. Description of the invention (b) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 10, 20: Semiconductor substrate 12, 23: Gate oxide layer 13: Alarm layer 14, 29 : Source / drain region 22: field oxide layers 24, 240, 340: doped polycrystalline silicon layer 26, 260: tungsten silicide layer 28 '48: silicon nitride layer 30, 50: spacer 32: contact window for bit lines □ 34: contact window 36 of the contact 36: first insulating layer 38 '40: metal tungsten plug 42: second insulating layer 44: AA ------ Yiyi contact window 46: metal crane layer 52: bit line 54 : The third insulating layer 56: the photoresist 58: the fourth contact window 60: the lower electrode 62: the dielectric layer 64: the upper electrode 300: the polycrystalline plug (also read the business matters on the back and fill in this page) ---- Order ---------- The dimensions of Weifang paper are applicable to China National Standard (CNS) A4 (210 X 297 mm) 3069twf.doc / 008 4i0849i A7 _B7__ V. Description of the invention (· ( The present invention is about one Manufacturing method of dynamic random access memory (hereinafter referred to as DRAM) capacitors (please read the precautions on the back before filling this page), and in particular relates to a method using metal tungsten as the upper and lower electrodes Capacitor manufacturing method. In the present invention, a metal tungsten plug (tungsten PluS) is formed to connect the source / drain region of a silicon substrate, and metal tungsten is used as the upper and lower electrodes of the capacitor. Among them, chemical vapor deposition (hereinafter referred to as CVD) The metal tungsten layer of the lower electrode has a rough surface and can increase the surface area. In addition, using tantalum pentoxide with an excellent dielectric constant as the dielectric layer can also effectively increase the capacitance. Printed by the Consumers' Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs, DRAM is a widely used integrated circuit element, which holds an indispensable position especially in the information electronics industry today. Please refer to Fig. 1, which is a circuit diagram of a DRAM cell with a hundred million cells. As shown, a memory cell is composed of a transfer transistor T and a storage capacitor C. The source (scnnxe) of the transfer transistor T is connected to a corresponding bit line (BL), the drain is connected to a storage electrode 6 of a storage capacitor C, and the alarm (Gate) is connected to a corresponding word line (WL). An opposed electrode 8 of the storage capacitor C is connected to a fixed voltage source, and a dielectric layer 7 is provided between the storage electrode 6 and the opposite electrode 8. As those skilled in the art know, the storage capacitor C is used to store electronic data, and it should have a sufficient capacitance to avoid data loss. In traditional DRAM processes with less than one million bits (1MB), two-dimensional capacitive elements are usually used to store data, which is generally referred to as flat. This paper size is applicable to China; ^ Standard (CNS) A4 specifications (210X297 mm) 3069twf, doc / 008 6491 A7 B7 Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of the invention (planar-type capacitor). Referring to FIG. 2, a field oxide layer 11 is formed on a semiconductor substrate 10 to define an active region. Then, a gate oxide layer 12, a gate layer 13, and a source / drain region are sequentially formed. I4 constitutes a transfer transistor T; thereafter, a dielectric layer 7 and a conductive layer 8 are formed on the surface of the semiconductor substrate 10 adjacent to the drain side, and the portion 6 connected to the semiconductor substrate 10 constitutes a storage. Capacitor C. Obviously, the flat capacitor needs to occupy a considerable area of the substrate to form the storage capacitor C to provide sufficient capacitance, so it is not suitable for the process requirements of DRAM devices with high accumulation. Generally, highly integrated DHAMs, such as those with a storage capacity greater than 4 MB, need to be implemented using a three-dimensional space capacitor structure, such as a so-called stack type or trench type capacitor element. Please refer to FIG. 3, which is a cross-section of a conventional stacked capacitor structure. In the figure, a field oxide layer 11, a gate oxide layer 12, a gate layer 13, and a source / drain region are sequentially formed on a semiconductor substrate 10. 14. Form a transfer transistor T. Next, an insulating layer I5 is formed, and a contact opening is etched over the source / drain region Η. Then, a second polycrystalline silicon layer 6 (as a storage electrode), a dielectric layer 7, and a conductive layer 8 (as a counter electrode) are sequentially formed on the contact window. In this way, a memory cell with a dynamic random access memory with a laminated capacitor C is completed, which can still provide a sufficiently large capacitance to ensure the properties of the component when the component size is reduced. However, when memories and components are further integrated, for example, if a DRAM with a storage capacity of 64 MB or more is manufactured, the above-mentioned simple multilayer capacitor structure is no longer required. Please refer to FIG. 4 ', which shows a cross-sectional view of a conventional trench capacitor structure. 4 Applicable to China National Standards (匚) 8 4 specifications (210 father 297 mm > (Please read the precautions on the back before filling in this page)
經濟部中央標準局員工消費合作社印裝 3069twf.doc/008 〇 8 4 9 文 _____Β7 _ 五、發明説明（今） 其先以一般程序在一半導體基底10上形成轉移電晶體Τ， 包括閘極氧化層12，閘極層13，及源/汲極區14 ;然後在 半導體基底10上鄰近汲極14那側蝕刻出一深溝槽，再於 該溝槽中形成儲存電容C，其包含由半導體基底側壁形成 的儲存電極6，介電層7，及一多晶矽層之相對電極8。此 種電容結構及製法雖可增加電極表面積以提高其電容量， 然而，由於蝕刻深構槽時不可避免地會造成半導體基底10 產生晶格缺陷（defects)，導致漏電流增加而影響元件性 質，並且隨著溝槽深寬比値（aspect ratio)的增大，其蝕刻 速率將遞減，不僅增加製程困難度也影響生產效率。 請參照第5圖，另一方面，在傳統製程上以形成多晶 矽層（polysilicon)340 與沈積半球型矽晶粒層 (hemispherical silicon grain ;以下簡稱 HSG)400 作爲電容 器之下電極，以增加其表面積，並採用氧化物/氮化物/氧 化物三層結構（oxide/nitride/oxide;以下簡稱ONO)500作 爲電容器之介電層。但是，當元件的設計法則（design rule) 小於m時，此結構很難達到25fF之電容要求。 因此’習知的DRAM之電容，面臨的問題爲： 1. 平坦型電容需佔用基底一相當大的面積來形成儲存 電容’以提供足夠的電容量，故並不適用於日益高度積集 化之DRAM元件的製程要求。 2. 電容欲大於4MB的儲存容量者，需要利用三度空間 的電容結構來實現，例如所謂的堆疊狀（stack type)或溝槽 型（trench type)電容元件。但是，當記憶元件再進入更高 5 本紙張錢適用士國國家樣2^ ( CNS > A4祕 ( 210χ297公瘦) ~ I ^ (請先閱讀背面之注意事項再填寫本頁)Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 3069twf.doc / 008 〇 8 4 9 Text _____ Β7 _ V. Description of the Invention (Today) It first uses a general procedure to form a transfer transistor T on a semiconductor substrate 10, including the gate An oxide layer 12, a gate layer 13, and a source / drain region 14; and then a deep trench is etched on the semiconductor substrate 10 side adjacent to the drain 14, and a storage capacitor C is formed in the trench, which includes a semiconductor A storage electrode 6, a dielectric layer 7, and a counter electrode 8 of a polycrystalline silicon layer are formed on the sidewall of the substrate. Although such a capacitor structure and manufacturing method can increase the surface area of the electrode to increase its capacitance, since the semiconductor substrate 10 will inevitably cause lattice defects during etching of the deep trenches, resulting in an increase in leakage current and affecting element properties, And as the aspect ratio of the trench increases, its etching rate will decrease, which not only increases the difficulty of the process but also affects the production efficiency. Please refer to FIG. 5. On the other hand, in the conventional process, a polysilicon 340 and a hemispherical silicon grain (HSG) 400 are formed as the lower electrode of the capacitor to increase its surface area. And adopts an oxide / nitride / oxide three-layer structure (oxide / nitride / oxide; hereinafter referred to as ONO) 500 as the dielectric layer of the capacitor. However, when the design rule of the component is less than m, this structure is difficult to meet the capacitance requirement of 25fF. Therefore, the problems of conventional DRAM capacitors are as follows: 1. Flat capacitors need to occupy a considerable area of the substrate to form storage capacitors to provide sufficient capacitance, so they are not suitable for increasingly highly integrated capacitors. Process requirements for DRAM components. 2. Capacitors with a storage capacity of more than 4MB need to be realized with a three-dimensional capacitor structure, such as a so-called stack type or trench type capacitor element. However, when the memory element enters a higher level, 5 papers are applicable to the country and country 2 ^ (CNS > A4 secret (210x297 male thin) ~ I ^ (Please read the precautions on the back before filling this page)
/ / 經濟部中央標準局員工消費合作社印製 3069twf.doc/008 408491 A7 B7 五、發明説明（α) 度的積集化時，例如製造64MB以上儲存容量的DRAM， 單純的疊層形電容結構已不符所需。 3. 習知溝槽型電容結構，雖可增加電極表面積以提高 其電容量。然而，由於飩刻深構槽時不可避免地會造成半 導體基底產生晶格缺陷，導致漏電流增加而影響元件性 質，並且隨著溝槽深寬比値的增大，其蝕刻速率將遞減， 不僅增加製程困難度也影響生產效率。 4. 另一方面，在傳統製程上以形成多晶矽層、HSG與 ΟΝΟ三層結構爲DRAM的電容主體。但是，當元件的設 計法則小於〇.25//m時，此結構很難達到25fF之電容要 求。 有鑑於此’本發明的主要目的在於提供一種DRAM之 電容的製造方法，以改善習知之元件的設計法則小於0.25 /z m時，電容結構很難達到25fF之要求的缺點。 爲達成上述和其它之目的，本發明提出一種DRAM電 容的製造方法，包括形成金屬鎢插塞以連接矽基底之源極 /汲極區，並以金屬鎢作爲電容器上下電極，且以五氧化二 钽做爲電容器之介電層的結構。 依照本發明之一較佳實施例，提出一種以金屬鎢作爲 電容器之上下電極，並以五氧化二鉅做爲電容器之介電 層，以取代習知以形成多晶矽層、HSG與ΟΝΟ三層結構 爲DRAM的電容主體，以降低電阻値，並避免漏電流。 其中，電容體的下電極，係先利用物理氣相沈積法形成一 金屬鎢層，再以化學氣相沈積法形成具有粗糙的表面之金 6 本紙張尺度逋用中國國家標準（CNS > A4規格（21〇X297公釐） (請先聞讀背面之注意事項再填寫本頁}// Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 3069twf.doc / 008 408491 A7 B7 V. Description of the invention (α) When the degree of accumulation is used, for example, a DRAM with a storage capacity of 64MB or more is used, and a simple stacked capacitor structure No longer required. 3. Although the trench capacitor structure is known, the surface area of the electrode can be increased to increase its capacitance. However, since etched deep trenches will inevitably cause lattice defects in the semiconductor substrate, leading to an increase in leakage current and affecting the properties of the device, and as the trench aspect ratio increases, the etching rate will decrease, not only Increasing process difficulty also affects production efficiency. 4. On the other hand, the three-layer structure of polycrystalline silicon layer, HSG and ONO is used as the main body of DRAM in the traditional process. However, when the design rule of the component is less than 0.25 // m, it is difficult for this structure to meet the capacitance requirement of 25fF. In view of this, the main purpose of the present invention is to provide a method for manufacturing a DRAM capacitor, in order to improve the disadvantage that the capacitor structure is difficult to achieve the requirement of 25fF when the design rule of a conventional device is less than 0.25 / z m. To achieve the above and other objectives, the present invention provides a method for manufacturing a DRAM capacitor, which includes forming a metal tungsten plug to connect a source / drain region of a silicon substrate, using metal tungsten as the upper and lower electrodes of the capacitor, and using pentoxide Tantalum is used as the structure of the dielectric layer of the capacitor. According to a preferred embodiment of the present invention, a metal tungsten is used as the upper and lower electrodes of the capacitor, and pentoxide is used as the dielectric layer of the capacitor, instead of the conventional method to form a polycrystalline silicon layer, HSG and ONO three-layer structure. It is the main body of the DRAM capacitor to reduce the resistance 値 and avoid leakage current. Among them, the lower electrode of the capacitor body is formed by a physical vapor deposition method using a metal tungsten layer, and then a chemical vapor deposition method is used to form gold with a rough surface. 6 This paper uses the Chinese national standard (CNS > A4). Specifications (21〇X297 mm) (Please read the notes on the back before filling in this page}
.JeT 3069twf.doc/008 ^ 408491 at B7 五、發明説明（ir) 屬鎢層，可以增加表面積，使電容量大爲提高。此外，利 用具有極佳之介電常數的五氧化二鉅做爲介電層，亦能有 效增加電容量。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1圖係一般DRAM中一記憶單兀的電路意圖； 第2圖係繪示一種習知具平坦型電容DRAM之剖面 圖； 第3圖係繪示一種習知具疊層型電容DRAM之剖面 圖； 第4圖係繪示一種習知具溝槽型電容DRAM之剖面 圖； 第5圖係繪示一種習知傳統製程上以形成多晶矽層 /HSG/ONO三層結構爲DRAM之電容的剖面圖；以及 第6A〜6L圖係繪示依照本發明之較佳實施例的一種 DRAM之電容的製造流程剖面圖。 圖示標記說明： T :轉移電晶體 C :儲存電容 6 :儲存電極 7 :介電層 8 :電極 7 (請先閲讀背面之注意事項再填寫本頁).JeT 3069twf.doc / 008 ^ 408491 at B7 V. Description of the Invention (ir) It is a tungsten layer, which can increase the surface area and greatly increase the capacitance. In addition, the use of pentoxide with an excellent dielectric constant as the dielectric layer can also effectively increase the capacitance. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: FIG. 1 Fig. 2 is a circuit diagram of a memory unit in general DRAM; Fig. 2 is a cross-sectional view of a conventional flat-type capacitor DRAM; Fig. 3 is a cross-sectional view of a conventional stacked-type capacitor DRAM; FIG. 4 is a cross-sectional view of a conventional trench DRAM capacitor; FIG. 5 is a cross-sectional view of a conventional conventional process for forming a polycrystalline silicon layer / HSG / ONO three-layer structure as a DRAM capacitor; and 6A to 6L are cross-sectional views illustrating a manufacturing process of a DRAM capacitor according to a preferred embodiment of the present invention. Description of pictographs: T: Transistor C: Storage capacitor 6: Storage electrode 7: Dielectric layer 8: Electrode 7 (Please read the precautions on the back before filling this page)
、1T 經濟部中央標準局員工消費合作社印製 本纸張尺度逍用中國國家標準（CNS ) Α·4規格（210X297公釐） 408491 3069twfl ,doc/002 ^ 87113971 A7 B7 五、發明‘說明（b ) 經濟部智慧財產局員工消費合作社印製 10、 20 ： 半導體基底 12、 23 ： 閘極氧化層 13 ： 鬧極 層 14、 29 ： 源/汲極區 22 ： 場氧 化層 24、 240 、340 :摻雜 多晶矽層 26、 260 :矽化鎢層 28 ' 48 ： 氮化矽層 30、 50 ： 間隙壁 32 ： 位元線的接觸窗 □ 34 ： 接點的接觸窗口 36 ： 第一 絕緣層 38 ' 40 ： 金屬鎢插塞 42 ： 第二 絕緣層 44 ： A-A-——- 弟一 接觸窗口 46 ： 金屬 鶴層 52 ： 位元 線 54 ： 第三 絕緣層 56 ： 光阻 58 ： 第四 接觸窗口 60 ： 下電 極 62 ： 介電 層 64 ： 上電 極 300 :多晶较插塞 (諳也閲讀背面之生意事項再填寫本頁) 修裝---- 訂----------緯 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 408491 3069twfl .doc/002 A7 B7_ 五、發明說明（G ) 400 :沈積半球型矽晶粒層 · 5〇〇:氧化物/氮化物/氧化物三層結構 實施例 ' (請先閲讀背面之注意事項再填寫本頁) 第6A〜6L圖係繪示依照本發明之較佳實施例的一種 DRAM之電容的製造流程剖面圖。 經濟部智慧財產局員工消費合作社印製 請參照第6A圖，於一半導體矽基底20上形成隔離結 構，比如用淺溝槽絕緣法定義出淺溝槽的位置，再用習知 的化學氣相沈積法（chemical vapor deposition;以下簡稱 CVD)將二氧化砂塡入淺溝槽中，形成場氧化層（field oxide) 22。在矽基底20和場氧化矽層22上方形成一閫極氧化物 層23，例如以熱氧化法形成，之後再於閘極氧化物層23 上形成第一導電層，比如依序沈積一層約1000人厚的摻 雜多晶矽層24、一層約1000 A厚的矽化鎢26和一層約 1500 A厚的氮化矽32。摻雜多晶矽層24和矽化鎢層26 形成第一導電層，氮化矽層28則形成一保護層。在氮化 矽層28上方塗佈一層光阻（圖上未繪示出來），經由習知 的微影製程定義出電晶體的閘極或連線（wire line)，再用 習知的蝕刻步驟蝕刻未被光阻保護的區域直到露出矽基 底10爲止。然後在上方沈積一氮化矽，並藉由非等向性 蝕刻，在電晶體閘極周緣形成間隙壁30的構造。另外， 在間隙壁30形成前，利用氮化矽層28保護閘極，而對 基底20表面進行離子植入法，遂在閘極側邊的基底20 表面形成一源/汲極區29。 請參照第6B圖，形成第一絕緣層36,比如用常壓CVD 沈積一層約2000人厚的二氧化矽和一層約7500 A厚的硼 磷矽玻璃（BPSG)層，二者構成第一絕緣層36。並且將基 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 ^08491 3069twfl ,doc/002 A7 ___B7_____ 五、發明說明（ί) 底結構置於約8〇〇°c的環境中，使硼磷矽玻璃層產生回流 (reflow)。再用化學機械研磨法（chemical mechanical polishing;以下簡稱CMP)或回蝕的方法將其表面平坦化， 接著蝕穿第一絕緣層36直至矽基底.20爲止，將源極、汲 極的接觸窗口 32、34定義出來。此時由於電晶體之閘極 有氮化矽層28及間隙壁30的保護，所以可利用乾蝕刻法 形成自動對準接觸窗口（self align contact ; SAC)的方法來 定義接觸窗口 32、34。 請參照第6C圖，再將金屬鎢塡入源極、汲極的接觸 窗口 32、34，連接多個接觸窗口中暴露出的源/汲極區， 包括位元線的接觸窗口 32和接點的接觸窗口 34，形成多 個金屬鎢插塞38、40，構成內金屬導線。接著用CMP或 鎢回蝕的方法，讓金屬鎢的表面和第一絕緣層36等高。 金屬鎢插塞38、40在此取代習知所用的摻雜多晶矽作爲 內導線，優點爲可以使得內導線的電阻下降，因而電晶體 的操作速度會增快。 請參照第6D圖，然後再沈積第二絕緣層42，例如用 常壓CVD沈積一層約2000 A厚的二氧化矽。再用習知的 微影蝕刻步驟，定義出和位在位元線的接觸窗口 32的金 屬鎢插塞38相同位置的第二接觸窗口 44。 請參照第6E圖，再於第二絕緣層42與第二接觸窗口 44上方形成一第二導電層，例如依序爲沈積一層約2000 A 厚的金屬鎢層46和一層約1 500 A厚的氮化矽48。金屬鎢 層46形成第二導電層，氮化矽層48則形成一保護層。然 後，經由習知的微影蝕刻步驟，蝕刻未被光阻（圖上未繪 示出來）保護的區域直到露出第二絕緣層42爲止，以定義 in 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公餐1 ^ 1·—-__________ ' (諳fc閲讀背面之生意事項再填寫φ頁) •^1 ^1 ^1 .1 訂·----^----線 3069twf.doc/008 408491 A7 B7 經濟部中央標準局員工消費合作社印袋 五、發明説明（1) 出位元線52。接著’在上方沈積一氮化矽，並藉由非等向 性蝕刻，在位元線52周緣形成間隙壁50的構造。 請參照第6F圖’形成第三絕緣層5 4，例如用常壓CVD 沈積先一層約2000 A厚的二氧化砂；然後，例如以高密 度電獎法（high density plasma ; HDP)，再沈積一層厚度約 爲16KA的氧化矽或其他氧化物，二者構成第三絕緣層 54。然後’以CMP使第三絕緣層54表面平坦化；接著， 上光阻56覆蓋特定區域之第三絕緣層54。 請參照第6G圖，蝕刻光阻W所暴露出的第三絕緣層 54,並進一步蝕刻第二絕緣層42,而形成第四接觸窗口 58 暴露出金屬鎢插塞40，然後去除光阻50。依照本發明之較 佳實施例的一種DRAM之電容的製造方法，由於位元線52 具有氮化矽層48及間隙壁5〇的保護，可使得此處的蝕刻 步驟可利用自行對準接觸窗口的方法進行蝕刻，避免蝕刻 步驟中對準失焦所產生的缺點。 請參照第6H圖，然後依照整個基底結構的形狀，例 如使用物理氣相沈積法(physical vapor deposition ;以下簡 稱PVD)，沈積一層厚度約爲300A的金屬鎢，覆蓋整個基 底結構；接著，再以CVD沈積一層厚度約爲500A的金屬 鎢，共同形成下電極60。其中，利用CVD所沈積之金屬 鎢，具有粗糙的表面，可以增加表面積，提高電容量。 請參照第61圖，然後，以CMP去除位於第三絕緣層 54上的下電極60之金屬鎢，直至暴露出第三絕緣層54的 表面。 (請先閱讀背面之注意事項再填寫本頁) ώ)· 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 3069twf.doc/008 U8491 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（A ) 請參照第6J圖，使用緩衝氧化鈾刻劑（BOE 2〇 : 1)， 進行約400〜600秒的蝕刻步驟，藉以去除第三絕緣層54。 請參照第6K圖，例如以快速加熱製程(rapid thermal processing; RTP)在850°C及充滿氨氣環境下作用120秒。 隨後，例如以沈積法，沈積r*層厚度約爲8〇A的五氧化二 鉅，覆蓋整個基底結構，做爲介電層62。而五氧化二鉅具 有極佳之介電常數，做爲介電層可以有效增加電容量。 請參照第6L圖，例如以RTP在850t及充滿氧氣環境 下作用60秒。然後，例如以PVD沈積一層厚度約爲500A 的金屬鎢，覆蓋整個基底結構，而形成電容之上電極64。 再以傳統的微影蝕刻法，以定義出如第6L圖所示之圖案。 接著，進行後續的步驟，以完成電容之製造。然而此後續 之製程，無關本發明之特徵，故此處不再贅述。 綜上所述，本發明的特徵在於： 1·本發明之較佳實施例的一種DRAM之電容的製造方 法，係形成金屬鎢插塞以連接矽基底之源極/汲極區，以及 以金屬鎢作爲電容器之上下電極，並以五氧化二鉅作爲介 電層，取代傳統製程上以形成多晶矽層/HSG/ONO三層結 構爲動態隨機存取記憶體的電容器。 2. 依照本發明之較佳實施例，以金屬鎢插塞，取代習 知所用的摻雜多晶矽作爲內導線，可以使得內導線的電阻 下降，因而電晶體的操作速度會增快。 3. 本發明係使用以CVD和PVD所沉積的金屬鎢當電 容之下電極。其中，CVD所沉積之金屬鎢層具有粗糙的表 本紙張尺度適用中國國家標準（CNS )八4規格（210X297公釐） (請先聞讀背面之注，意事項再镇^頁) 訂|丨. 竣， 3069tw£doc/008 3069tw£doc/008 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（11 ) 面，可以增加表面積；而做爲介電層之五氧化二鉅具有極 佳之介電常數，皆可以有效增加電容量。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 (請先閣讀背面之注意事項再填寫本頁)、 1T Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. The paper size is free of Chinese National Standards (CNS) Α · 4 specifications (210X297 mm) 408491 3069twfl, doc / 002 ^ 87113971 A7 B7 V. Description of the invention (b ) Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 10, 20: Semiconductor substrates 12, 23: Gate oxide layer 13: Alarm layer 14, 29: Source / drain region 22: Field oxide layer 24, 240, 340: Doped polycrystalline silicon layer 26, 260: Tungsten silicide layer 28 '48: Silicon nitride layer 30, 50: Spacer wall 32: Contact window of bit line □ 34: Contact window of contact 36: First insulating layer 38' 40 : Metal tungsten plug 42: Second insulation layer 44: AA ------ Yiyi contact window 46: Metal crane layer 52: Bit line 54: Third insulation layer 56: Photoresist 58: Fourth contact window 60: Lower electrode 62: Dielectric layer 64: Upper electrode 300: Polycrystalline plug (I also read the business matters on the back and then fill out this page) Repair ---- Order ---------- Weiben Paper scale suitable for China National Standard (CNS) A4 Specification (210 X 297 mm) 408491 3069twfl .doc / 002 A7 B7_ V. Description of the Invention (G) 400: Deposition of Hemispherical Silicon Grain Layer · 500: Oxide / Nitride / Oxidation Example of a Three-Layer Structure (Please read the precautions on the back before filling out this page) Figures 6A to 6L are cross-sectional views showing the manufacturing process of a DRAM capacitor according to a preferred embodiment of the present invention. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, please refer to FIG. 6A. An isolation structure is formed on a semiconductor silicon substrate 20, for example, the position of the shallow trench is defined by the shallow trench insulation method, and then the conventional chemical vapor phase is used. A deposition method (chemical vapor deposition; hereinafter abbreviated as CVD) injects sand dioxide into shallow trenches to form a field oxide layer 22. A gate oxide layer 23 is formed on the silicon substrate 20 and the field silicon oxide layer 22, for example, by a thermal oxidation method, and then a first conductive layer is formed on the gate oxide layer 23, such as sequentially depositing a layer of about 1000 A thick doped polycrystalline silicon layer 24, a layer of tungsten silicide 26 with a thickness of about 1000 A, and a layer of silicon nitride 32 with a thickness of about 1500 A. The doped polycrystalline silicon layer 24 and the tungsten silicide layer 26 form a first conductive layer, and the silicon nitride layer 28 forms a protective layer. A layer of photoresist (not shown in the figure) is coated on the silicon nitride layer 28, and the gate or wire line of the transistor is defined by a conventional lithography process, and then a conventional etching step is used. The unprotected area is etched until the silicon substrate 10 is exposed. Then, a silicon nitride is deposited on the upper side, and the structure of the spacer 30 is formed on the periphery of the transistor gate by anisotropic etching. In addition, before the spacer 30 is formed, the gate is protected by the silicon nitride layer 28, and the surface of the substrate 20 is ion-implanted to form a source / drain region 29 on the surface of the substrate 20 on the side of the gate. Referring to FIG. 6B, a first insulating layer 36 is formed. For example, a layer of silicon dioxide with a thickness of about 2,000 people and a layer of borophosphosilicate glass (BPSG) with a thickness of about 7,500 A are deposited by atmospheric pressure CVD. The two constitute the first insulation. Layer 36. And the basic paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ^ 08491 3069twfl, doc / 002 A7 ___B7_____ V. Description of the invention (ί) The borophosphosilicate glass layer was reflowed in an environment of about 800 ° C. The surface is then planarized by chemical mechanical polishing (hereinafter referred to as CMP) or etch-back, and then the first insulating layer 36 is etched up to the silicon substrate. 20, and the source and drain contact windows are contacted. 32, 34 are defined. At this time, since the gate of the transistor is protected by the silicon nitride layer 28 and the spacer 30, the contact windows 32 and 34 can be defined by using a dry etching method to form a self-align contact (SAC) window. Referring to FIG. 6C, metal tungsten is inserted into the contact windows 32 and 34 of the source and drain electrodes to connect the source / drain regions exposed in the multiple contact windows, including the contact window 32 and contacts of the bit line. The contact window 34 is formed with a plurality of metal tungsten plugs 38 and 40 to form an inner metal wire. Then, CMP or tungsten etch-back is used to make the surface of the metal tungsten and the first insulating layer 36 the same height. The metal tungsten plugs 38 and 40 replace the conventionally used doped polycrystalline silicon as the inner conductor. The advantage is that the resistance of the inner conductor can be reduced, and the operation speed of the transistor will be increased. Please refer to FIG. 6D, and then deposit a second insulating layer 42, such as a layer of about 2000 A thick silicon dioxide by atmospheric pressure CVD. The conventional lithography etching step is used to define a second contact window 44 at the same position as the metal tungsten plug 38 of the contact window 32 on the bit line. Referring to FIG. 6E, a second conductive layer is formed over the second insulating layer 42 and the second contact window 44. For example, a metal tungsten layer 46 with a thickness of about 2000 A and a layer with a thickness of about 1,500 A are sequentially deposited. Silicon nitride 48. The metal tungsten layer 46 forms a second conductive layer, and the silicon nitride layer 48 forms a protective layer. Then, through the conventional lithographic etching step, the area not protected by photoresist (not shown in the figure) is etched until the second insulating layer 42 is exposed, so as to define in. This paper size applies Chinese National Standard (CNS) A4. Specifications (210 X 297 public meals 1 ^ 1 · —-__________ '(谙 fc read the business matters on the back and fill in the φ page) • ^ 1 ^ 1 ^ 1 .1 Order · ---- ^ ---- line 3069twf .doc / 008 408491 A7 B7 Printed bags of the consumer cooperative of employees of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (1) The bit line 52 is then deposited. Then, a silicon nitride is deposited on top, and by anisotropic etching, The structure of the gap wall 50 is formed around the bit line 52. Please refer to FIG. 6F to form a third insulating layer 54. For example, a layer of about 2000 A thick sand dioxide is deposited by atmospheric pressure CVD; (High density plasma; HDP), and then deposit a layer of silicon oxide or other oxides with a thickness of about 16KA, both of which constitute the third insulating layer 54. Then, the surface of the third insulating layer 54 is planarized by CMP; then, The upper photoresist 56 covers the third insulating layer 54 in a specific area. Referring to FIG. 6G, etching Resist the exposed third insulating layer 54 and further etch the second insulating layer 42 to form a fourth contact window 58 to expose the metal tungsten plug 40 and then remove the photoresist 50. According to a preferred embodiment of the present invention A method for manufacturing a DRAM capacitor, since the bit line 52 is protected by a silicon nitride layer 48 and a spacer 50, the etching step here can be etched by self-aligning the contact window to avoid the etching step. Disadvantages caused by the misalignment of the center alignment. Please refer to Figure 6H, and then according to the shape of the entire substrate structure, for example, physical vapor deposition (PVD) is used to deposit a layer of metal tungsten with a thickness of about 300A Then, the entire base structure is covered; then, a layer of metal tungsten with a thickness of about 500 A is deposited by CVD to jointly form the lower electrode 60. Among them, the metal tungsten deposited by CVD has a rough surface, which can increase the surface area and increase the capacitance. Referring to FIG. 61, the metal tungsten of the lower electrode 60 on the third insulating layer 54 is removed by CMP until the surface of the third insulating layer 54 is exposed. (Please read the notes on the back before filling this page) FREE) · This paper size is applicable to Chinese National Standard (CNS) A4 size (210X297 mm) 3069twf.doc / 008 U8491 A7 B7 Explanation of the invention (A) Please refer to FIG. 6J, and use a buffered uranium oxide etchant (BOE 20: 1) to perform an etching step for about 400 to 600 seconds to remove the third insulating layer 54. Please refer to FIG. 6K, for example, a rapid thermal processing (RTP) process is performed at 850 ° C and an ammonia-filled environment for 120 seconds. Subsequently, for example, a deposition method is used to deposit a layer of pentoxide with a thickness of about 80 A to cover the entire base structure as the dielectric layer 62. The pentoxide has an excellent dielectric constant, which can effectively increase the capacitance as a dielectric layer. Please refer to Fig. 6L, for example, using RTP at 850t and oxygen-filled environment for 60 seconds. Then, for example, a layer of metal tungsten with a thickness of about 500 A is deposited with PVD to cover the entire base structure to form the capacitor-on-electrode 64. Then, the traditional lithographic etching method is used to define the pattern shown in FIG. 6L. Then, the subsequent steps are performed to complete the manufacturing of the capacitor. However, this subsequent process has nothing to do with the features of the present invention, so it will not be repeated here. In summary, the present invention is characterized by: 1. A method of manufacturing a DRAM capacitor according to a preferred embodiment of the present invention, which forms a metal tungsten plug to connect a source / drain region of a silicon substrate, and a metal Tungsten is used as the upper and lower electrodes of the capacitor, and uses pentoxide as the dielectric layer. It replaces the traditional process of forming a capacitor with a polycrystalline silicon layer / HSG / ONO three-layer structure as a dynamic random access memory. 2. According to a preferred embodiment of the present invention, the use of a metal tungsten plug instead of the conventionally doped polycrystalline silicon as the inner conductor can reduce the resistance of the inner conductor, and thus the operating speed of the transistor will increase. 3. The present invention uses a metal tungsten electrode deposited by CVD and PVD as a capacitor. Among them, the metal tungsten layer deposited by CVD has a rough surface and the paper size is applicable to the Chinese National Standard (CNS) 8-4 specification (210X297 mm) (please read the note on the back first, and then note the ^ page) Order | 丨At the end, 3069tw doc / 008 3069tw doc / 008 Printed by A7 B7 of the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. The description of the invention (11) can increase the surface area; the pentoxide as the dielectric layer has Excellent dielectric constant can effectively increase capacitance. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. (Please read the notes on the back before filling out this page)
本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）This paper size applies to Chinese National Standard (CNS) A4 (210X297 mm)