3729twf.doc/008 3729twf.doc/008 經濟部中央標準局負工消費合作社印製 H? 五、發明説明（（） 本發明是有關於一種動態隨機存取記憶體（Dynamic Random Access Memory; DRAM)及其製造方法，且特別是 有關於一種動態隨機存取記憶體電容器之製造方法，利用 增加電容器之儲存電極的表面積，以提高動態隨機存取記 憶體之儲存電荷。 當電腦微處理器(Microprocessor)的功能越來越強，軟 體所進行的程式與運算越來越龐大時，記憶體的容量需求 也就越來越高。電容器是動態隨機存取記憶體藉以儲存訊 號的心臟，如果電容器所儲存的電荷越多，在讀取資料時 受雜訊影響，如α粒子所產生的軟錯記(Soft Errors)將大大 的降低電容器效能。增加電容器儲存電荷能力的方法有： (1)增加介電層的介電常數，使電容器單位面積所能儲存的 電荷數增加；（2)減少介電層的厚度，但是介電材質本身的 品質程度將使介電層的厚度受限於某一最低値；以及(3)增 加電容器的面積，使整個儲存於電容器內的電荷數量增 加。 傳統的動態隨機存取記憶體的儲存電容量較小時，在 積體電路製程中，主要利用二度空間的電容器來實現，亦 即所謂的平坦型電容器（Planar Type Capacitor)。平坦型電 容器需佔用半導體基底相當大的面積來儲存電荷，故並不 適合應用於高度的積集化。高度積集化的動態隨機存取記 憶體需要利用三度空間的電容器來實現，例如所謂的堆疊 型（Stacked Type)，溝槽型（Trench Type)，柱狀（Cylinder3729twf.doc / 008 3729twf.doc / 008 Printed by the Consumers' Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs H. V. Description of the invention (() The present invention relates to a dynamic random access memory (DRAM) And a method for manufacturing the same, and in particular, a method for manufacturing a dynamic random access memory capacitor, by increasing the surface area of the storage electrode of the capacitor to increase the stored charge of the dynamic random access memory. When a computer microprocessor (Microprocessor ) The function is getting stronger and stronger, and as the programs and calculations performed by the software become larger and larger, the memory capacity requirements become higher and higher. The capacitor is the heart of the dynamic random access memory to store signals. The more stored charges are affected by noise when reading data, such as Soft Errors generated by alpha particles, which will greatly reduce the performance of the capacitor. The methods to increase the capacity of the capacitor to store charge are: (1) increase the dielectric The dielectric constant of the electrical layer increases the number of charges that can be stored per unit area of the capacitor; (2) The thickness of the dielectric layer is reduced, but the dielectric The quality of the material itself will limit the thickness of the dielectric layer to a certain minimum; and (3) increase the area of the capacitor and increase the amount of charge stored in the capacitor as a whole. Traditional dynamic random access memory storage When the capacitance is small, in the integrated circuit manufacturing process, a capacitor with a two-degree space is mainly used to achieve it, which is called a planar capacitor (Planar Type Capacitor). The planar capacitor needs to occupy a relatively large area of the semiconductor substrate to store charge. Therefore, it is not suitable for high accumulation. Highly accumulated dynamic random access memory needs to be realized by using three-dimensional capacitors, such as the so-called stacked type and trench type. (Cylinder
Type)電容器，記憶體元件在進入更高度的積集化時，單純 3 本紙張尺度適用中國國家標準（CNS ) Λ4規格（21〇χ297公楚) (請先閱讀背面之注意事項再填寫本頁) m m m n^i tn U5-e 3729twf.d〇c/008 Λ7 五、發明説明（么） 的三度空間電容器結構已不敷使用，在小面積範圍內增加 動態隨機存取記憶體的電容器表面積的方法便被發展。 第1A圖至第1D圖，所繪示係爲習知動態隨機存取記憶 體柱狀電容器的製造方法。 請參照第1A圖，在所提供一個半導體基底100上形成一 場隔離區101以定義元件之主動區，續再於半導體基底100 上形成動態存取記憶體的電晶體104，其中電晶體103包括 閘極104與源/汲極區102，再於半導體基底100上形成內介 電層106，圖案化此內介電層106,在內介電層106中形成一 儲存節點開口 108暴露出源/汲極區102電性耦接。 請參照第1B圖，在內介電層106上，形成第一多晶矽層 110，並塡滿儲存節點開口 108。然後，再於第一多晶矽層 110上，形成已圖案化的氧化層112，並對應於儲存節點開 口 108。接著，在氧化層112及第一多晶矽層110上，再形成 一層第二多晶矽層Π4。 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 請參照第1C圖，利用非等向性蝕，去除部分的第一多 晶矽層110及第二多晶矽層114，直到暴露出內介電層106 爲止。在氧化層112側壁，形成第二多晶矽間隙壁114a，被 氧化層Π2覆蓋的部分第一多晶矽層110a，因受氧化層112 的保護而不會被去除。 請參照第1D圖，利用濕式蝕刻法，去除氧化層112，形 成由第一多晶矽層ll〇a及第二多晶矽層114a所構成的儲存 電極。接著，在內介電層106上形成薄介電質層116覆蓋住 4 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公矩） 3729twf.doc/008 3729twf.doc/008 經濟部中央標準局貝工消费合作社印褽 B7 五、發明説明（$ ) 儲存電極，再形成一上電極118覆蓋住薄介電質層116，完 成動態隨機存取記憶體柱狀電容器的結構。 請參照第2A至第2B圖，其繪示爲習知的另一種動態隨 機存取記憶體的柱狀電容器的剖面示意圖。 請參照第2A圖，在所提供一個半導體基底200上形成一 場隔離區201以定義元件之主動區，續再於半導體基底2〇〇 上形成動態存取記憶體的電晶體2〇4，其中電晶體2〇4包括 閘極204與源/汲極區202，再於半導體基底200上形成內介 電層206，圖案化此內介電層206，在內介電層206中形成一 儲存節點開口 208暴露出源/汲極區202。接著，利用光阻層 以習知的蝕刻、微影製程，在內介電層206上形成一已圖案 化的多晶矽層210，塡滿儲存節點開口 208，並與源/汲極區 202電性耦接。 請參照第2B圖，再利用光阻層以習知的蝕刻、微影製 程，去除部份對應於儲存節點開口 208的多晶矽層210，以 形成一由多晶矽層210a所構成的柱狀儲存電極。接著，在 內介電層206上形成薄介電質層212覆蓋住儲存電極，再形 成一上電極214覆蓋住薄介電質層212，完成動態隨機存取 記憶體柱狀電容器的結構。 目前習知用於動態隨機存取記憶體的柱狀電容器，其 方法所形成的單一柱狀電容器，其缺點在於所增加的電容 器面積有限，不足以應用於更高的電容量需求，且由第2A 至第2B圖所繪示的習知之另一種動態隨機存取記憶體的 5 (請先閱讀背面之注意事項再填寫本頁)Type) Capacitors, memory elements are entering a higher level of integration, only 3 paper sizes are applicable to the Chinese National Standard (CNS) Λ4 specification (21〇χ297 公 楚) (Please read the precautions on the back before filling this page ) mmmn ^ i tn U5-e 3729twf.d〇c / 008 Λ7 V. The three-dimensional space capacitor structure of the invention (me) is no longer sufficient, and the surface area of the capacitor of the dynamic random access memory is increased in a small area. The method was developed. Figures 1A to 1D show the manufacturing method of a conventional column capacitor of dynamic random access memory. Referring to FIG. 1A, a field isolation region 101 is formed on a provided semiconductor substrate 100 to define an active area of a component, and a transistor 104 of a dynamic access memory is further formed on the semiconductor substrate 100. The transistor 103 includes a gate The electrode 104 and the source / drain region 102, and then an internal dielectric layer 106 is formed on the semiconductor substrate 100, the internal dielectric layer 106 is patterned, and a storage node opening 108 is formed in the internal dielectric layer 106 to expose the source / drain The pole region 102 is electrically coupled. Referring to FIG. 1B, a first polycrystalline silicon layer 110 is formed on the inner dielectric layer 106 and fills the storage node opening 108. Then, a patterned oxide layer 112 is formed on the first polycrystalline silicon layer 110 and corresponds to the storage node opening 108. Next, a second polycrystalline silicon layer Π4 is formed on the oxide layer 112 and the first polycrystalline silicon layer 110. Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page) Please refer to Figure 1C, using anisotropic etching to remove part of the first polycrystalline silicon layer 110 and the second The silicon layer 114 is formed until the inner dielectric layer 106 is exposed. On the sidewall of the oxide layer 112, a second polycrystalline silicon spacer 114a is formed. A part of the first polycrystalline silicon layer 110a covered by the oxide layer Π2 is not removed because it is protected by the oxide layer 112. Referring to FIG. 1D, the oxide layer 112 is removed by a wet etching method to form a storage electrode composed of a first polycrystalline silicon layer 110a and a second polycrystalline silicon layer 114a. Next, a thin dielectric layer 116 is formed on the inner dielectric layer 106 to cover 4 paper sizes. The Chinese paper standard (CNS) Λ4 specification (210X297 mm) is applicable. 3729twf.doc / 008 3729twf.doc / 008 Central Standard of the Ministry of Economic Affairs Yinbei B7, Bureau Coconut Consumer Cooperative Co., Ltd. 5. Description of the invention ($) The storage electrode is formed with an upper electrode 118 covering the thin dielectric layer 116 to complete the structure of the column capacitor of the dynamic random access memory. Please refer to FIGS. 2A to 2B, which are schematic cross-sectional views of a conventional cylindrical capacitor of another type of dynamic random access memory. Referring to FIG. 2A, a field isolation region 201 is formed on a provided semiconductor substrate 200 to define an active area of the device, and a transistor 204 of a dynamic access memory is further formed on the semiconductor substrate 200. The crystal 204 includes a gate 204 and a source / drain region 202, and an internal dielectric layer 206 is formed on the semiconductor substrate 200. The internal dielectric layer 206 is patterned to form a storage node opening in the internal dielectric layer 206. 208 exposes the source / drain region 202. Then, a photoresist layer is used to form a patterned polycrystalline silicon layer 210 on the inner dielectric layer 206 by a conventional etching and lithography process, which fills the storage node opening 208 and is electrically connected to the source / drain region 202. Coupling. Referring to FIG. 2B, the photoresist layer is used in a conventional etching and lithography process to remove a portion of the polycrystalline silicon layer 210 corresponding to the storage node opening 208 to form a columnar storage electrode composed of the polycrystalline silicon layer 210a. Next, a thin dielectric layer 212 is formed on the inner dielectric layer 206 to cover the storage electrode, and an upper electrode 214 is formed to cover the thin dielectric layer 212, thereby completing the structure of the dynamic random access memory column capacitor. At present, conventional column capacitors used in dynamic random access memory. The method of forming a single column capacitor has the disadvantage that the increased area of the capacitor is limited, which is not sufficient for higher capacitance requirements. 2A to 2B of another conventional dynamic random access memory 5 (Please read the precautions on the back before filling this page)
本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公飨） 3729twf.doc/008 Λ7 H7 _ 五、發明説明（t ) 柱狀電容器製程，得知此柱狀電容器必須使用兩次光罩， 造成製作過程較繁複。 因此本發明的主要目的，在提供一種動態隨機存取記 憶體雙柱狀電容之製造方法，藉著雙柱狀的幾何表面以增 加電容器的表面積，有效的提高電容量（Capacitance)，且 適用於更小尺寸的半導體元件，並且在形成雙柱狀的電容 器構造過程中僅需使用一次光罩。 根據本發明的上述及其他目的，提出一種動態隨機存 取記憶體雙柱式電容之製造方法，首先，提供半導體基底， 在基底上已形成有電晶體，此電晶體具有一閘極及一源/ 汲極區，在半導體基底上覆蓋一層內介電層，於介電層中 形成儲存節點開口，暴露出源/汲極區，在內介電層上形成 第一多晶矽層，並塡滿儲存節點開口，在第一多晶矽層上 依序形成薄氧化層及第二多晶矽層，去除部份的第二多晶 矽層’留下部份第二多晶矽層對應於儲存節點開口，並去 除部份的薄氧化層，在第二多晶矽層與第一多晶矽層間， 留下部份的薄氧化層正對儲存節點開口，在第二多晶矽層 與第一多晶矽層間，形成物質層，在第二多晶矽層與物質 層的側壁’形成間隙壁，以薄氧化層、間隙壁及物質層爲 蝕刻終止層，去除第二多晶矽層及部份第一多晶矽層，再 以薄氧化層及間隙壁爲罩幕，去除物質層及部份第一多晶 矽層，直至暴露出部份內介電層，再去除薄氧化層及間隙 壁，形成一儲存電極，在基底上依序形成一介電層與一上 電極。 6 本紙張尺度適用中國國家ϋ ( CNS ) A4規格（210X297公嫠) ---------— -* (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部中央標準局貝工消費合作社印製 3729twf.doc/008 Λ7 H? 五 '發明説明（t) (請先閲讀背面之注意事項再填寫本頁) 爲讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉一實施例，並配合所附圖式，作詳細說明如下： 圖式之簡單說明： H1A圖至第1D圖，所繪示係爲習知動態隨機存取記憶 體柱狀電容器的製造方法； 第2A至第2B圖，所繪示係爲習知的另一種動態隨機存 取記憶體的柱狀電容器的剖面示意圖； 第3A圖至第3H圖，所繪示係依照本發明第一實施例， 形成動態隨機存取記億體雙柱式電容器結構的製造方法結 構剖面圖；以及 第4圖，所繪示係爲第3G圖之上視圖。 圖式標記說明： 100、 200、300 :半導體基底 101、 201、301 :場隔離區 102、 202、304 :源/汲極區 1.04、204、302 :閘極 103、 203、303 :電晶體 106、206、306 :內介電層 經濟部中央標準局貝工消费合作社印製 108、208、308 :儲存節點開口 110、110a、310 :第一多晶矽層 112 :氧化層 114、114a、314、314:第二多晶矽層 114a :第二多晶矽層間隙壁 116、212 :薄介電層 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公碰） 3729twf.doc/008 Λ 7 B7 五、發明説明（έ ) 118、214、324 :上電極 210、210a :多晶矽層 312、312a :薄氧化層 316 :光阻層 318 :罩幕層 320 :間隙壁 321 :形成儲存電極的區域 322 :介電層 Η :厚度 實施例 第3Α圖至第31圖，所繪示係爲依照本發明一較佳實施 例的一種隨機存取記憶體雙柱式電容器的流程結構剖面 圖。 經濟部中央標準局貝工消费合作社印袋 (請先閱讀背面之注意事項再填寫本頁) 請參照第3Α圖，首先，在所提供一個半導體基底300 上形成一場隔離區301以定義元件之主動區，續再於半導體 基底300上形成動態存取記憶體的電晶體303，接著再覆蓋 一層內介電層306於半導體基底300上，並將內介電層306 圖案化，在內介電層306中形成一儲存節點開口 308暴露出 源/汲極區304。 其中，半導體基底300的材質例如爲Ρ型矽基底；場隔 離區301的形成方式例如爲局部區域氧化法（LOCOS)或淺 溝渠隔離法（STI)。電晶體303具有閘極302與源極/汲極區 304，且源極/汲極區304位於閘極302兩側之半導體基底300 中，而內介電層306覆蓋於閘極302和源/汲極區304上，此 8 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 3729twf.doc/008 A7 B7 五、發明说明（9) (請先聞讀背面之注意事項再填寫本頁) 內介電層306之材料例如爲氧化砂、砂酸四乙酯 (Tetraethylorthosilicate ; TEOS)以及棚隣砂玻璃 (Borophosphosilicate Glass ; BPSG)等，而其形成的方式例如 可以爲化學氣相沈積法（Chemical Vapor Deposition ; CVD)。 請參照第3B圖，在內介電層306上形成一第一多晶矽層 310，內介電層306並塡滿儲存節點開口 308與源/汲極區304 電性耦接。其中，第一多晶矽層310的厚度與欲形成之儲存 電極的高度相等，且儲存電極爲第一多晶矽層3 10所架構而 成，此第一多晶矽層310形成的方式例如爲化學氣相沈積 法。然後，於第一多晶矽層310上，依序形成薄氧化層312 與第二多晶矽層314。 請參照第3C圖，利用一已圖案化之光阻層3 16爲蝕刻罩 幕，此光阻層316的圖案對應於儲存節點開口 308，且光阻 層3 Ιό所遮蓋的部份第一多晶矽層3 10爲欲形成儲存電極的 部份區域。進行蝕刻步驟，將第二多晶矽層314圖案化，用 以在光阻層3 16與薄氧化層3 12間形成如圖所示之第二多晶 矽層314a，並對應儲存節點開口 308。 請參照第3D圖，去除光阻層310後，去除部份薄氧化層 312，形成薄氧化層312a對應於儲存節點開口 308，直到暴 露出部份的多晶矽層310，去除薄氧化^312的方法例如使 用等向性蝕刻法（Isotropic Etch)，在第二多晶矽314a與第— 多晶矽3 10間形成薄氧化層312a，其中薄氧化層312a的大小 略小於第二多晶矽層3 14a。之後在內介電層S10上形成—物 9 $紙張只中國國家择二率(1奶）Λ4規格T210X297公釐） -- 經渗-部十次樟準局員J消费含作社印來 3729twf.doc/008 A7 B7 五、發明説明（$ ) 質層（未繪出）並塡入第二多晶矽層3 14a與第一多晶矽層 310間與薄氧化層3 12a接觸，此物質層較佳爲氮化矽層。利 用回蝕刻法去除部份物質層，留下介於第二多晶矽層314a 與內介電層3 10間的物質層3 18,且物質層3 18與該薄氧化層 312的範圍與第二多晶矽層314a相同。 請參照第3E圖’在第二多晶矽層314a與物質層318的側 壁形成一間隙壁320。此間隙壁320的材質較佳爲一氧化物 間隙壁，其形成方式例如以化學氣相沈積法，沈積一氧化 物層，並利用回蝕刻法蝕刻形成氧化物間隙壁320。其中間 隙壁320與薄氧化層3 12a具有相近的蝕刻性質，因此在後續 蝕刻部份第一多晶矽層31〇，形成由部份第一多晶矽層310 所架構的儲存電極製程中，將以間隙壁320與薄氧化層3 12a 爲罩幕，進行蝕刻。 請參照第3F圖，以薄氧化層312a、間隙壁32〇及物質層 318爲蝕刻終止層，利用回蝕刻法’去除第二多晶矽層 314a，並同時去除未被薄氧化層312a、間隙壁320及物質層 318覆蓋的第一多晶矽層310 ’其中薄氧化層312a、間隙壁 320及物質層318爲欲形成儲存電極的區域321，其中欲形成 儲存電極的區域321下之第一多晶矽層31〇將不會被去除， 經去除未被間隙壁320、物質層318及薄氧化層312a所覆蓋 的第一多晶矽層310’形成第一多晶矽層/l〇a。 請參照第3G圖’以間隙壁320及薄氧化層爲罩幕’ 去除物質層3 18及部份第一多晶矽層3l〇a’直到暴露出部份 本紙張尺度適用中國國家標卑（CNS ) Λ4規格（210 X 297公釐） (請先閱讀背面之注意^項再填寫本頁)This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 cm) 3729twf.doc / 008 Λ7 H7 _ V. Description of the invention (t) The manufacturing process of the cylindrical capacitor, we know that the cylindrical capacitor must be used twice. The production process is more complicated. Therefore, the main object of the present invention is to provide a method for manufacturing a dual-cylindrical capacitor of a dynamic random access memory, which can increase the surface area of a capacitor by a dual-cylindrical geometric surface, and effectively increase the capacitance. Smaller-sized semiconductor components, and only need to use a photomask once to form a double-pillar capacitor structure. According to the above and other objects of the present invention, a method for manufacturing a dual-pillar capacitor of dynamic random access memory is provided. First, a semiconductor substrate is provided, and a transistor has been formed on the substrate. The transistor has a gate and a source. / Drain region, covering an inner dielectric layer on the semiconductor substrate, forming a storage node opening in the dielectric layer, exposing the source / drain region, forming a first polycrystalline silicon layer on the inner dielectric layer, and With a full storage node opening, a thin oxide layer and a second polycrystalline silicon layer are sequentially formed on the first polycrystalline silicon layer, and a portion of the second polycrystalline silicon layer is removed, leaving a portion of the second polycrystalline silicon layer corresponding to The storage node is opened, and a part of the thin oxide layer is removed. Between the second polycrystalline silicon layer and the first polycrystalline silicon layer, a part of the thin oxide layer is left facing the storage node opening, and the second polycrystalline silicon layer and the A material layer is formed between the first polycrystalline silicon layer, and a gap wall is formed on the side wall of the second polycrystalline silicon layer and the material layer. The thin oxide layer, the gap wall and the material layer are used as the etching stop layer to remove the second polycrystalline silicon layer. And part of the first polycrystalline silicon layer, and then a thin oxide layer The barrier wall is a mask. The material layer and part of the first polycrystalline silicon layer are removed until a part of the internal dielectric layer is exposed, and then the thin oxide layer and the barrier wall are removed to form a storage electrode. A storage electrode is sequentially formed on the substrate. The dielectric layer and an upper electrode. 6 This paper size is applicable to China National Cricket (CNS) A4 specification (210X297 cm) ------------* (Please read the precautions on the back before filling this page) Order by the Central Bureau of Standards of the Ministry of Economic Affairs Printed by Industrial and Consumer Cooperatives 3729twf.doc / 008 Λ7 H? Five 'invention description (t) (Please read the notes on the back before filling this page) In order to make the above-mentioned objects, features, and advantages of the present invention more obvious and easier to understand In the following, an embodiment is given, and it is described in detail with the accompanying drawings as follows: A brief description of the drawings: H1A to 1D, shown are the conventional dynamic random access memory column capacitors. Manufacturing method; FIGS. 2A to 2B, which are schematic sectional views of a columnar capacitor of another conventional type of dynamic random access memory; FIGS. 3A to 3H, which are shown in accordance with the present invention. An embodiment is a structural cross-sectional view of a manufacturing method for forming a dynamic random access memory bi-capacitor dual-pillar capacitor structure; and FIG. 4 is a top view of FIG. 3G. Description of graphical symbols: 100, 200, 300: semiconductor substrates 101, 201, 301: field isolation regions 102, 202, 304: source / drain regions 1.04, 204, 302: gate 103, 203, 303: transistor 106 , 206, 306: Printed by Shelley Consumer Cooperative, Central Standards Bureau of the Ministry of Internal Dielectric Layers, 108, 208, 308: Storage node openings 110, 110a, 310: First polycrystalline silicon layer 112: Oxide layers 114, 114a, 314 , 314: second polycrystalline silicon layer 114a: second polycrystalline silicon layer spacer 116, 212: thin dielectric layer This paper size applies Chinese National Standard (CNS) Λ4 specification (210X297 male touch) 3729twf.doc / 008 Λ 7 B7 V. Description of the invention 118, 214, 324: upper electrodes 210, 210a: polycrystalline silicon layers 312, 312a: thin oxide layer 316: photoresist layer 318: cover layer 320: gap wall 321: forming storage electrode Region 322: dielectric layer Η: FIG. 3A to FIG. 31 of the thickness embodiment, which are cross-sectional views showing a flow structure of a random access memory dual-pillar capacitor according to a preferred embodiment of the present invention. Printed bags of the Shellfish Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page) Please refer to Figure 3A. First, a field 301 is formed on a provided semiconductor substrate 300 to define the initiative of the component. Then, a transistor 303 of a dynamic access memory is formed on the semiconductor substrate 300, and then an internal dielectric layer 306 is covered on the semiconductor substrate 300, and the internal dielectric layer 306 is patterned to form an internal dielectric layer. A storage node opening 308 is formed in 306 to expose the source / drain region 304. The material of the semiconductor substrate 300 is, for example, a P-type silicon substrate; the formation method of the field isolation region 301 is, for example, a local area oxidation method (LOCOS) or a shallow trench isolation method (STI). The transistor 303 has a gate 302 and a source / drain region 304. The source / drain region 304 is located in the semiconductor substrate 300 on both sides of the gate 302. The inner dielectric layer 306 covers the gate 302 and the source / drain region. On the drain region 304, these 8 paper sizes are applicable to the Chinese National Standard (CNS) A4 specifications (210X297 mm) 3729twf.doc / 008 A7 B7 V. Description of the invention (9) (Please read the precautions on the back before filling (This page) The material of the inner dielectric layer 306 is, for example, oxidized sand, Tetraethylorthosilicate (TEOS), and Borophosphosilicate Glass (BPSG), etc., and the formation method thereof can be, for example, chemical vapor deposition (Chemical Vapor Deposition; CVD). Referring to FIG. 3B, a first polycrystalline silicon layer 310 is formed on the inner dielectric layer 306. The inner dielectric layer 306 fills the storage node opening 308 and is electrically coupled to the source / drain region 304. The thickness of the first polycrystalline silicon layer 310 is equal to the height of the storage electrode to be formed, and the storage electrode is structured by the first polycrystalline silicon layer 310. The method for forming the first polycrystalline silicon layer 310 is, for example, It is a chemical vapor deposition method. Then, a thin oxide layer 312 and a second polycrystalline silicon layer 314 are sequentially formed on the first polycrystalline silicon layer 310. Referring to FIG. 3C, a patterned photoresist layer 3 16 is used as an etching mask. The pattern of the photoresist layer 316 corresponds to the storage node opening 308, and the portion covered by the photoresist layer 3 is the first. The crystalline silicon layer 3 10 is a partial region where a storage electrode is to be formed. An etching step is performed to pattern the second polycrystalline silicon layer 314 to form a second polycrystalline silicon layer 314a as shown in the figure between the photoresist layer 3 16 and the thin oxide layer 3 12 and correspond to the storage node opening 308. . Referring to FIG. 3D, after removing the photoresist layer 310, a part of the thin oxide layer 312 is removed to form a thin oxide layer 312a corresponding to the storage node opening 308 until a portion of the polycrystalline silicon layer 310 is exposed. For example, using an isotropic etching method (Isotropic Etch), a thin oxide layer 312a is formed between the second polycrystalline silicon 314a and the first polycrystalline silicon 310, wherein the size of the thin oxide layer 312a is slightly smaller than that of the second polycrystalline silicon layer 314a. Then formed on the inner dielectric layer S10-material 9 $ paper only China's national alternative rate (1 milk) Λ4 size T210X297 mm)-after infiltration-ten times by the Zhang Junzhe Bureau member J Consumption printed as 3729twf. doc / 008 A7 B7 V. Description of the invention ($) The quality layer (not shown) is incorporated into the second polycrystalline silicon layer 3 14a and the first polycrystalline silicon layer 310 in contact with the thin oxide layer 3 12a. This material layer A silicon nitride layer is preferred. A part of the material layer is removed by the etch-back method, leaving a material layer 3 18 between the second polycrystalline silicon layer 314a and the inner dielectric layer 3 10, and the range of the material layer 3 18 and the thin oxide layer 312 is the same as that of the thin oxide layer 312. The two polycrystalline silicon layers 314a are the same. Referring to FIG. 3E, a gap 320 is formed on the side walls of the second polycrystalline silicon layer 314a and the material layer 318. The material of the spacer wall 320 is preferably an oxide spacer wall, and the formation method is, for example, a chemical vapor deposition method, depositing an oxide layer, and forming the oxide spacer wall 320 by etching back. The spacer 320 and the thin oxide layer 3 12a have similar etching properties. Therefore, in the subsequent process of etching a part of the first polycrystalline silicon layer 31 to form a storage electrode structured by a part of the first polycrystalline silicon layer 310, The spacer 320 and the thin oxide layer 3 12a are used as a mask to perform etching. Referring to FIG. 3F, using the thin oxide layer 312a, the spacer 32o, and the material layer 318 as the etching stop layer, the second polycrystalline silicon layer 314a is removed by the etch-back method, and the non-thin oxide layer 312a and the gap are simultaneously removed. The first polycrystalline silicon layer 310 ′ covered by the wall 320 and the substance layer 318 is a thin oxide layer 312 a, the spacer 320 and the substance layer 318 are the first region 321 where the storage electrode is to be formed, and the first region under the region 321 where the storage electrode is to be formed. The polycrystalline silicon layer 31 will not be removed. The first polycrystalline silicon layer 310a is formed by removing the first polycrystalline silicon layer 310 'not covered by the spacer 320, the material layer 318, and the thin oxide layer 312a. . Please refer to Figure 3G, 'with the spacer 320 and the thin oxide layer as the cover'. Remove the material layer 3 18 and part of the first polycrystalline silicon layer 310a 'until a part of this paper is exposed. CNS) Λ4 specification (210 X 297 mm) (Please read the note on the back ^ before filling this page)
3729twf.doc/008 A7 3729twf.doc/008 A7 經漭部中决枒準局妈工消於合作社印^ B7 五、發明説明（今） 的內介電層306，並使對應於物質層318之第一多晶矽層 3 l〇b與欲形成儲存電極的區域321保留一厚度Η。 請同時參照第4圖，其係爲第3G圖之上視圖，其中俯視 薄氧化層312a的形狀爲一圓形，外圍由內介電層310b呈環 狀包圍，而間隙壁320亦呈環狀緊鄰並包圍住薄氧化層3 12a 與第一多晶矽層310b，其外圍再由內介電層306包圍住。 請參照第3H圖，去除間隙壁320及薄氧化層3 12a，形成 一雙柱狀結構的第一多晶矽層310b，完成由第一多晶矽層 3 10b所架構的雙柱狀儲存電極，並在半導體基底300上形成 介電層322以及上電極324覆蓋住儲存電極，其中介電層322 例如可爲氧化矽層、氮化矽/氧化矽(NO)層、氧化矽/氮化 砂/氧化砂層（Oxide/Nitride/Oxide layer; ΟΝΟ)或五氧化二 鉬(Ta205)層。 本發明的主要特徵，在提供一種動態隨機存取記憶體 雙柱式電容，且藉著雙柱狀的幾何表面以增加電容器的表 面積，因此其電容値亦即其電荷儲存量，較傳統電容爲大， 且形成雙柱狀結構僅需使用一光阻層爲罩幕，簡化製程。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 --------------,η------ 一- (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度珀用中國國家標準（CNS ) Λ4規格（210X297公釐）3729twf.doc / 008 A7 3729twf.doc / 008 A7 The Ministry of Economic Affairs decided that the quasi-bureau ’s mother should be printed by the cooperative ^ B7 V. The inner dielectric layer 306 of the invention description (present) and the corresponding layer 318 of the material layer 318 The first polycrystalline silicon layer 3 10b and the region 321 where the storage electrode is to be formed have a thickness of Η. Please refer to FIG. 4 at the same time, which is a top view of FIG. 3G, in which the shape of the thin oxide layer 312a in a plan view is a circle, the periphery is surrounded by the inner dielectric layer 310b in a ring shape, and the partition wall 320 is also in a ring shape. The thin oxide layer 312a and the first polycrystalline silicon layer 310b are immediately adjacent and surrounded, and the periphery thereof is surrounded by the inner dielectric layer 306. Referring to FIG. 3H, the spacer 320 and the thin oxide layer 3 12a are removed to form a first columnar structure of the first polycrystalline silicon layer 310b, and the double columnar storage electrode structured by the first polycrystalline silicon layer 3 10b is completed. A dielectric layer 322 and an upper electrode 324 are formed on the semiconductor substrate 300 to cover the storage electrode. The dielectric layer 322 may be, for example, a silicon oxide layer, a silicon nitride / silicon oxide (NO) layer, or a silicon oxide / sand nitride. / Oxide sand layer (Oxide / Nitride / Oxide layer; ONO) or a layer of molybdenum pentoxide (Ta205). The main feature of the present invention is to provide a dual-cylinder capacitor of dynamic random access memory, and to increase the surface area of the capacitor by the dual-cylinder geometric surface. Therefore, its capacitance 値 is its charge storage capacity. It is large, and only a photoresist layer is required to form a double-column structure, which simplifies the manufacturing process. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. --------------, η ------ One-(Please read the notes on the back before filling in this page) The paper standard uses the Chinese National Standard (CNS) Λ4 specification (210X297 mm)