JPH1126717A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the period for development by forming the lower electrode having a crown structure in consideration of the embedding limit of an upper electrode, the resolution limit of photolithography technology and the minimum processing dimension. SOLUTION: The lower electrode having a crown structure is considered as the lower electrode which does not use a rough-surface conducting film, as the lower electrode which uses the rough-surface conducting film only for an inner film, as the lower electrode which uses the rough-surface conducting film only for an outer wall, and as the lower electrode which uses the rough-surface conducting film for both the inner wall and the outer wall. When the defective operation of an information storing capacitor element caused by the insufficient deposition of the conducting film of the upper electrode is caused by the inner short circuit and the occurrence of the leakage of the stored electric charge caused by the insufficient outer space between the lower electrodes is caused by the outer short circuit, the limited value of the inner short circuit and the limited value of the outer short circuit are obtained by computation. The photo-lithography limits of a concave crown and a convex crown are obtained by computation. The limits are corrected by the minimum processing dimension. The optimum height of the lower electrode and the inner space are indicated with thick solid lines.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for manufacturing a semiconductor integrated circuit device, and more particularly to a DRAM having an information storage capacitor constituted by a lower electrode having a crown structure.
(Dynamic Random Access Memory) and a technique effective when applied to a semiconductor integrated circuit device.

[0002]

2. Description of the Related Art In one of semiconductor integrated circuit devices, a memory cell is a memory cell selecting MISFET (Metal Insulator).
There is a DRAM composed of a semiconductor field effect transistor) and an information storage capacitor. But D
The RAM has a problem that the memory cell is miniaturized with the increase in the capacity, the amount of charge stored in the information storage capacitor element is reduced, and the information retention characteristic is deteriorated.

Therefore, in a DRAM of 64 Mbit or more, a capacitor over bit line (Capacitor Over B) in which an information storage capacitor is arranged above a bit line.
It has an itline (COB) structure, and the lower electrode has a three-dimensional shape such as a crown structure or a fin structure, thereby increasing the surface area to increase the amount of accumulated charges.

The lower electrode having a crown structure is described in, for example, “Super LSI Memory” published by Baifukan in January 1994.
It is published on January 5, published by Kiyo Ito, p.19.

However, DR of 256 Mbit or more
In AM, even if a lower electrode having a crown structure is adopted, the height of the lower electrode must be 1 μm in order to obtain a required amount of accumulated charge.
m, which makes it difficult to process the lower electrode. Therefore, a method of roughening the surface of the lower electrode of the crown structure to increase the effective surface area of the lower electrode, and increasing the amount of accumulated charge within a range in which the height of the lower electrode of the crown structure can be processed has been studied.

An information storage capacitor using a rough conductive film on the surface of a conductive film forming a lower electrode having a crown structure is described in, for example, I.E.D.M.
rnational Electron Device Meetings. "A High-Capaci
tor (20.4 fF / μm) with Ultrathin CVD-Ta2O5 Films
Deposited on Rugged Poly-Si for High Density DRAM
s "PP.263-266, 1992).

[0007]

SUMMARY OF THE INVENTION In developing an information storage capacitor using a rough conductive film on the surface of the conductive film constituting the lower electrode of the crown structure, the present inventors have identified the following problems. I found it.

That is, the use of the rough conductive film makes it possible to reduce the height of the lower electrode of the crown structure. However, by miniaturizing the memory cell, the protrusions on the surface of the rough conductive film become adjacent. There is a possibility that a short circuit occurs between the lower electrodes. To prevent this, there is a process and layout restriction that the layout interval between adjacent lower electrodes must be increased. Therefore, in order to utilize the effect that the height of the lower electrode of the crown structure can be reduced by using the rough surface conductive film, it is necessary to optimize the formation process and the minimum processing size of the lower electrode of the crown structure. However, since the formation process is complicated, it takes a lot of time to optimize the formation process and the minimum processing size of the lower electrode having the crown structure.

An object of the present invention is to provide a technique capable of shortening the development period of a semiconductor integrated circuit device having a DRAM.

Another object of the present invention is to provide a technique capable of simultaneously realizing high reliability and high integration of a semiconductor integrated circuit device having a DRAM.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, according to the method of manufacturing a semiconductor integrated circuit device of the present invention, a DRAM having an information storage capacitance element composed of a lower electrode having a crown structure and an upper electrode provided with a capacitance insulating film interposed therebetween is formed. In the relationship between the height of the lower electrode and the minimum processing size of the lower electrode, the optimum height of the lower electrode obtained by adding at least the embedding limit of the upper electrode and the resolution limit of the photolithography technology and The lower electrode having the crown structure is formed by using an optimum minimum processing size of the lower electrode.

According to the above means, the process window can be quantified by clarifying the relationship between the height of the lower electrode and the minimum processing size of the lower electrode, and the process of forming the information storage capacitor element can be performed. Can be efficiently selected.

Further, the optimum height of the lower electrode and the minimum processing size of the optimum lower electrode for forming the lower electrode having the crown structure are clarified, and thus the height of the lower electrode is optimized by optimizing the height of the lower electrode. It is possible to miniaturize the memory cell by reducing the size and optimizing the minimum processing size.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and their repeated description will be omitted.

The optimization of the dimensions of the lower electrode of the crown structure constituting the information storage capacitor according to an embodiment of the present invention will be described with reference to FIG.

FIG. 1 is a graph showing the relationship between the height (h) of the lower electrode of the crown structure and the inner space (A-2t ₁ -a).

As the lower electrode of the crown structure, (1)
A lower electrode having a crown structure without using a rough conductive film, (2)
A crown structure lower electrode using a rough conductive film only on the inner wall; (3) a crown structure lower electrode using the rough conductive film only on the outer wall; and (4) a crown structure using the rough conductive film on both the inner and outer walls. In the figure, the height of the lower electrode required for each lower electrode to obtain a storage capacitance of 30 fF is shown.

The relationship between the height of the lower electrode of the crown structure and the inner space shown in FIG. 1 is obtained by the following equations (1) to (1) representing the effective effective area of the lower electrode of each crown structure.
Equations (1) to (12) are obtained based on the plan and cross-sectional views of the lower electrode of each crown structure shown in FIGS. 2 to 5. Was.

In the equations (1) to (12), S ₁ is the effective effective area of the outer wall of the lower electrode of the crown structure, S ₂ is the effective effective area of the inner wall of the lower electrode of the crown structure, and S ₃ is the effective area of the crown electrode. This is the effective effective area of the bottom surface of the lower electrode.

A is the short side length of the memory cell, B is the long side length of the memory cell, a and b are the distances between adjacent lower electrodes,
t ₁ is the thickness of the side wall of the lower electrode, t ₂ is the thickness of the bottom surface of the lower electrode, t ₄ is the thickness of the rough conductive film, r is the curvature of the lower electrode,
AEF is an effect of increasing the surface area of the lower electrode by using a rough conductive film.

Each numerical value substituted into the equations (1) to (12) is a general value in the semiconductor technology. For example, the short side length (A) and the long side length (B) of the memory cell are each 0.45.
μm and 0.90 μm, the thickness (t ₁ ) of the side wall of the lower electrode is 50 ± 5 nm, the thickness (t ₂ ) of the bottom surface of the lower electrode is 50 nm, and the thickness (t ₃ ) of the capacitive insulating film is 15 μm.
± 1.5 nm, thickness (t ₄ ) of rough conductive film is 30 ± 3 nm
It is. Further, the effect of enlarging the surface area of the lower electrode by roughening (AEF) was set to 1.6. The curvature (r) of the lower electrode is represented by r = (A-a) / 2. It is assumed that a <b.

In a lower electrode having a crown structure without using a rough conductive film, the following equation is used: S ₁ = (A−a−2r) × h × 2 + (B−b−2r) × h × 2 + 2πr × h (2) S ₂ = (A−a−2r) × (ht− ₂ ) × 2 + (B−b−2r) × (ht− ₂ ) × 2 + 2π (rt− ₁ ) × (h− t ₂ ) Equation (3) S ₃ = (A−a−2t ₁ ) × (B−b−2r) + (A−a−2r) × (r−t ₁ ) + π (r−t ₁ ) ² Become. However, when the curvature (r) of the lower electrode is smaller than the thickness (t ₁ ) of the side wall of the lower electrode, the third term of the equation (2) and the second and third terms of the equation (3) become zero.

For a lower electrode having a crown structure in which a rough conductive film is used only for the inner wall, the following equation (4) is obtained. S ₁ = (A−a−2r) × h × 2 + (B−b−2r) × h × 2 + 2πr × h Equation (5) S ₂ = [(A−a−2r) × (ht ₂ −t ₄ ) × 2 + (B−b−2r) × (ht ₂ −t ₄ ) × 2 + 2π ( _{r-t 1 -t 4) ×} (h-t 2 -t 4)] × AEF formula _{(6) S 3 = [(} A-a-2t 1 -2t 4) × (B-b-2r) + ( A−a−2r) × (rt ₁ −t ₄ ) + π (rt ₁ −t ₄ ) ² ] × AEF. However, if the curvature of the lower electrode (r) <the thickness of the sidewall of the lower electrode (t1) + Somenshirubedenmaku thickness of (t _4), the third term of the formula (5) (6) The second and third terms are 0
Becomes

In the lower electrode having a crown structure in which the rough conductive film is used only for the outer wall, the following equation is obtained: S ₁ = [(A−a−2r) × h × 2 + (B−b−2r) × h × 2 + 2π] (R + t4) × h] × AEF Equation (8) S ₂ = (A−a−2r) × (ht− ₂ ) × 2 + (B−b−2r) × (ht− ₂ ) × 2 + 2π ( rt ₁ ) × (ht ₂ ) Equation (9) S ₃ = (A−a−2t ₁ ) × (B−b−2r) + (A−a−2r) × (r−t 1) + π (Rt1) ² . However, when the curvature (r) of the lower electrode is smaller than the thickness (t1) of the side wall of the lower electrode, the third term of the equation (8) and the second and third terms of the equation (9) become zero.

In a lower electrode having a crown structure in which a rough conductive film is used on both the inner wall and the outer wall, the following equation is obtained: S ₁ = [(A−a−2r) × h × 2 + (B−b−2r) × h × 2 + 2π (r + t ₄ ) × h] × AEF Equation (11) S ₂ = [(A−a−2r) × (ht− ₂₋ t ₄ ) × 2 + (B−b−2r) × (h −t ₂ −t ₄ ) × 2 + 2π (rt ₁ −t ₄ ) × (ht ₂ −t ₄ )] × AEF Equation (12) S ₃ = [(A−a−2t ₁ −2t ₄₎ ) × (Bb−2r) + (A−a−2r) × (rt ₁ −t ₄ ) + π (rt ₁ −t ₄ ) ² ] × AEF. However, when the curvature of the lower electrode (r) <the thickness of the side wall of the lower electrode (t ₁ ) + the thickness of the rough conductive film (t ₄ ), the third term of the equation (11) and the equation (12) Are the second and third terms.

By the way, the relationship between the height of the lower electrode of the crown structure and the inner space shown in FIG. 1 is further restricted by short circuit, photolithography and process.

First, the short limit will be described.

If the space inside the lower electrode of the crown structure is small, the capacity insulating film deposited on the inner wall further reduces the size of the inside space by twice the film thickness of the capacity insulating film, so that the conductive film forming the upper electrode is formed. Cannot be sufficiently deposited to the bottom inside the lower electrode, and the storage capacity is reduced, so that the operation as designed as an information storage capacitor cannot be performed (hereinafter, referred to as an inner short circuit).

The above inner short limit is expressed by the following equation (13).

Equation (13) Aa−2t ₁ ′ −2t ₃ ′> c where t ₁ ′ is the upper limit of the thickness of the sidewall of the lower electrode,
t ₃ ′ is a standard upper limit value of the thickness of the capacitive insulating film, and c is an upper electrode embedding limit. By substituting the general value of the semiconductor technology into the equation (13), the distance a between the adjacent lower electrodes is obtained, and the inner short circuit is obtained from the distance a obtained by the equation (13) and the following equation (14). The limit Li is obtained.

In FIG. 1, the upper electrode embedding limit value c = 50 nm is used.

Equation (14) Li = A-a-2t ₁ Similarly, if the outer space between the adjacent lower electrodes of the crown structure is small, the conductive film forming the upper electrode cannot be deposited, and the space between the adjacent memory cells cannot be formed. , A leak of accumulated charge occurs (hereinafter referred to as an outer short circuit).

The above outer short limit is expressed by the following equation (15).

Equation (15) a−2t ₃ ′> c By substituting the general value of the semiconductor technology into Equation (15), the distance a between adjacent lower electrodes is obtained, and is obtained by Equation (15). The outer short limit Lo is obtained from the short side length a and the following equation (16).

Formula (16) Lo = A−a−2t _{1 In} the case of a crown structure lower electrode using a rough conductive film,
Due to the projections on the surface of the rough conductive film, the film thickness deposited on the inner or outer wall of the lower electrode further increases, and the range in which a lower electrode having a crown structure can be formed by preventing an inner short or an outer short is narrowed.

The inner short-circuit limit in the case of the crown structure lower electrode using the rough conductive film is expressed by the following equation (17).

Equation (17) Aa−2t ₁ ′ −2t ₄ ′ −2t ₃ ′> c Here, t4 ′ is a standard upper limit value of the thickness of the rough conductive film. By substituting the general value of the semiconductor technology into Equation (17), the distance a between adjacent lower electrodes is obtained,
The inner short-circuit limit Li is obtained from the distance a obtained by the expression (17) and the expression (14).

Similarly, the outer short-circuit limit in the case of a crown structure lower electrode using a rough conductive film is expressed by the following equation (1).
8).

Equation (18) a−2t ₄ ′ −2t ₃ ′> c By substituting general values of semiconductor technology into equation (18), the distance a between adjacent lower electrodes is obtained, and the equation (18) is obtained. An outer short-circuit limit Lo is obtained from the short side length a obtained in 18) and the equation (16).

FIG. 1 shows the inner short-circuit limit and the outer short-circuit limit in the case of a crown-structured lower electrode using no roughened conductive film, and the inner short-circuit limit in the case of a crown-shaped lower electrode using a roughened conductive film. And the outer short limit respectively.

Next, regarding the limit of photolithography,
This will be described with reference to FIGS.

The method for forming the lower electrode having the crown structure includes:
There are a concave crown forming method and a convex crown forming method.
In the concave crown forming method, as shown in FIG. 6, a hole pattern is formed in a pseudo film (for example, a silicon oxide film) having a height equal to the height of the crown structure lower electrode, and the lower electrode is formed inside the hole pattern. Is formed.
Therefore, the resolution of the hole diameter (A-a) and the distance (a or b) between adjacent holes when the hole diameter is increased
Is the photolithography limit in the concave crown forming method.

In the convex crown method, as shown in FIG. 7, a line pattern is formed on a pseudo film having a height equal to the height of the lower electrode of the crown structure, and a lower electrode is formed outside the line pattern. Form electrodes. Therefore, the resolution of the line width (A-a-2t ₁ ) and the distance between adjacent lines (a + 2t ₁ or b when the line width is increased)
The resolution of + 2t ₁ ) is the limit of photolithography in the convex crown forming method.

FIG. 1 shows the photolithographic limit in the concave crown forming method and the photolithographic limit in the convex crown forming method. The values used in FIG. 1 are on the assumption that a <b, where a ≧ 0.14 μm and A−a ≧ 0.25 μm for the concave crown, and A−a2t ₁ ≧ 0.21 μm and a + 2t for the convex crown. ₁ ≧ 0.2
1 μm.

Note that it is impossible to apply the rough conductive film only to the outer wall in the concave crown forming method due to process restrictions. Conversely, in the convex crown forming method, the rough conductive film is applied to the inner wall. It is impossible to apply only to.

FIG. 1 showing the relationship between the height of the lower electrode of the crown structure and the inner space obtained by using the formulas (1) to (12) is shown in FIG. By adding a process constraint, an optimum lower electrode height and an optimum inner space of the lower electrode can be obtained for each of the crown structure lower electrodes. In the figure, the range of the optimum height of the lower electrode and the space inside the optimum lower electrode is indicated by a thick solid line.
Further, Table 1 summarizes the range of the optimum lower electrode height and the optimum lower electrode inner space shown in FIG.

[0050]

[Table 1]

That is, in the case of a crown-shaped lower electrode not using a roughened conductive film, the optimum lower electrode height in the concave crown formation method is 1.04 to 0.93 μm, and the optimum inner space of the lower electrode is: 0.14 to 0.21 μm. Also,
The optimum height of the lower electrode in the convex crown formation method is 0.9
6 ~ 0.86μm, optimal inner space of lower electrode is 0.1
9 to 0.25 μm.

In the case of a crown-structured lower electrode using a rough conductive film, the optimum lower electrode height is 0.82 in the concave crown forming method using the rough conductive film only on the inner wall of the lower electrode.
~ 0.74μm, optimal inner space of lower electrode is 0.16
The optimum height of the lower electrode is 0.65 to 0.60 μm in the concave crown forming method in which the rough conductive film is used on both the inner and outer walls of the lower electrode, and the optimum inner side of the lower electrode. The space is between 0.16 and 0.20 μm. However, in the concave crown forming method using the rough conductive film only for the outer wall of the lower electrode, there is no optimum range of the lower electrode height and the optimum inner space of the lower electrode.

Also, in the convex crown forming method, the optimum lower electrode height and the optimum inner space of the lower electrode are used in any case where the rough conductive film is used only for the inner wall of the lower electrode, only the outer wall, or the inner and outer walls. Does not exist.

Next, a method for manufacturing a lower electrode having a crown structure, which does not use a rough conductive film formed by the above-described concave crown forming method, will be described with reference to cross-sectional views of essential parts of a semiconductor substrate shown in FIGS. .

First, as shown in FIG. 8, after an element isolation groove 5 is formed on a main surface of a semiconductor substrate 1 made of p ^- type silicon single crystal, subsequently, p-type wells 11, n are formed by a well-known method.
A mold well 12 and a gate oxide film 13 are sequentially formed. Next, a gate electrode 14 is formed on the gate oxide film 13.
A, 14B and 14C are formed. The gate electrode 14A is
It constitutes a part of the memory cell selection MISFET, and functions as a word line WL in a region other than the active region. The gate electrode 14B and the gate electrode 14C are an n-channel MISFET and a p-channel MISFET of a peripheral circuit.
To form a part.

The gate electrodes 14A, 14B and 14C have a film thickness of 7 doped with an n-type impurity such as P (phosphorus).
A polycrystalline silicon film of about 0 nm is formed on the semiconductor substrate 1 by CV.
Then, a WN (tungsten nitride) film having a thickness of about 50 nm and a W film having a thickness of about 100 nm are deposited thereon by a sputtering method, and a 150 nm thick film is further deposited thereon. After the silicon nitride film 15 is deposited by the CVD method, the film is formed by patterning these films using a photoresist film (not shown) as a mask.

Next, after removing the photoresist film, a p-type impurity such as B (boron) is added to the n-type well 12.
Is implanted to form ap ⁻ type semiconductor region 17 in the n type well 12 on both sides of the gate electrode 14C. Also, p
An n-type impurity, for example, P (phosphorus) is ion-implanted into the p-type well 11 on both sides of the gate electrode 14B.
Then, an n ⁻ type semiconductor region 18 is formed, and an n type semiconductor region 19 is formed in the p type well 11 on both sides of the gate electrode 14A. Thereby, the memory cell selection MI is stored in the memory array.
The SFET Qs is formed.

Next, as shown in FIG. 9, after a silicon nitride film 20 having a thickness of about 50 nm is deposited on the semiconductor substrate 1 by the CVD method, the silicon nitride film 20 of the memory array is covered with a photoresist film 21. Peripheral circuit silicon nitride film 2
0 is anisotropically etched to form the gate electrode 14.
Sidewall spacers 20a are formed on the side walls of B and 14C.

Next, after removing the photoresist film 21, as shown in FIG. 10, the n-type well 1 in the peripheral circuit region is formed.
2 is ion-implanted with a p-type impurity, for example, B (boron) to form ap ⁺ -type semiconductor region 22 of a p-channel MISFET.
(Source, drain) are formed, and an n-type impurity, for example, As (arsenic) is ion-implanted into the p-type well 11 in the peripheral circuit region to form an n ⁺ -type semiconductor region 23 (source, drain) of the n-channel MISFET. I do. This allows
P channel type MISFETs Qp and n
A channel type MISFET Qn is formed.

Next, an SOG (spin-on-glass) film 24 having a thickness of about 300 nm is spin-coated on the semiconductor substrate 1, and then the semiconductor substrate 1 is heat-treated at 800.degree.
The OG film 24 is sintered (baked).

Next, as shown in FIG.
After a silicon oxide film 25 having a thickness of about 600 nm is deposited on the upper surface of the substrate, the silicon oxide film 25 is polished by a chemical mechanical polishing (CMP) method to planarize the surface. The surface of the silicon oxide film 25 in the peripheral circuit region after the CMP has a slightly lower shape (dishing) than the surface of the silicon oxide film 25 in the memory array. This is because the gate pattern density in the peripheral circuit region is lower than the gate pattern density in the memory array. The silicon oxide film 25 is deposited by, for example, a plasma CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas.

Next, a film thickness of 1 is formed on the silicon oxide film 25.
A silicon oxide film 26 of about 00 nm is deposited. The silicon oxide film 26 is deposited in order to repair fine scratches on the surface of the silicon oxide film 25 generated when the silicon oxide film 25 is polished by the CMP method. The surface of the silicon oxide film 26 is deposited along the surface of the silicon oxide film 25. The silicon oxide film 26 is deposited by, for example, a plasma CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas. A PSG (Phospho Silicon) is formed on the silicon oxide film 25 instead of the silicon oxide film 26.
(cate Glass) film may be deposited.

Next, a memory cell selecting MIS is performed by dry etching using a photoresist film (not shown) as a mask.
FET Qs n-type semiconductor region 19 (source, drain)
Oxide films 26 and 25 and SOG film 24 on top of
Is removed.

Subsequently, as shown in FIG. 12, the silicon nitride film 15 on the n-type semiconductor region 19 (source, drain) of the memory cell selecting MISFET Qs and the gate oxide are formed by dry etching using the photoresist film as a mask. By removing the film 13 and the n-type semiconductor region 19
A contact hole 28 is formed on one upper portion of the (source, drain), and a contact hole 29 is formed on the other upper portion.

Next, after removing the photoresist film, plugs 30 are formed in the contact holes 28 and 29. The plug 30 is formed by depositing a polycrystalline silicon film doped with an n-type impurity (for example, P (phosphorus)) on the silicon oxide film 26 by a CVD method, and polishing the polycrystalline silicon film by a CMP method to form a contact hole. It is formed by leaving inside of 28 and 29.

Next, as shown in FIG. 13, a silicon oxide film 3 having a thickness of about 200 nm is formed on the silicon oxide film 26.
After depositing the semiconductor substrate 1, the semiconductor substrate 1 is heat-treated at about 800.degree. The silicon oxide film 31 is deposited by, for example, a plasma CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas. Further, by this heat treatment, n in the polycrystalline silicon film forming plug 30 is removed.
Type impurity is supplied from the bottom of the contact holes 28 and 29 to the n-type semiconductor region 19 of the memory cell selecting MISFET Qs.
(Source, drain), and the resistance of the n-type semiconductor region 19 is reduced.

Next, the surface of the plug 30 is exposed by removing the silicon oxide film 31 above the contact hole 28 by dry etching using the photoresist film 32 as a mask.

The silicon oxide film 26 shown in FIG.
In the figure, the peripheral circuit region is thicker than the memory array. However, actually, the silicon oxide film 3 is formed on the surface step of the silicon oxide film 26 shown in FIG.
1 and a photoresist film 32 are deposited.

Next, after removing the photoresist film 32, as shown in FIG. 14, the silicon oxide films 31, 26, 25, the SOG film 24 and the silicon oxide films in the peripheral circuit region are dry-etched using the photoresist film 33 as a mask. By removing the gate oxide film 13, the n-channel MISFE
Contact holes 34 and 35 are formed above the n ⁺ type semiconductor region 23 (source and drain) of TQn, and contact holes 36 and 37 are formed above the p ⁺ type semiconductor region 22 (source and drain) of the p-channel MISFET Qp. Form.

Next, after removing the photoresist film 33, a bit line BL and first layer wirings 38 and 39 of the peripheral circuit are formed on the silicon oxide film 31, as shown in FIG. The bit line BL and the first layer wirings 38 and 39 are
For example, a Ti film having a thickness of about 50 nm and a TiN film having a thickness of about 50 nm are deposited on the silicon oxide film 31 by a sputtering method, and a W film having a thickness of about 150 nm and silicon nitride having a thickness of about 200 nm are further formed thereon. The membrane 40 and C
After deposition by the VD method, these films are formed by patterning these films using the photoresist film 41 as a mask.

After a Ti film is deposited on the silicon oxide film 31, the semiconductor substrate 1 is subjected to a heat treatment at about 800 ° C., whereby the Ti film reacts with the Si substrate, and the n-channel M
A low-resistance TiSi ₂ (titanium silicide) layer 42 is formed on the surface of the n ⁺ type semiconductor region 23 (source, drain) of the ISFET Qn and the surface of the p ⁺ type semiconductor region 22 (source, drain) of the p-channel MISFET Qp. You. Thereby, the contact resistance of the wiring (bit line BL, first layer wirings 38 and 39) connected to n ⁺ type semiconductor region 23 and P ⁺ type semiconductor region 22 can be reduced. Further, since the bit line BL is composed of the W film / TiN film / Ti film, the sheet resistance can be reduced to 2 Ω / □ or less, so that the bit line BL and the first layer wirings 38 and 39 of the peripheral circuit are connected. They can be formed simultaneously in the same step.

Next, after removing the photoresist film 41, a sidewall spacer 43 is formed on the side wall of the bit line BL and the first layer wirings 38 and 39 as shown in FIG. The side wall spacer 43 is connected to the bit line BL
After a silicon nitride film is deposited on the first layer wirings 38 and 39 by the CVD method, the silicon nitride film is formed by anisotropic etching.

Next, as shown in FIG.
Then, after spin-coating an SOG film 44 having a thickness of about 300 nm on the first layer wirings 38 and 39, the semiconductor substrate 1 is heat-treated at 800 ° C. for about 1 minute to sinter (sinter) the SOG film 44.

Next, as shown in FIG.
After a silicon oxide film 45 having a thickness of about 600 nm is deposited on the upper surface of the silicon oxide film 45, the silicon oxide film 45 is polished by a CMP method to planarize the surface. The silicon oxide film 45 is made of, for example, ozone (O ₃ ) and tetraethoxysilane (TEOS).
Are deposited by a plasma CVD method using a source gas.

Next, a film thickness of 1 is formed on the silicon oxide film 45.
A silicon oxide film 46 of about 00 nm is deposited. The silicon oxide film 46 is deposited to repair fine scratches on the surface of the silicon oxide film 45 generated when the silicon oxide film 45 is polished by the CMP method. The silicon oxide film 46 is deposited by, for example, a plasma CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas.

Next, the silicon oxide films 46 and 45, the SOG film 44 and the silicon oxide film 31 above the contact hole 29 are removed by dry etching using a photoresist (not shown) film as a mask, and the surface of the plug 30 is removed. Is formed.

Next, after removing the photoresist film, a plug 49 is formed inside the through hole 48 as shown in FIG. The plug 49 is made of the silicon oxide film 4
6 is formed by depositing a polycrystalline silicon film doped with an n-type impurity (for example, P (phosphorus)) by CVD, and then etching back the polycrystalline silicon film to leave inside the through hole 48. .

Next, as shown in FIG. 20, a silicon nitride film 5 having a thickness of about 100 nm is formed on the silicon oxide film 46.
Then, the silicon nitride film 51 in the peripheral circuit region is removed by dry etching using the photoresist film 52 as a mask. The silicon nitride film 51 remaining in the memory array is used as an etching stopper when etching a silicon oxide film between the lower electrodes in a step of forming a lower electrode of the information storage capacitor element described later.

Next, after removing the photoresist film 52, as shown in FIG. 21, a silicon oxide film 53 having a thickness of about 1.0 μm is deposited on the silicon nitride film 51, and the photoresist film 54 is masked. By removing the silicon oxide film 53 and the silicon nitride film 51 by the dry etching described above, a groove 55 is formed above the through hole 48. At the same time, a frame-like groove 55a surrounding the memory array is formed around the memory array. The silicon oxide film 53 is formed, for example, by plasma CVD using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas.
It is deposited by the method.

Next, after removing the photoresist film 54, as shown in FIG. 22, an n-type impurity (for example, P (phosphorus))-doped film thickness 50 is formed on the silicon oxide film 53.
A polycrystalline silicon film 56 of about nm is deposited by a CVD method. This polycrystalline silicon film 56 is used as a lower electrode material of the information storage capacitor.

Next, an SO film is formed on the polycrystalline silicon film 56.
The G film 57 is spin-coated. The film thickness is about 0.3 μm.
The grooves 55 and 55a are embedded by the flow of the OG.
As shown in FIG. 23, the SOG film 57 is etched back,
Further, the polycrystalline silicon film 5 on the silicon oxide film 53
By etching back 5, the polycrystalline silicon film 56 is left inside the grooves 55 and 55 a (the inner wall and the bottom).

Next, as shown in FIG. 24, using the photoresist film 58 covering the silicon oxide film 53 in the peripheral circuit region as a mask, the SOG film 57 inside the groove 55 and the silicon oxide film 53 in the gap between the groove 55 are wet. The lower electrode 60 having a crown structure of the information storage capacitor is formed by etching. At this time, since the silicon nitride film 51 remains in the gap between the trenches 55, the silicon oxide film 46 thereunder is not etched. One end of the photoresist film 58 covering the silicon oxide film 53 in the peripheral circuit region is disposed at a boundary between the lower electrode 60 formed on the outermost side of the memory array and the peripheral circuit region, that is, above the groove 55a. . By doing so, even if misalignment occurs at the end of the photoresist film 58, the SOG film 5 is formed inside the groove 55 of the lower electrode 60 formed on the outermost side of the memory array.
7 does not remain, and the silicon oxide film 53 in the peripheral circuit region is not etched.

The lower electrode 60 having the crown structure formed as described above has a height of 1.04 to 0.93 μm and a height of 0.14 to 0.93 μm.
It has an inner space of 0.21 μm.

Next, in order to remove the photoresist film 58 and then prevent the polycrystalline silicon film 56 constituting the lower electrode 60 from being oxidized, the semiconductor substrate 1 is heat-treated at about 800 ° C. in an ammonia atmosphere. After nitriding the surface of the crystalline silicon film 56, as shown in FIG.
A Ta ₂ O ₅ (tantalum oxide) film 61 having a thickness of about 15 nm is deposited on the upper surface of the substrate by a CVD method, and then the semiconductor substrate 1 is heat-treated at about 800 ° C. to repair the defect of the Ta ₂ O ₅ film 61. This Ta ₂ O ₅ film 61 is used as a material of a capacitive insulating film of the information storage capacitor.

Next, after a TiN film 62 having a thickness of about 150 nm is deposited on the Ta ₂ O ₅ film 61 by a CVD method and a sputtering method, the TiN film 62 and the TiN film 62 are formed by dry etching using a photoresist film 63 as a mask. By patterning the Ta ₂ O ₅ film 61, information composed of an upper electrode made of the TiN film 62, a capacitance insulating film made of the Ta ₂ O ₅ film 61, and a lower electrode 60 made of the polycrystalline silicon film 56. The storage capacitor C is formed. Thus, the DRA composed of the memory cell selecting MISFET Qs and the information storage capacitor C connected in series to the MISFET Qs
M memory cells are completed.

Next, a method of manufacturing a lower electrode having a crown structure without using a rough conductive film formed by the above-described method of forming a convex crown will be described with reference to cross-sectional views of essential parts of a semiconductor substrate shown in FIGS. explain.

First, in the same manner as in the manufacturing method shown in FIGS.
ETQs and n-channel MISFETQ of peripheral circuit
After forming the n and p channel MISFETs Qp, the bit lines BL and the first layer wirings 38 and 39 are formed.

Next, as shown in FIG.
After a silicon oxide film 45 having a thickness of about 600 nm is deposited on the upper surface of the silicon oxide film 45, the silicon oxide film 45 is polished by a CMP method to planarize the surface. The silicon oxide film 45 is made of, for example, ozone (O ₃ ) and tetraethoxysilane (TEOS).
Are deposited by a plasma CVD method using a source gas.
Next, a silicon nitride film 64 having a thickness of about 100 nm is deposited on the silicon oxide film 45.

Next, the silicon nitride film 64, the silicon oxide film 45, and the silicon oxide film 45 above the contact hole 29 are dry-etched using a photoresist (not shown) film as a mask.
The G film 44 and the silicon oxide film 31 are removed to remove the plug 3
A through hole 48 reaching the surface of the zero is formed.

Next, after removing the photoresist film, a plug 49 is formed inside the through hole 48.
The plug 49 is formed by depositing a polycrystalline silicon film doped with an n-type impurity (for example, P (phosphorus)) on the silicon nitride film 64 by a CVD method, and then etching back the polycrystalline silicon film to form a through hole 48. It is formed by leaving it inside. Next, a polycrystalline silicon film 65 having a thickness of about 50 nm doped with an n-type impurity (for example, P (phosphorus)) is deposited on the silicon nitride film 64. This polycrystalline silicon film 65 is used as a part of the lower electrode material of the information storage capacitor.

Next, as shown in FIG. 27, a silicon oxide film 6 having a thickness of about 1.0 μm is formed on the polycrystalline silicon film 65.
6 is deposited, and the silicon oxide film 66 and the polycrystalline silicon film 65 are removed by dry etching using the photoresist film 67 as a mask, thereby forming columns 68 made of the silicon oxide film 66 above the through holes 48. The silicon oxide film 66 is deposited by, for example, a plasma CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas.

Next, after removing the photoresist film 67, as shown in FIG. 28, an upper portion of the silicon oxide film 66 is doped with an n-type impurity (for example, P (phosphorus)) to a thickness of 50 nm.
A polycrystalline silicon film 69 of about ± 5 nm is deposited by a CVD method. This polycrystalline silicon film 69 is used as another part of the lower electrode material of the information storage capacitor.

Next, as shown in FIG. 29, the polycrystalline silicon film 69 above the silicon oxide film 66 is etched back to leave the polycrystalline silicon film 69 on the side walls of the pillar 68. Next, as shown in FIG. 30, the silicon oxide film 66 constituting the pillar 68 is wet-etched to form the lower electrode 70 of the information storage capacitor. At this time, since the silicon nitride film 64 remains under the polycrystalline silicon films 65 and 69, the silicon oxide film 45 thereunder is not etched.

The lower electrode 70 having the crown structure thus formed has a height of 0.96 to 0.86 μm and a height of 0.14 to 0.86 μm.
It has an inner space of 0.21 μm.

Thereafter, in order to prevent oxidation of the polycrystalline silicon films 65 and 69 constituting the lower electrode 60, the semiconductor substrate 1 is heat-treated at about 800 ° C. in an ammonia atmosphere to form the polycrystalline silicon films 65 and 69. after nitriding the surface, the Ta ₂ O ₅ (tantalum oxide) film 61 upper portion having a thickness of about 15nm of the lower electrode 70 is deposited by CVD, and then Ta ₂ O ₅ and the semiconductor substrate 1 is heat-treated at about 800 ° C. The defect of the film 61 is repaired.

Next, after a TiN film 62 having a thickness of about 150 nm is deposited on the Ta ₂ O ₅ film 61 by the CVD method and the sputtering method, the TiN film 62 and the Ta ₂ O ₅ film 6 are deposited.
1 is patterned to form an upper electrode made of a TiN film 62, a capacitance insulating film made of a Ta ₂ O ₅ film 61, and a lower electrode 70 made of polycrystalline silicon films 65 and 69.
Are formed.

Next, a method of manufacturing a lower electrode having a crown structure using a rough conductive film formed on the inner wall by the above-described concave crown forming method will be described with reference to the cross-sectional views of the main parts of a semiconductor substrate shown in FIGS. Will be explained.

First, in the same manner as in the manufacturing method shown in FIGS.
ETQs and n-channel MISFETQ of peripheral circuit
After forming the n and p channel MISFETs Qp, the bit lines BL and the first layer wirings 38 and 39 are formed, and then the silicon oxide film 5 deposited on the silicon oxide film 46 is formed.
3 and the silicon nitride film 51 are removed to form a groove 55 above the through hole 48.

Next, as shown in FIG. 31, an approximately 50 nm-thick polycrystalline silicon film 56 doped with an n-type impurity (for example, P (phosphorus)) is formed on the silicon oxide film 53 by CV.
After the deposition by the method D, a polycrystalline silicon film 71 having a thickness of about 30 ± 3 nm is formed on the surface of the polycrystalline silicon film 56. These polycrystalline silicon films 56 and 71
Is used as a lower electrode material of an information storage capacitor.

Next, an SO film is formed on the polycrystalline silicon film 71.
The G film 57 is spin-coated. The film thickness is about 0.3 μm.
The grooves 55 and 55a are embedded by the flow of the OG.
As shown in FIG. 32, the SOG film 57 is etched back,
Further, as shown in FIG. 33, the polycrystalline silicon films 71, 56 on the silicon oxide film 53 are etched back, so that the polycrystalline silicon films 56, 71 are formed inside (the inner wall and the bottom) of the grooves 55, 55a. leave.

Next, as shown in FIG. 34, with the photoresist film 58 covering the silicon oxide film 53 in the peripheral circuit region as a mask, the SOG film 57 inside the groove 55 and the silicon oxide film 53 in the gap between the groove 55 are wet. By etching, a lower electrode 72 having a crown structure of the information storage capacitor is formed.

The crown-shaped lower electrode 72 thus formed has a height of 0.82 to 0.74 μm and a height of 0.16 to 0.74 μm.
It has an inner space of 21 μm.

Next, the photoresist film 58 is removed, and then the polycrystalline silicon films 56 and 7 constituting the lower electrode 72 are formed.
In order to prevent oxidation of the semiconductor substrate 1, the semiconductor substrate 1 is heat-treated at about 800 ° C. in an ammonia atmosphere to nitride the surfaces of the polycrystalline silicon films 56 and 71, and then a Ta film having a thickness of about 15 nm is formed on the lower electrode 72. ₂ O ₅ (tantalum oxide) film 61
Is deposited by the CVD method, and then the semiconductor substrate 1 is heat-treated at about 800 ° C. to repair the defect of the Ta ₂ O ₅ film 61. This Ta ₂ O ₅ film 61 is used as a material of a capacitive insulating film of the information storage capacitor.

Next, after a TiN film 62 having a thickness of about 150 nm is deposited on the Ta ₂ O ₅ film 61 by a CVD method and a sputtering method, the TiN film 62 and the TiN film 62 are formed by dry etching using a photoresist film 63 as a mask. By patterning the Ta ₂ O ₅ film 61, an upper electrode made of the TiN film 62, a capacitance insulating film made of the Ta ₂ O ₅ film 61, and a lower electrode made of the polycrystalline silicon films 56 and 71 are formed. An information storage capacitor is formed.

Next, a method of manufacturing a lower electrode having a crown structure using the rough surface conductive film formed by the above-described concave crown forming method for the inner and outer walls will be described with reference to the cross-sectional view of the principal part of the semiconductor substrate shown in FIG. explain.

First, in the same manner as the manufacturing method shown in FIGS.
ETQs and n-channel MISFETQ of peripheral circuit
After forming the n and p channel MISFETs Qp, a bit line BL, first layer wirings 38 and 39, and a polycrystalline silicon film 56 having a crown structure are formed.

Next, as shown in FIG. 35, a roughened polycrystalline silicon film 71 having a thickness of about 30 ± 3 nm is selectively formed on the surface of the polycrystalline silicon film 56 to form an information storage capacitor. The lower electrode 73 having a crown structure is formed.

The crown-structured lower electrode 73 thus formed has a height of 0.65 to 0.60 μm and a height of 0.16 to 0.60 μm.
It has an inner space of 20 μm.

Next, in order to prevent oxidation of the polycrystalline silicon films 56 and 71 forming the lower electrode 73, the semiconductor substrate 1 is heat-treated at about 800 ° C. in an ammonia atmosphere to form the polycrystalline silicon films 56 and 71. after nitriding the surface, the Ta ₂ O ₅ (tantalum oxide) film 61 upper portion having a thickness of about 20nm of the lower electrode 73 is deposited by CVD, and then Ta ₂ O ₅ and the semiconductor substrate 1 is heat-treated at about 800 ° C. The defect of the film 61 is repaired.

Next, after a TiN film 62 having a thickness of about 150 nm is deposited on the Ta ₂ O ₅ film 61 by a CVD method and a sputtering method, the TiN film 62 and the TiN film 62 are formed by dry etching using a photoresist film 63 as a mask. By patterning the Ta ₂ O ₅ film 61, an upper electrode made of the TiN film 62, a capacitance insulating film made of the Ta ₂ O ₅ film 61, and a lower electrode made of the polycrystalline silicon films 56 and 71 are formed. An information storage capacitor is formed.

As described above, according to the above-described embodiment, the process window can be quantified by clarifying the relationship between the height of the lower electrode of the crown structure and the inner space, and the information storage capacitor can be quantified. The respective processes for forming the lower electrode, the capacitor insulating film, and the upper electrode constituting the element can be efficiently selected. further,
By adding a short limit, a photolithography limit, and a process constraint to the relationship between the height of the crown structure lower electrode and the inner space, the optimum lower electrode height and the optimum lower electrode inner space are reduced. Accordingly, the height of the lower electrode can be reduced by optimizing the height of the lower electrode, and the memory cell can be miniaturized by optimizing the space inside the lower electrode.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in the above embodiment, the case where the lower electrode is applied to the lower electrode having a crown structure necessary for obtaining a storage capacitance of 30 fF has been described. However, the lower electrode can be applied to the lower electrode having a crown structure having any storage capacitance. It is.

[0114]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the present invention, it is possible to quantify the process window by clarifying the relationship between the height of the lower electrode and the minimum processing size of the lower electrode. Since the formation process can be selected efficiently, the development period of a DRAM having an information storage capacitor having a crown structure lower electrode can be shortened.

(2) According to the present invention, the height of the lower electrode can be reduced by optimizing the height of the lower electrode, and the memory cell can be miniaturized by optimizing the minimum processing size.
At the same time, the processing accuracy in the wiring process is improved and the reliability of the DRAM can be increased, and at the same time, the integration of the DRAM can be increased.

[Brief description of the drawings]

FIG. 1 is a graph showing the relationship between the height of a lower electrode having a crown structure and an inner space.

FIG. 2A is a plan view of a lower electrode without a rough conductive film used for obtaining an effective effective area of a lower electrode having a crown structure, and FIG. 2B is a II ′ of FIG. It is principal part sectional drawing in a line.

FIG. 3A is a plan view of a lower electrode using only a rough conductive film for the inner wall used for obtaining an effective effective area of the lower electrode of the crown structure, and FIG. 3B is a plan view of I of FIG. It is principal part sectional drawing in the -I 'line.

FIG. 4A is a plan view of a lower electrode using only a rough conductive film for an outer wall used for obtaining an effective effective area of the lower electrode having a crown structure, and FIG. 4B is a plan view of I of FIG. It is principal part sectional drawing in the -I 'line.

FIG. 5A is a plan view of a lower electrode in which a rough conductive film used for obtaining an effective effective area of a lower electrode having a crown structure is used on both inner and outer walls, and FIG. ) I-
It is principal part sectional drawing in the I 'line.

6A is a plan view of a lower electrode of a crown structure for explaining a photolithography limit in the concave crown forming method, and FIG. 6B is a cross-sectional view of a main part taken along line II ′ of FIG. It is.

FIG. 7A is a plan view of a lower electrode of a crown structure for explaining a photolithography limit in a convex crown forming method, and FIG. 7B is a cross-sectional view of a main part taken along line II ′ of FIG. FIG.

FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the information storage capacitor of the DRAM according to one embodiment of the present invention;

FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the information storage capacitor of the DRAM according to one embodiment of the present invention;

FIG. 10 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the information storage capacitor of the DRAM according to one embodiment of the present invention;

FIG. 11 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the information storage capacitor of the DRAM according to one embodiment of the present invention;

FIG. 12 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the information storage capacitor of the DRAM according to an embodiment of the present invention;

FIG. 13 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the information storage capacitor of the DRAM according to an embodiment of the present invention;

14 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the information storage capacitor of the DRAM according to one embodiment of the present invention; FIG.

FIG. 15 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the information storage capacitor of the DRAM according to one embodiment of the present invention;

FIG. 16 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the information storage capacitor of the DRAM according to an embodiment of the present invention;

FIG. 17 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the information storage capacitor of the DRAM according to an embodiment of the present invention;

FIG. 18 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the information storage capacitor of the DRAM according to an embodiment of the present invention;

FIG. 19 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the information storage capacitor of the DRAM according to an embodiment of the present invention;

20 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the information storage capacitor of the DRAM according to an embodiment of the present invention; FIG.

FIG. 21 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the information storage capacitor of the DRAM according to an embodiment of the present invention;

FIG. 22 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the information storage capacitor of the DRAM according to an embodiment of the present invention;

FIG. 23 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the information storage capacitor of the DRAM according to an embodiment of the present invention;

24 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the information storage capacitor of the DRAM according to an embodiment of the present invention; FIG.

FIG. 25 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the information storage capacitor of the DRAM according to an embodiment of the present invention;

FIG. 26 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the information storage capacitor of the DRAM according to an embodiment of the present invention;

FIG. 27 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the information storage capacitor of the DRAM according to an embodiment of the present invention;

FIG. 28 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the information storage capacitor of the DRAM according to an embodiment of the present invention;

29 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the information storage capacitor of the DRAM according to an embodiment of the present invention; FIG.

FIG. 30 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the information storage capacitor of the DRAM according to an embodiment of the present invention;

FIG. 31 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the information storage capacitor of the DRAM according to an embodiment of the present invention;

FIG. 32 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the information storage capacitor of the DRAM according to an embodiment of the present invention;

FIG. 33 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the information storage capacitor of the DRAM according to an embodiment of the present invention;

34 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the information storage capacitor of the DRAM according to an embodiment of the present invention; FIG.

FIG. 35 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the information storage capacitor of the DRAM according to an embodiment of the present invention;

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 5 element isolation groove 11 p-type well 12 n-type well 13 gate oxide film 14A gate electrode 14B gate electrode 14C gate electrode 15 silicon nitride film 17 p ^- type semiconductor region 18 n ^- type semiconductor region 19 n-type semiconductor region 20 Silicon nitride film 21 Photoresist film 20a Side wall spacer 22 p ⁺ type semiconductor region 23 n ⁺ type semiconductor region 24 SOG film 25 silicon oxide film 26 silicon oxide film 28 contact hole 29 contact hole 30 plug 31 silicon oxide film 32 photoresist film 33 the photoresist film 34 contact hole 35 the contact hole 36 the contact hole 37 the contact hole 38 first layer wiring 39 first layer wiring 40 silicon film 41 a photoresist film 42 TiSi ₂ layer 43 is nitrided Wall spacer 44 SOG film 45 Silicon oxide film 46 Silicon oxide film 48 Through hole 49 Plug 51 Silicon nitride film 52 Photoresist film 53 Silicon oxide film 54 Photoresist film 55 Groove 55a Groove 56 Polycrystalline silicon film 57 SOG film 58 Photoresist Film 60 lower electrode 61 Ta ₂ O ₅ film 62 TiN film 63 photoresist film 64 silicon nitride film 65 polycrystalline silicon film 66 silicon oxide film 67 photoresist film 68 pillar 69 polycrystalline silicon film 70 lower electrode 71 polycrystalline silicon film 72 Lower electrode 73 Lower electrode A Short side length of memory cell B Long side length of memory cell a Distance between adjacent lower electrodes b Distance between adjacent lower electrodes t ₁ Thickness of side wall of lower electrode t ₂ Bottom surface of lower electrode Thickness t ₄ Thickness of rough conductive film r Lower electrode H of lower electrode Qs MISFET for memory cell selection Qn n-channel MISFET Qp p-channel MISFET BL bit line C information storage capacitor

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Satoru Yamada 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Yoshitaka Nakamura 5-2-1, Josuihoncho, Kodaira-shi, Tokyo (72) Inventor, Isamu Asano 2326 Imai, Ome-shi, Tokyo In-house Hitachi, Ltd.Device Development Center (72) Hitachi, Ltd. Device Development Center

Claims (7)

[Claims] 1. A method for manufacturing a semiconductor integrated circuit device for forming a DRAM having an information storage capacitance element constituted by a lower electrode having a crown structure and an upper electrode provided with a capacitance insulating film interposed therebetween, An optimum lower electrode height and an optimum lower electrode minimum obtained by adding at least the embedding limit of the upper electrode and the resolution limit of the photolithography technology to the relationship between the height of the lower electrode and the minimum processing size of the lower electrode. A method of manufacturing a semiconductor integrated circuit device, wherein a lower electrode having the crown structure is formed using a processing dimension. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the minimum processing dimension of the lower electrode is a space inside the lower electrode. 3. A method of manufacturing a semiconductor integrated circuit device for forming a DRAM having an information storage capacitance element constituted by a lower electrode having a crown structure and an upper electrode provided with a capacitance insulating film interposed therebetween. (a) forming a memory cell selecting MISFET on a semiconductor substrate; and (b) forming a bit line connected to one semiconductor region of the memory cell selecting MISFET on the semiconductor substrate.
(c) forming a first insulating film on the semiconductor substrate and then forming a buried wiring connected to the other semiconductor region of the memory cell selecting MISFET; and (d) forming a buried wiring on the semiconductor substrate. (E) sequentially depositing a second insulating film and a third insulating film, and then sequentially processing the third insulating film and the second insulating film to form a groove reaching the embedded wiring; A) sequentially depositing a conductive film and a fourth insulating film on the semiconductor substrate and then burying the fourth insulating film in the trench by etch-back; and (f) removing the exposed conductive film. Then, by removing the fourth insulating film in the trench in the memory cell region, the height constituted by the conductive film is 1.04 to 0.93 μm, and the inner space is 0.14 to 0.93. Forming a lower electrode having a crown structure of 21 μm; (g). The method of manufacturing a semiconductor integrated circuit device characterized by a step of sequentially forming a capacitor insulating film and an upper electrode on the lower electrode of the emission structures. 4. A method of manufacturing a semiconductor integrated circuit device for forming a DRAM having an information storage capacitor constituted by a lower electrode having a crown structure and an upper electrode provided with a capacitor insulating film interposed therebetween. (a) forming a memory cell selecting MISFET on a semiconductor substrate; and (b) forming a bit line connected to one semiconductor region of the memory cell selecting MISFET on the semiconductor substrate. (C) forming a first insulating film and a second insulating film on the semiconductor substrate sequentially, and then forming the memory cell selecting MIS;
Forming a buried interconnect connected to the other semiconductor region of the FET; and (d) sequentially depositing a first conductive film and a third insulating film on the semiconductor substrate; Processing the first conductive film sequentially to form a column formed by the first conductive film and the third insulating film in contact with the embedded wiring; and (e) forming a column on the semiconductor substrate. After depositing a second conductive film, leaving the second conductive film on the side wall of the pillar by etch back;
(f). By removing the third insulating film constituting the pillar, the height constituted by the first conductive film and the second conductive film is 0.96 to 0.86 μm, Forming a lower electrode having a crown structure having a space of 0.19 to 0.25 μm; and (g) sequentially forming a capacitor insulating film and an upper electrode on the lower electrode having the crown structure. Of manufacturing a semiconductor integrated circuit device. 5. A method of manufacturing a semiconductor integrated circuit device for forming a DRAM having an information storage capacitor constituted by a lower electrode having a crown structure and an upper electrode provided with a capacitor insulating film interposed therebetween. (a) forming a memory cell selecting MISFET on a semiconductor substrate; and (b) forming a bit line connected to one semiconductor region of the memory cell selecting MISFET on the semiconductor substrate.
(c) forming a first insulating film on the previous semiconductor substrate, and then forming a buried wiring connected to the other semiconductor region of the memory cell selecting MISFET; and (d). (E) sequentially depositing a second insulating film and a third insulating film, and then sequentially processing the third insulating film and the second insulating film to form a groove reaching the embedded wiring; A) depositing a conductive film on the semiconductor substrate, subsequently forming a rough conductive film on the surface of the conductive film, depositing a fourth insulating film on the semiconductor substrate, and then etching back Burying the fourth insulating film in the groove; and (f) removing the exposed rough conductive film and the conductive film, and then removing the fourth insulating film in the groove in the memory cell region. By doing so, it is constituted by the conductive film and the rough conductive film 0.82 ~ 0.74μm in height,
Forming a lower electrode having a crown structure with an inner space of 0.16 to 0.21 μm; and (g) sequentially forming a capacitive insulating film and an upper electrode on the lower electrode having the crown structure. A method for manufacturing a semiconductor integrated circuit device. 6. A method of manufacturing a semiconductor integrated circuit device for forming a DRAM having an information storage capacitance element constituted by a lower electrode having a crown structure and an upper electrode provided with a capacitance insulating film interposed therebetween, (a) forming a memory cell selecting MISFET on a semiconductor substrate; and (b) forming a bit line connected to one semiconductor region of the memory cell selecting MISFET on the semiconductor substrate. (C) forming a first insulating film on the semiconductor substrate and then forming a buried wiring connected to the other semiconductor region of the memory cell selecting MISFET; and (d) forming a buried wiring on the semiconductor substrate. Forming a groove reaching the buried wiring by sequentially processing the third insulating film and the second insulating film after sequentially depositing a second insulating film and a third insulating film, e). The semiconductor substrate Conductive film and on the fourth
(C) burying the fourth insulating film in the trench by etch-back after sequentially depositing the insulating film, and (f) removing the exposed conductive film and then removing the fourth insulating film. Then, by forming a rough conductive film on the surface of the conductive film, the height constituted by the conductive film and the rough conductive film is 0.65 to 0.60 μm, and the inner space is 0.16 to 0.66 μm. A semiconductor integrated circuit device comprising: a step of forming a lower electrode having a crown structure of 0.20 μm; and (g) a step of sequentially forming a capacitive insulating film and an upper electrode on the lower electrode having the crown structure. Manufacturing method. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 5, wherein said rough conductive film is made of a polycrystalline silicon film.