TW388811B - Out-of-pipeline trace buffer for instruction replay following misspeculation - Google Patents
Out-of-pipeline trace buffer for instruction replay following misspeculation Download PDFInfo
- Publication number
- TW388811B TW388811B TW087120952A TW87120952A TW388811B TW 388811 B TW388811 B TW 388811B TW 087120952 A TW087120952 A TW 087120952A TW 87120952 A TW87120952 A TW 87120952A TW 388811 B TW388811 B TW 388811B
- Authority
- TW
- Taiwan
- Prior art keywords
- instruction
- buffer
- line
- execution
- instructions
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
- G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1405—Saving, restoring, recovering or retrying at machine instruction level
- G06F11/1407—Checkpointing the instruction stream
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3842—Speculative instruction execution
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- Computer Hardware Design (AREA)
- Advance Control (AREA)
- Debugging And Monitoring (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/991,269 US6240509B1 (en) | 1997-12-16 | 1997-12-16 | Out-of-pipeline trace buffer for holding instructions that may be re-executed following misspeculation |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW388811B true TW388811B (en) | 2000-05-01 |
Family
ID=25537042
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW087120952A TW388811B (en) | 1997-12-16 | 1998-12-16 | Out-of-pipeline trace buffer for instruction replay following misspeculation |
Country Status (10)
| Country | Link |
|---|---|
| US (1) | US6240509B1 (enExample) |
| EP (1) | EP1040421B1 (enExample) |
| JP (1) | JP3971893B2 (enExample) |
| KR (1) | KR100382126B1 (enExample) |
| CN (1) | CN100342349C (enExample) |
| AU (1) | AU1911099A (enExample) |
| BR (1) | BR9814290A (enExample) |
| DE (1) | DE69829778T2 (enExample) |
| TW (1) | TW388811B (enExample) |
| WO (1) | WO1999031589A1 (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI559221B (zh) * | 2012-06-15 | 2016-11-21 | 軟體機器公司 | 實現從載入儲存重新排序與最佳化所導致的推測性轉送錯失預測/錯誤當中復原之方法及系統 |
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| US6772324B2 (en) | 1997-12-17 | 2004-08-03 | Intel Corporation | Processor having multiple program counters and trace buffers outside an execution pipeline |
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| AU1437300A (en) * | 1998-11-16 | 2000-06-05 | Telefonaktiebolaget Lm Ericsson (Publ) | Concurrent processing for event-based systems |
| SE9902373D0 (sv) * | 1998-11-16 | 1999-06-22 | Ericsson Telefon Ab L M | A processing system and method |
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| JP2001209535A (ja) * | 2000-01-27 | 2001-08-03 | Toshiba Corp | プロセッサの命令スケジューリング装置 |
| US6609247B1 (en) * | 2000-02-18 | 2003-08-19 | Hewlett-Packard Development Company | Method and apparatus for re-creating the trace of an emulated instruction set when executed on hardware native to a different instruction set field |
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| US6880069B1 (en) * | 2000-06-30 | 2005-04-12 | Intel Corporation | Replay instruction morphing |
| US6981129B1 (en) * | 2000-11-02 | 2005-12-27 | Intel Corporation | Breaking replay dependency loops in a processor using a rescheduled replay queue |
| US6877086B1 (en) * | 2000-11-02 | 2005-04-05 | Intel Corporation | Method and apparatus for rescheduling multiple micro-operations in a processor using a replay queue and a counter |
| US7207035B2 (en) * | 2001-08-23 | 2007-04-17 | International Business Machines Corporation | Apparatus and method for converting an instruction and data trace to an executable program |
| US7047395B2 (en) * | 2001-11-13 | 2006-05-16 | Intel Corporation | Reordering serial data in a system with parallel processing flows |
| US6950924B2 (en) * | 2002-01-02 | 2005-09-27 | Intel Corporation | Passing decoded instructions to both trace cache building engine and allocation module operating in trace cache or decoder reading state |
| CN100449478C (zh) * | 2002-05-31 | 2009-01-07 | 德拉华州大学 | 用于实时多线程处理的方法和装置 |
| US7941651B1 (en) | 2002-06-27 | 2011-05-10 | Intel Corporation | Method and apparatus for combining micro-operations to process immediate data |
| US7103751B1 (en) | 2002-06-27 | 2006-09-05 | Intel Corporation | Method and apparatus for representation of an address in canonical form |
| US7111148B1 (en) | 2002-06-27 | 2006-09-19 | Intel Corporation | Method and apparatus for compressing relative addresses |
| US7010665B1 (en) | 2002-06-27 | 2006-03-07 | Intel Corporation | Method and apparatus for decompressing relative addresses |
| US7194603B2 (en) * | 2003-04-23 | 2007-03-20 | International Business Machines Corporation | SMT flush arbitration |
| US20040225870A1 (en) * | 2003-05-07 | 2004-11-11 | Srinivasan Srikanth T. | Method and apparatus for reducing wrong path execution in a speculative multi-threaded processor |
| US20040255104A1 (en) * | 2003-06-12 | 2004-12-16 | Intel Corporation | Method and apparatus for recycling candidate branch outcomes after a wrong-path execution in a superscalar processor |
| CN100442244C (zh) * | 2004-05-12 | 2008-12-10 | Nxp股份有限公司 | 具有跟踪协处理器的数据处理设备、系统和方法 |
| US7496735B2 (en) * | 2004-11-22 | 2009-02-24 | Strandera Corporation | Method and apparatus for incremental commitment to architectural state in a microprocessor |
| US7508396B2 (en) | 2005-09-28 | 2009-03-24 | Silicon Integrated Systems Corp. | Register-collecting mechanism, method for performing the same and pixel processing system employing the same |
| US8219885B2 (en) * | 2006-05-12 | 2012-07-10 | Arm Limited | Error detecting and correcting mechanism for a register file |
| US20100306509A1 (en) * | 2009-05-29 | 2010-12-02 | Via Technologies, Inc. | Out-of-order execution microprocessor with reduced store collision load replay reduction |
| CN102567137B (zh) * | 2010-12-27 | 2013-09-25 | 北京国睿中数科技股份有限公司 | 在分支预测失败时使用rob恢复rat内容的系统和方法 |
| US9612934B2 (en) * | 2011-10-28 | 2017-04-04 | Cavium, Inc. | Network processor with distributed trace buffers |
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| US10209992B2 (en) | 2014-04-25 | 2019-02-19 | Avago Technologies International Sales Pte. Limited | System and method for branch prediction using two branch history tables and presetting a global branch history register |
| US9996354B2 (en) | 2015-01-09 | 2018-06-12 | International Business Machines Corporation | Instruction stream tracing of multi-threaded processors |
| CN104657145B (zh) * | 2015-03-09 | 2017-12-15 | 上海兆芯集成电路有限公司 | 用于微处理器的重发停靠的系统和方法 |
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-
1997
- 1997-12-16 US US08/991,269 patent/US6240509B1/en not_active Expired - Lifetime
-
1998
- 1998-12-11 DE DE69829778T patent/DE69829778T2/de not_active Expired - Lifetime
- 1998-12-11 BR BR9814290-9A patent/BR9814290A/pt not_active Application Discontinuation
- 1998-12-11 WO PCT/US1998/026408 patent/WO1999031589A1/en not_active Ceased
- 1998-12-11 AU AU19110/99A patent/AU1911099A/en not_active Abandoned
- 1998-12-11 JP JP2000539419A patent/JP3971893B2/ja not_active Expired - Fee Related
- 1998-12-11 KR KR10-2000-7006657A patent/KR100382126B1/ko not_active Expired - Fee Related
- 1998-12-11 EP EP98963873A patent/EP1040421B1/en not_active Expired - Lifetime
- 1998-12-11 CN CNB988136562A patent/CN100342349C/zh not_active Expired - Fee Related
- 1998-12-16 TW TW087120952A patent/TW388811B/zh not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI559221B (zh) * | 2012-06-15 | 2016-11-21 | 軟體機器公司 | 實現從載入儲存重新排序與最佳化所導致的推測性轉送錯失預測/錯誤當中復原之方法及系統 |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3971893B2 (ja) | 2007-09-05 |
| DE69829778T2 (de) | 2006-01-26 |
| AU1911099A (en) | 1999-07-05 |
| KR20010024750A (ko) | 2001-03-26 |
| HK1029194A1 (en) | 2001-03-23 |
| KR100382126B1 (ko) | 2003-05-09 |
| EP1040421B1 (en) | 2005-04-13 |
| US6240509B1 (en) | 2001-05-29 |
| JP2002508567A (ja) | 2002-03-19 |
| DE69829778D1 (de) | 2005-05-19 |
| WO1999031589A1 (en) | 1999-06-24 |
| EP1040421A1 (en) | 2000-10-04 |
| EP1040421A4 (en) | 2002-07-17 |
| BR9814290A (pt) | 2001-10-30 |
| CN100342349C (zh) | 2007-10-10 |
| CN1286771A (zh) | 2001-03-07 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GD4A | Issue of patent certificate for granted invention patent | ||
| MM4A | Annulment or lapse of patent due to non-payment of fees |