TW379416B - Method of manufacturing dual damascence - Google Patents

Method of manufacturing dual damascence Download PDF

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Publication number
TW379416B
TW379416B TW87106840A TW87106840A TW379416B TW 379416 B TW379416 B TW 379416B TW 87106840 A TW87106840 A TW 87106840A TW 87106840 A TW87106840 A TW 87106840A TW 379416 B TW379416 B TW 379416B
Authority
TW
Taiwan
Prior art keywords
layer
opening
manufacturing
oxide layer
scope
Prior art date
Application number
TW87106840A
Other languages
English (en)
Chinese (zh)
Inventor
Meng-Jin Tsai
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to TW87106840A priority Critical patent/TW379416B/zh
Priority to DE1998136379 priority patent/DE19836379A1/de
Priority to JP10228796A priority patent/JP2969109B1/ja
Priority to FR9810540A priority patent/FR2778268A1/fr
Application granted granted Critical
Publication of TW379416B publication Critical patent/TW379416B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/7681—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving one or more buried masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW87106840A 1998-05-04 1998-05-04 Method of manufacturing dual damascence TW379416B (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
TW87106840A TW379416B (en) 1998-05-04 1998-05-04 Method of manufacturing dual damascence
DE1998136379 DE19836379A1 (de) 1998-05-04 1998-08-11 Herstellungsverfahren durch Verwenden des Doppel-Damaszierungs-Verfahrens
JP10228796A JP2969109B1 (ja) 1998-05-04 1998-08-13 二重波型模様プロセスを使用した半導体装置の製造方法
FR9810540A FR2778268A1 (fr) 1998-05-04 1998-08-19 Procede de double incrustation pour la formation d'interconnexions dans un dispositif a semiconducteur

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW87106840A TW379416B (en) 1998-05-04 1998-05-04 Method of manufacturing dual damascence

Publications (1)

Publication Number Publication Date
TW379416B true TW379416B (en) 2000-01-11

Family

ID=21630030

Family Applications (1)

Application Number Title Priority Date Filing Date
TW87106840A TW379416B (en) 1998-05-04 1998-05-04 Method of manufacturing dual damascence

Country Status (4)

Country Link
JP (1) JP2969109B1 (ja)
DE (1) DE19836379A1 (ja)
FR (1) FR2778268A1 (ja)
TW (1) TW379416B (ja)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103295955B (zh) * 2012-03-02 2015-11-25 中芯国际集成电路制造(上海)有限公司 半导体结构的制造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5246884A (en) * 1991-10-30 1993-09-21 International Business Machines Corporation Cvd diamond or diamond-like carbon for chemical-mechanical polish etch stop
US5494854A (en) * 1994-08-17 1996-02-27 Texas Instruments Incorporated Enhancement in throughput and planarity during CMP using a dielectric stack containing HDP-SiO2 films
US6157083A (en) * 1996-06-03 2000-12-05 Nec Corporation Fluorine doping concentrations in a multi-structure semiconductor device

Also Published As

Publication number Publication date
JP2969109B1 (ja) 1999-11-02
FR2778268A1 (fr) 1999-11-05
DE19836379A1 (de) 1999-11-18
JPH11330243A (ja) 1999-11-30

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Legal Events

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GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees