TW375773B - Method for forming shallow junctions in semiconductor wafer - Google Patents

Method for forming shallow junctions in semiconductor wafer

Info

Publication number
TW375773B
TW375773B TW087107315A TW87107315A TW375773B TW 375773 B TW375773 B TW 375773B TW 087107315 A TW087107315 A TW 087107315A TW 87107315 A TW87107315 A TW 87107315A TW 375773 B TW375773 B TW 375773B
Authority
TW
Taiwan
Prior art keywords
semiconductor wafer
dopant material
fluorine
wafer
shallow junctions
Prior art date
Application number
TW087107315A
Other languages
English (en)
Inventor
Daniel F Downey
Original Assignee
Varian Associates
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Varian Associates filed Critical Varian Associates
Application granted granted Critical
Publication of TW375773B publication Critical patent/TW375773B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2658—Bombardment with radiation with high-energy radiation producing ion implantation of a molecular ion, e.g. decaborane

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Health & Medical Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Recrystallisation Techniques (AREA)
TW087107315A 1997-09-16 1998-05-12 Method for forming shallow junctions in semiconductor wafer TW375773B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/929,973 US6069062A (en) 1997-09-16 1997-09-16 Methods for forming shallow junctions in semiconductor wafers

Publications (1)

Publication Number Publication Date
TW375773B true TW375773B (en) 1999-12-01

Family

ID=25458773

Family Applications (1)

Application Number Title Priority Date Filing Date
TW087107315A TW375773B (en) 1997-09-16 1998-05-12 Method for forming shallow junctions in semiconductor wafer

Country Status (6)

Country Link
US (1) US6069062A (zh)
EP (1) EP1019952A1 (zh)
JP (1) JP4065661B2 (zh)
KR (1) KR100498657B1 (zh)
TW (1) TW375773B (zh)
WO (1) WO1999014799A1 (zh)

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US6551946B1 (en) 1999-06-24 2003-04-22 Agere Systems Inc. Two-step oxidation process for oxidizing a silicon substrate wherein the first step is carried out at a temperature below the viscoelastic temperature of silicon dioxide and the second step is carried out at a temperature above the viscoelastic temperature
US6521496B1 (en) 1999-06-24 2003-02-18 Lucent Technologies Inc. Non-volatile memory semiconductor device including a graded, grown, high quality control gate oxide layer and associated methods
US6670242B1 (en) * 1999-06-24 2003-12-30 Agere Systems Inc. Method for making an integrated circuit device including a graded, grown, high quality gate oxide layer and a nitride layer
US6395610B1 (en) 1999-06-24 2002-05-28 Lucent Technologies Inc. Method of making bipolar transistor semiconductor device including graded, grown, high quality oxide layer
US6509230B1 (en) 1999-06-24 2003-01-21 Lucent Technologies Inc. Non-volatile memory semiconductor device including a graded, grown, high quality oxide layer and associated methods
US6204157B1 (en) * 1999-12-07 2001-03-20 Advanced Micro Devices, Inc. Method for establishing shallow junction in semiconductor device to minimize junction capacitance
US20030235957A1 (en) * 2002-06-25 2003-12-25 Samir Chaudhry Method and structure for graded gate oxides on vertical and non-planar surfaces
US20020187614A1 (en) * 2001-04-16 2002-12-12 Downey Daniel F. Methods for forming ultrashallow junctions with low sheet resistance
US6849528B2 (en) * 2001-12-12 2005-02-01 Texas Instruments Incorporated Fabrication of ultra shallow junctions from a solid source with fluorine implantation
US6555439B1 (en) * 2001-12-18 2003-04-29 Advanced Micro Devices, Inc. Partial recrystallization of source/drain region before laser thermal annealing
US6544853B1 (en) * 2002-01-18 2003-04-08 Infineon Technologies Ag Reduction of negative bias temperature instability using fluorine implantation
US6780730B2 (en) * 2002-01-31 2004-08-24 Infineon Technologies Ag Reduction of negative bias temperature instability in narrow width PMOS using F2 implantation
US20030186519A1 (en) * 2002-04-01 2003-10-02 Downey Daniel F. Dopant diffusion and activation control with athermal annealing
US7135423B2 (en) 2002-05-09 2006-11-14 Varian Semiconductor Equipment Associates, Inc Methods for forming low resistivity, ultrashallow junctions with low damage
WO2003096397A1 (en) * 2002-05-10 2003-11-20 Varian Semiconductor Equipment Associates, Inc. Methods and systems for dopant profiling
US6699771B1 (en) * 2002-08-06 2004-03-02 Texas Instruments Incorporated Process for optimizing junctions formed by solid phase epitaxy
CN1253929C (zh) 2003-03-04 2006-04-26 松下电器产业株式会社 半导体装置及其制造方法
GB0305610D0 (en) * 2003-03-12 2003-04-16 Univ Southampton Methods for reducing dopant diffusion in semiconductor processes
US6808997B2 (en) * 2003-03-21 2004-10-26 Texas Instruments Incorporated Complementary junction-narrowing implants for ultra-shallow junctions
US20040191999A1 (en) * 2003-03-24 2004-09-30 Texas Instruments Incroporated Semiconductor structure and method of fabrication
US7163867B2 (en) * 2003-07-28 2007-01-16 International Business Machines Corporation Method for slowing down dopant-enhanced diffusion in substrates and devices fabricated therefrom
US6797555B1 (en) * 2003-09-10 2004-09-28 National Semiconductor Corporation Direct implantation of fluorine into the channel region of a PMOS device
CN1930663A (zh) * 2004-03-15 2007-03-14 皇家飞利浦电子股份有限公司 制造半导体器件的方法和用这种方法获得的半导体器件
EP1610371A1 (en) * 2004-06-24 2005-12-28 STMicroelectronics S.r.l. SiGe heterojunction bipolar transistors
US7163878B2 (en) * 2004-11-12 2007-01-16 Texas Instruments Incorporated Ultra-shallow arsenic junction formation in silicon germanium
US8076228B2 (en) * 2007-01-29 2011-12-13 Infineon Technologies Ag Low noise transistor and method of making same
JP2021034408A (ja) * 2019-08-15 2021-03-01 信越半導体株式会社 シリコン基板の熱処理方法

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US4584026A (en) * 1984-07-25 1986-04-22 Rca Corporation Ion-implantation of phosphorus, arsenic or boron by pre-amorphizing with fluorine ions
US4617066A (en) * 1984-11-26 1986-10-14 Hughes Aircraft Company Process of making semiconductors having shallow, hyperabrupt doped regions by implantation and two step annealing
JPH02237024A (ja) * 1988-07-12 1990-09-19 Seiko Epson Corp 半導体装置及びその製造方法
EP0350845A3 (en) * 1988-07-12 1991-05-29 Seiko Epson Corporation Semiconductor device with doped regions and method for manufacturing it
US5654209A (en) * 1988-07-12 1997-08-05 Seiko Epson Corporation Method of making N-type semiconductor region by implantation
JPH0368134A (ja) * 1989-08-05 1991-03-25 Mitsubishi Electric Corp 半導体装置の製造方法
JP2773957B2 (ja) * 1989-09-08 1998-07-09 富士通株式会社 半導体装置の製造方法
JPH03265131A (ja) * 1990-03-15 1991-11-26 Fujitsu Ltd 半導体装置の製造方法
US5108935A (en) * 1990-11-16 1992-04-28 Texas Instruments Incorporated Reduction of hot carrier effects in semiconductor devices by controlled scattering via the intentional introduction of impurities
JPH0521448A (ja) * 1991-07-10 1993-01-29 Sharp Corp 半導体装置の製造方法
US5466612A (en) * 1992-03-11 1995-11-14 Matsushita Electronics Corp. Method of manufacturing a solid-state image pickup device
JP3464247B2 (ja) * 1993-08-24 2003-11-05 株式会社東芝 半導体装置の製造方法
JPH0950970A (ja) * 1995-08-10 1997-02-18 Sony Corp 半導体装置の製造方法
US5897363A (en) * 1996-05-29 1999-04-27 Micron Technology, Inc. Shallow junction formation using multiple implant sources

Also Published As

Publication number Publication date
JP2001516969A (ja) 2001-10-02
JP4065661B2 (ja) 2008-03-26
EP1019952A1 (en) 2000-07-19
KR100498657B1 (ko) 2005-07-01
WO1999014799A1 (en) 1999-03-25
US6069062A (en) 2000-05-30
KR20010024040A (ko) 2001-03-26

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