TW370697B - Semiconductor package with offset die pad and method for manufacturing same - Google Patents
Semiconductor package with offset die pad and method for manufacturing sameInfo
- Publication number
- TW370697B TW370697B TW087100750A TW87100750A TW370697B TW 370697 B TW370697 B TW 370697B TW 087100750 A TW087100750 A TW 087100750A TW 87100750 A TW87100750 A TW 87100750A TW 370697 B TW370697 B TW 370697B
- Authority
- TW
- Taiwan
- Prior art keywords
- die pad
- semiconductor package
- manufacturing same
- die
- substrate
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/49531—Additional leads the additional leads being a wiring board
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US3763897P | 1997-01-21 | 1997-01-21 |
Publications (1)
Publication Number | Publication Date |
---|---|
TW370697B true TW370697B (en) | 1999-09-21 |
Family
ID=21895443
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW087100750A TW370697B (en) | 1997-01-21 | 1998-03-02 | Semiconductor package with offset die pad and method for manufacturing same |
Country Status (6)
Country | Link |
---|---|
US (1) | US6111315A (zh) |
EP (1) | EP0854513A3 (zh) |
JP (1) | JPH10256455A (zh) |
KR (1) | KR19980070675A (zh) |
SG (1) | SG91798A1 (zh) |
TW (1) | TW370697B (zh) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000150730A (ja) * | 1998-11-17 | 2000-05-30 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US6773965B2 (en) | 1999-05-25 | 2004-08-10 | Micron Technology, Inc. | Semiconductor device, ball grid array connection system, and method of making |
US6268650B1 (en) * | 1999-05-25 | 2001-07-31 | Micron Technology, Inc. | Semiconductor device, ball grid array connection system, and method of making |
US6544812B1 (en) * | 2000-11-06 | 2003-04-08 | St Assembly Test Service Ltd. | Single unit automated assembly of flex enhanced ball grid array packages |
US6509635B1 (en) | 2000-11-28 | 2003-01-21 | National Semiconductor Corporation | Integrated circuit package having offset die |
US20030205828A9 (en) * | 2001-04-05 | 2003-11-06 | Larry Kinsman | Circuit substrates, semiconductor packages, and ball grid arrays |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5196992A (en) * | 1989-08-25 | 1993-03-23 | Kabushiki Kaisha Toshiba | Resin sealing type semiconductor device in which a very small semiconductor chip is sealed in package with resin |
JPH04129253A (ja) * | 1990-09-20 | 1992-04-30 | Mitsubishi Electric Corp | 半導体パッケージ |
JPH0547979A (ja) * | 1991-08-21 | 1993-02-26 | Nec Corp | 樹脂封止型半導体装置 |
JP3226628B2 (ja) * | 1992-10-15 | 2001-11-05 | 三菱電機株式会社 | テープキャリア、それを用いた半導体装置及びその製造方法 |
JPH06268101A (ja) * | 1993-03-17 | 1994-09-22 | Hitachi Ltd | 半導体装置及びその製造方法、電子装置、リ−ドフレ−ム並びに実装基板 |
JPH0786458A (ja) * | 1993-09-09 | 1995-03-31 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP3226244B2 (ja) * | 1993-12-03 | 2001-11-05 | 株式会社東芝 | 樹脂封止型半導体装置 |
US5717252A (en) * | 1994-07-25 | 1998-02-10 | Mitsui High-Tec, Inc. | Solder-ball connected semiconductor device with a recessed chip mounting area |
US5586010A (en) * | 1995-03-13 | 1996-12-17 | Texas Instruments Incorporated | Low stress ball grid array package |
-
1997
- 1997-12-19 US US08/994,789 patent/US6111315A/en not_active Expired - Lifetime
-
1998
- 1998-01-17 SG SG9800128A patent/SG91798A1/en unknown
- 1998-01-19 EP EP98100825A patent/EP0854513A3/en not_active Withdrawn
- 1998-01-21 KR KR1019980001757A patent/KR19980070675A/ko not_active Application Discontinuation
- 1998-01-21 JP JP10009191A patent/JPH10256455A/ja active Pending
- 1998-03-02 TW TW087100750A patent/TW370697B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
SG91798A1 (en) | 2002-10-15 |
KR19980070675A (ko) | 1998-10-26 |
EP0854513A2 (en) | 1998-07-22 |
EP0854513A3 (en) | 2000-04-05 |
JPH10256455A (ja) | 1998-09-25 |
US6111315A (en) | 2000-08-29 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |