TW360962B - Chip with hybrid input/output slot structure - Google Patents
Chip with hybrid input/output slot structureInfo
- Publication number
- TW360962B TW360962B TW087102082A TW87102082A TW360962B TW 360962 B TW360962 B TW 360962B TW 087102082 A TW087102082 A TW 087102082A TW 87102082 A TW87102082 A TW 87102082A TW 360962 B TW360962 B TW 360962B
- Authority
- TW
- Taiwan
- Prior art keywords
- input
- output
- region
- chip
- slot structure
- Prior art date
Links
- 238000005457 optimization Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Coils Or Transformers For Communication (AREA)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW087102082A TW360962B (en) | 1998-02-16 | 1998-02-16 | Chip with hybrid input/output slot structure |
US09/065,471 US5945696A (en) | 1998-02-16 | 1998-04-23 | Silicon chip having mixed input/output slot structure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW087102082A TW360962B (en) | 1998-02-16 | 1998-02-16 | Chip with hybrid input/output slot structure |
Publications (1)
Publication Number | Publication Date |
---|---|
TW360962B true TW360962B (en) | 1999-06-11 |
Family
ID=21629507
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW087102082A TW360962B (en) | 1998-02-16 | 1998-02-16 | Chip with hybrid input/output slot structure |
Country Status (2)
Country | Link |
---|---|
US (1) | US5945696A (zh) |
TW (1) | TW360962B (zh) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6324677B1 (en) * | 1999-02-23 | 2001-11-27 | Agere Systems Guardian Corp. | Integrated circuit layout design |
US7939856B2 (en) * | 2004-12-31 | 2011-05-10 | Stmicroelectronics Pvt. Ltd. | Area-efficient distributed device structure for integrated voltage regulators |
US9135373B1 (en) | 2010-04-12 | 2015-09-15 | Cadence Design Systems, Inc. | Method and system for implementing an interface for I/O rings |
US8386981B1 (en) | 2010-04-12 | 2013-02-26 | Cadence Design Systems, Inc. | Method and systems for implementing I/O rings and die area estimations |
CN103383712B (zh) * | 2013-07-18 | 2016-01-06 | 中国兵器工业集团第二一四研究所苏州研发中心 | 一种优化焊盘位置减小芯片面积的集成电路版图设计方法 |
CN106653748B (zh) * | 2016-12-30 | 2019-09-06 | 合肥恒烁半导体有限公司 | 集成电路角落的使用方法 |
CN106783731B (zh) * | 2016-12-30 | 2019-09-06 | 合肥恒烁半导体有限公司 | 提升集成电路角落处硅片使用效率的方法 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0760855B2 (ja) * | 1987-09-07 | 1995-06-28 | 日本電気株式会社 | 集積回路装置 |
JPH02275653A (ja) * | 1989-04-17 | 1990-11-09 | Nec Corp | 半導体装置 |
JPH03138972A (ja) * | 1989-10-24 | 1991-06-13 | Fujitsu Ltd | 集積回路装置 |
JPH0415954A (ja) * | 1990-05-09 | 1992-01-21 | Mitsubishi Electric Corp | 半導体集積回路装置 |
JP2901156B2 (ja) * | 1990-08-31 | 1999-06-07 | 三菱電機株式会社 | 半導体集積回路装置 |
JP3137413B2 (ja) * | 1992-03-26 | 2001-02-19 | 株式会社東芝 | セミカスタム集積回路 |
JP3228583B2 (ja) * | 1992-03-31 | 2001-11-12 | 株式会社東芝 | 半導体集積回路装置 |
JP2855975B2 (ja) * | 1992-07-06 | 1999-02-10 | 富士通株式会社 | 半導体集積回路 |
US5552333A (en) * | 1994-09-16 | 1996-09-03 | Lsi Logic Corporation | Method for designing low profile variable width input/output cells |
US5641978A (en) * | 1995-07-07 | 1997-06-24 | Intel Corporation | Input/output buffer layout having overlapping buffers for reducing die area of pad-limited integrated circuit |
-
1998
- 1998-02-16 TW TW087102082A patent/TW360962B/zh not_active IP Right Cessation
- 1998-04-23 US US09/065,471 patent/US5945696A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US5945696A (en) | 1999-08-31 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MK4A | Expiration of patent term of an invention patent |