TW358919B - System and method for handling interrupt and exception events in an asymmetric multiprocessor architecture - Google Patents
System and method for handling interrupt and exception events in an asymmetric multiprocessor architectureInfo
- Publication number
- TW358919B TW358919B TW086111973A TW86111973A TW358919B TW 358919 B TW358919 B TW 358919B TW 086111973 A TW086111973 A TW 086111973A TW 86111973 A TW86111973 A TW 86111973A TW 358919 B TW358919 B TW 358919B
- Authority
- TW
- Taiwan
- Prior art keywords
- interrupt
- processor
- processors
- multiprocessor architecture
- exception events
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
- G06F7/5443—Sum of products
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/699,294 US6003129A (en) | 1996-08-19 | 1996-08-19 | System and method for handling interrupt and exception events in an asymmetric multiprocessor architecture |
Publications (1)
Publication Number | Publication Date |
---|---|
TW358919B true TW358919B (en) | 1999-05-21 |
Family
ID=24808708
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW086111973A TW358919B (en) | 1996-08-19 | 1997-08-19 | System and method for handling interrupt and exception events in an asymmetric multiprocessor architecture |
Country Status (7)
Country | Link |
---|---|
US (1) | US6003129A (zh) |
JP (1) | JPH10154080A (zh) |
KR (1) | KR100257520B1 (zh) |
CN (1) | CN1176437B (zh) |
DE (1) | DE19735870A1 (zh) |
FR (1) | FR2752470B1 (zh) |
TW (1) | TW358919B (zh) |
Families Citing this family (47)
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US6192073B1 (en) | 1996-08-19 | 2001-02-20 | Samsung Electronics Co., Ltd. | Methods and apparatus for processing video data |
US5850556A (en) * | 1996-12-26 | 1998-12-15 | Cypress Semiconductor Corp. | Interruptible state machine |
US6317638B1 (en) * | 1997-08-22 | 2001-11-13 | Honeywell Inc. | Multi-layer state machine for a hybrid real-time control system and method of operation thereof |
US6571206B1 (en) * | 1998-01-15 | 2003-05-27 | Phoenix Technologies Ltd. | Apparatus and method for emulating an I/O instruction for the correct processor and for servicing software SMI's in a multi-processor environment |
US6625693B2 (en) * | 1999-05-04 | 2003-09-23 | Intel Corporation | Fast exception processing |
DE50014621D1 (de) * | 1999-05-06 | 2007-10-18 | Siemens Ag | Kommunikationseinrichtung mit Mitteln zur Echtzeitverarbeitung von zu übertragenden Nutzdaten |
US7171547B1 (en) * | 1999-12-28 | 2007-01-30 | Intel Corporation | Method and apparatus to save processor architectural state for later process resumption |
US7080205B2 (en) * | 2000-03-29 | 2006-07-18 | Fujitsu Siemens Computer Gmbh | Arrangement and method for reducing the processing time of a data processing device |
DE10015693A1 (de) * | 2000-03-29 | 2001-10-18 | Fujitsu Siemens Computers Gmbh | Anordnung und Verfahren zur Reduzierung der Interruptverarbeitungszeit einer Datenverarbeitungseinrichtung |
US6704863B1 (en) * | 2000-06-14 | 2004-03-09 | Cypress Semiconductor Corp. | Low-latency DMA handling in pipelined processors |
JP2002108837A (ja) * | 2000-09-29 | 2002-04-12 | Nec Corp | 計算機システムとその計算制御方法 |
US20020099893A1 (en) * | 2001-01-24 | 2002-07-25 | Nguyen Tuyet-Huong Thi | System and method for the handling of system management interrupts in a multiprocessor computer system |
US6832338B2 (en) * | 2001-04-12 | 2004-12-14 | International Business Machines Corporation | Apparatus, method and computer program product for stopping processors without using non-maskable interrupts |
JP3843048B2 (ja) * | 2002-06-28 | 2006-11-08 | 富士通株式会社 | 分岐予測機構を有する情報処理装置 |
US7117284B2 (en) * | 2002-11-18 | 2006-10-03 | Arm Limited | Vectored interrupt control within a system having a secure domain and a non-secure domain |
GB0226905D0 (en) * | 2002-11-18 | 2002-12-24 | Advanced Risc Mach Ltd | Exception tyres within a secure processing system |
US20040215937A1 (en) * | 2003-04-23 | 2004-10-28 | International Business Machines Corporation | Dynamically share interrupt handling logic among multiple threads |
CA2430763A1 (en) | 2003-05-30 | 2004-11-30 | Ibm Canada Limited - Ibm Canada Limitee | Efficiently releasing locks when an exception occurs |
US7313790B2 (en) * | 2003-06-23 | 2007-12-25 | Intel Corporation | Methods and apparatus for preserving precise exceptions in code reordering by using control speculation |
US20050102457A1 (en) * | 2003-11-12 | 2005-05-12 | Dell Products L.P. | System and method for interrupt processing in a multiple processor system |
US7721024B2 (en) * | 2003-11-12 | 2010-05-18 | Dell Products L.P. | System and method for exiting from an interrupt mode in a multiple processor system |
US7529914B2 (en) * | 2004-06-30 | 2009-05-05 | Intel Corporation | Method and apparatus for speculative execution of uncontended lock instructions |
US7487503B2 (en) | 2004-08-12 | 2009-02-03 | International Business Machines Corporation | Scheduling threads in a multiprocessor computer |
US8020141B2 (en) | 2004-12-06 | 2011-09-13 | Microsoft Corporation | Operating-system process construction |
JP4148223B2 (ja) * | 2005-01-28 | 2008-09-10 | セイコーエプソン株式会社 | プロセッサおよび情報処理方法 |
JP2006243838A (ja) * | 2005-02-28 | 2006-09-14 | Toshiba Corp | プログラム開発装置 |
US8849968B2 (en) | 2005-06-20 | 2014-09-30 | Microsoft Corporation | Secure and stable hosting of third-party extensions to web services |
US7447874B1 (en) * | 2005-10-18 | 2008-11-04 | Qlogic, Corporation | Method and system for designing a flexible hardware state machine |
US8074231B2 (en) * | 2005-10-26 | 2011-12-06 | Microsoft Corporation | Configuration of isolated extensions and device drivers |
KR100807039B1 (ko) * | 2006-04-07 | 2008-02-25 | 주식회사 퓨쳐시스템 | 비대칭 다중 프로세싱 시스템 및 그 방법 |
US8032898B2 (en) * | 2006-06-30 | 2011-10-04 | Microsoft Corporation | Kernel interface with categorized kernel objects |
CN100449495C (zh) * | 2006-08-25 | 2009-01-07 | 华为技术有限公司 | 一种辅助cpu对芯片进行驱动的系统及方法 |
US20080244507A1 (en) * | 2007-03-30 | 2008-10-02 | Microsoft Corporation | Homogeneous Programming For Heterogeneous Multiprocessor Systems |
US8789063B2 (en) | 2007-03-30 | 2014-07-22 | Microsoft Corporation | Master and subordinate operating system kernels for heterogeneous multiprocessor systems |
DE102007025397B4 (de) * | 2007-05-31 | 2010-07-15 | Advanced Micro Devices, Inc., Sunnyvale | System mit mehreren Prozessoren und Verfahren zu seinem Betrieb |
JP2009251802A (ja) * | 2008-04-03 | 2009-10-29 | Panasonic Corp | マルチプロセッサシステムおよびマルチプロセッサシステムの割込み制御方法 |
KR101717494B1 (ko) * | 2010-10-08 | 2017-03-28 | 삼성전자주식회사 | 인터럽트 처리 장치 및 방법 |
US10110891B2 (en) * | 2011-09-29 | 2018-10-23 | Sharp Kabushiki Kaisha | Image decoding device, image decoding method, and image encoding device |
GB2495959A (en) * | 2011-10-26 | 2013-05-01 | Imagination Tech Ltd | Multi-threaded memory access processor |
WO2013106210A1 (en) * | 2012-01-10 | 2013-07-18 | Intel Corporation | Electronic apparatus having parallel memory banks |
US9405551B2 (en) * | 2013-03-12 | 2016-08-02 | Intel Corporation | Creating an isolated execution environment in a co-designed processor |
US20160147536A1 (en) * | 2014-11-24 | 2016-05-26 | International Business Machines Corporation | Transitioning the Processor Core from Thread to Lane Mode and Enabling Data Transfer Between the Two Modes |
CN107436752B (zh) * | 2017-07-20 | 2020-12-01 | 龙芯中科技术有限公司 | 异常现场恢复方法、装置及计算机可读存储介质 |
CN108037951B (zh) * | 2017-12-27 | 2020-11-20 | 山东师范大学 | 一种dtp处理器的中断快速切换方法及装置 |
CN108845969B (zh) * | 2018-03-28 | 2021-09-10 | 核工业理化工程研究院 | 适用于不完全对称多处理微控制器的操作控制方法及操作系统 |
GB2579617B (en) * | 2018-12-06 | 2021-01-27 | Advanced Risc Mach Ltd | An apparatus and method for handling exception causing events |
CN115167933B (zh) * | 2022-09-08 | 2022-12-02 | 深圳市恒运昌真空技术有限公司 | 一种双处理器设备及其控制方法和处理器 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5274825A (en) * | 1987-09-03 | 1993-12-28 | Bull Hn Information Systems Inc. | Microprocessor vectored interrupts |
US5182811A (en) * | 1987-10-02 | 1993-01-26 | Mitsubishi Denki Kabushiki Kaisha | Exception, interrupt, and trap handling apparatus which fetches addressing and context data using a single instruction following an interrupt |
JP2858140B2 (ja) * | 1988-10-19 | 1999-02-17 | アポロ・コンピューター・インコーポレーテッド | パイプラインプロセッサ装置および方法 |
US5218711A (en) * | 1989-05-15 | 1993-06-08 | Mitsubishi Denki Kabushiki Kaisha | Microprocessor having program counter registers for its coprocessors |
US5278647A (en) * | 1992-08-05 | 1994-01-11 | At&T Bell Laboratories | Video decoder using adaptive macroblock leak signals |
US5319753A (en) * | 1992-09-29 | 1994-06-07 | Zilog, Inc. | Queued interrupt mechanism with supplementary command/status/message information |
US5576765A (en) * | 1994-03-17 | 1996-11-19 | International Business Machines, Corporation | Video decoder |
US5510842A (en) * | 1994-05-04 | 1996-04-23 | Matsushita Electric Corporation Of America | Parallel architecture for a high definition television video decoder having multiple independent frame memories |
US5729279A (en) * | 1995-01-26 | 1998-03-17 | Spectravision, Inc. | Video distribution system |
US5594905A (en) * | 1995-04-12 | 1997-01-14 | Microsoft Corporation | Exception handler and method for handling interrupts |
US5668599A (en) * | 1996-03-19 | 1997-09-16 | International Business Machines Corporation | Memory management for an MPEG2 compliant decoder |
-
1996
- 1996-08-19 US US08/699,294 patent/US6003129A/en not_active Expired - Lifetime
-
1997
- 1997-04-07 KR KR1019970012760A patent/KR100257520B1/ko not_active IP Right Cessation
- 1997-08-14 JP JP9219649A patent/JPH10154080A/ja active Pending
- 1997-08-15 CN CN971160481A patent/CN1176437B/zh not_active Expired - Fee Related
- 1997-08-18 DE DE19735870A patent/DE19735870A1/de not_active Ceased
- 1997-08-18 FR FR9710437A patent/FR2752470B1/fr not_active Expired - Fee Related
- 1997-08-19 TW TW086111973A patent/TW358919B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR19980018067A (ko) | 1998-06-05 |
US6003129A (en) | 1999-12-14 |
FR2752470A1 (fr) | 1998-02-20 |
JPH10154080A (ja) | 1998-06-09 |
CN1176437B (zh) | 2010-06-02 |
CN1176437A (zh) | 1998-03-18 |
FR2752470B1 (fr) | 1999-06-11 |
DE19735870A1 (de) | 1998-03-19 |
KR100257520B1 (ko) | 2000-06-01 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |