Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Vanguard Interational Semiconductor CorpfiledCriticalVanguard Interational Semiconductor Corp
Priority to TW086101589ApriorityCriticalpatent/TW341724B/en
Application grantedgrantedCritical
Publication of TW341724BpublicationCriticalpatent/TW341724B/en
A process for producing an IC memory device, which comprises: forming a first dielectric layer on a semiconductor wafer; planarizing the first dielectric layer; using a lithography technique and an etching technique to etch the first dielectric layer to expose the semiconductor wafer forming holes; forming a poly layer; forming a second dielectric layer; forming dot silicon particles; etching the second dielectric layer and a portion of the dot silicon particles; oxidizing the silicon particles and polysilicon to form a silicon oxide layer; removing the silicon oxide layer; thermally oxidizing the polysilicon to form a layer of thin thermal silicon oxide; using an etching technique to carry out etching on the second dielectric layer and the polysilicon; removing the thin thermal silicon oxide.
TW086101589A1997-02-051997-02-05Process for producing an IC memory device
TW341724B
(en)
Local oxidation method employing polycide/silicon nitride clearance wall by controlling the width of pad oxide and silicon nitride to optimize the forming of isolation area