TW345721B - Method for improving polysilicon interconnect between split gates of flash memory - Google Patents

Method for improving polysilicon interconnect between split gates of flash memory

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Publication number
TW345721B
TW345721B TW086116770A TW86116770A TW345721B TW 345721 B TW345721 B TW 345721B TW 086116770 A TW086116770 A TW 086116770A TW 86116770 A TW86116770 A TW 86116770A TW 345721 B TW345721 B TW 345721B
Authority
TW
Taiwan
Prior art keywords
forming
flash memory
gate
layer
split gates
Prior art date
Application number
TW086116770A
Other languages
Chinese (zh)
Inventor
Gwo-Dong Sonq
Wen-Dinq Ju
Original Assignee
Mos Electronics Taiwan Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mos Electronics Taiwan Inc filed Critical Mos Electronics Taiwan Inc
Priority to TW086116770A priority Critical patent/TW345721B/en
Application granted granted Critical
Publication of TW345721B publication Critical patent/TW345721B/en

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Abstract

A method for improving the polysilicon interconnect between split gates of a flash memory, which comprises the following steps: (a) forming an oxide layer on the surface of a semiconductor substrate; (b) forming a first conductive layer on the oxide layer; (c) defining the first conductive layer thereby forming a first gate; (d) forming a first dielectric layer on the first gate; (e) forming a second dielectric layer on a side wall of the second gate; (f) forming a second conductive layer on the first dielectric layer, the second dielectric layer and the oxide layer; (g) defining the second conductive layer thereby forming a second gate; (h) performing a thermal oxidation on the surface of the semiconductor substrate thereby oxidizing the polysilicon or amorphous silicon tips remained on the surface of the semiconductor substrate into silicon dioxide.
TW086116770A 1997-11-10 1997-11-10 Method for improving polysilicon interconnect between split gates of flash memory TW345721B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW086116770A TW345721B (en) 1997-11-10 1997-11-10 Method for improving polysilicon interconnect between split gates of flash memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW086116770A TW345721B (en) 1997-11-10 1997-11-10 Method for improving polysilicon interconnect between split gates of flash memory

Publications (1)

Publication Number Publication Date
TW345721B true TW345721B (en) 1998-11-21

Family

ID=58263853

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086116770A TW345721B (en) 1997-11-10 1997-11-10 Method for improving polysilicon interconnect between split gates of flash memory

Country Status (1)

Country Link
TW (1) TW345721B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6268264B1 (en) * 1998-12-04 2001-07-31 Vanguard International Semiconductor Corp. Method of forming shallow trench isolation

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6268264B1 (en) * 1998-12-04 2001-07-31 Vanguard International Semiconductor Corp. Method of forming shallow trench isolation

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees