KR100227629B1 - A fabrication method of semiconductor device - Google Patents

A fabrication method of semiconductor device Download PDF

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KR100227629B1
KR100227629B1 KR1019960074976A KR19960074976A KR100227629B1 KR 100227629 B1 KR100227629 B1 KR 100227629B1 KR 1019960074976 A KR1019960074976 A KR 1019960074976A KR 19960074976 A KR19960074976 A KR 19960074976A KR 100227629 B1 KR100227629 B1 KR 100227629B1
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polysilicon layer
oxide film
film
semiconductor device
forming
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KR1019960074976A
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Korean (ko)
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KR19980055740A (en
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한성오
손재현
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

본 발명은 반도체 소자의 제조방법을 제공하는 것으로, 제1폴리실리콘층 마스크를 이용하여 제1폴리실콘층을 소정두께 식각한 후 산화공정을 실시하여 산화막을 형성하고, 제2폴리실리콘층 형성후 자기정합 식각방법으로 패터닝하여 액티브 영역의 손상 및 필드 산화막 상에 제1폴리실리콘층의 잔류물을 방지하며 또한 필드 산화막의 손실을 방지할 수 있는 효과가 있다.The present invention provides a method for manufacturing a semiconductor device, by etching a predetermined thickness of the first polysilicon layer using a first polysilicon layer mask, and then performing an oxidation process to form an oxide film, after forming the second polysilicon layer Patterning by a self-matching etching method prevents damage to the active region and residues of the first polysilicon layer on the field oxide layer, and also prevents the loss of the field oxide layer.

Description

반도체 소자의 제조방법Manufacturing method of semiconductor device

본 발명은 반도체 소자의 제조방법에 관한 것으로 특히, 플래쉬 메모리에서 비트라인 액티브 영역의 손상을 방지할 수 있는 반도체 소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of preventing damage to a bit line active region in a flash memory.

일반적으로 플래쉬 메모리 소자는 제1폴리실리콘층으로 이루어지는 플로팅 게이트와 제2폴리실리콘층으로 이루어지는 컨트롤 게이트와 제3폴리실리콘층으로 이루어지는 셀렉트 게이트로 구성되며, 상기 플로팅 게이트와 컨트롤 게이트 및 셀렉트 게이트는 자기정합 식각방법에 의해 형성된다. 상기 자기정합 식각방법이 실시될 때 제2(a)도 내지 제2(d)도에 도시된 바와같이 난드(NAND)형 플래쉬 메모리 셀에서는 비트라인 액티브 영역에 손상을 주게되고, 노어(AND)형 플래쉬 메모리 셀에서는 소스라인 영역에 손상을 주게된다. 제1도는 일반적인 플래쉬 메모리 셀의 레이아웃도로서, 제2(a)도 내지 제2(d)도를 참조하여 반도체 소자의 제조방법을 설명하면 다음과 같다. 제2(a)도는 필드 산화막(2)이 형성된 실리콘 기판(1)의 전체 상부면에 터널 산화막(3)과 제1폴리실리콘층(4)과 유전체 막을 이루는 하부 산화막(5A) 및 질화막(5B)을 순차적으로 형성한 후 제1폴리실리콘층 마스크(M1)를 이용하여 질화막(5B), 하부 산화막(5A), 제1폴리실리콘층(4) 및 터널 산화막(3)을 순차적으로 식각한 상태를 도시한다. 제2(b)도는 실리콘 기판(1)의 전체 상부면에 불순물 이온을 주입한 상태를 도시하며 제2(c)도는 실리콘 기판(1)의 전체 상부면에 산화공정을 실시한 후 실리콘 기판(1)의 전체 상부면에 제2폴리실리콘층(8)을 형성한 상태를 도시한다. 상기 산화공정에 의해 액티브 영역 및 제1폴리실리콘층(4)의 측벽에 산화막(7)이 형성되고, 지로하막(5B) 상에 상부 산화막(5C)이 형성되어 상부 산화막(5C), 질화막(5B) 및 하부 산화막(5A)으로 이루어지는 유전체막(5)이 완성된다. 제2(d)도는 제2폴리실리콘층 마스크(M2)를 이용한 자기정합 식각방법으로 제2폴리실리콘층(8), 유전체막(5) 및 제1폴리실리콘층(4)을 패터닝한 상태를 도시한다. 이때, 액티브 영역과 필드 산화막(2)의 경계면에는 이온주입이 제대로 이루어지지 않아서 화살표 A로 도시된 바와같은 손상영역이 발생되고, 필드 산화막(2)의 일측 상부에는 화살표 B로 도시된 바와같은 산화막 잔류물이 발생된다. 이는 제3폴리실리콘층 형성후 단차로 인하여 식각을 어렵게 한다.In general, a flash memory device includes a floating gate composed of a first polysilicon layer, a control gate composed of a second polysilicon layer, and a select gate composed of a third polysilicon layer, and the floating gate, the control gate, and the select gate are magnetic. It is formed by a matched etching method. When the self-aligned etching method is performed, as shown in FIGS. 2A to 2D, in the NAND type flash memory cell, the bit line active region is damaged and NAND is damaged. In the flash memory cell, the source line region is damaged. FIG. 1 is a layout diagram of a typical flash memory cell. A method of manufacturing a semiconductor device will now be described with reference to FIGS. 2A through 2D. FIG. 2 (a) shows the lower oxide film 5A and the nitride film 5B forming the dielectric film with the tunnel oxide film 3, the first polysilicon layer 4 on the entire upper surface of the silicon substrate 1 on which the field oxide film 2 is formed. ) And then sequentially etched the nitride film 5B, the lower oxide film 5A, the first polysilicon layer 4 and the tunnel oxide film 3 using the first polysilicon layer mask M1. Shows. FIG. 2 (b) shows a state in which impurity ions are implanted into the entire upper surface of the silicon substrate 1, and FIG. 2 (c) shows the silicon substrate 1 after performing an oxidation process on the entire upper surface of the silicon substrate 1. The state where the 2nd polysilicon layer 8 was formed in the whole upper surface of () is shown. By the oxidation process, an oxide film 7 is formed on the active region and sidewalls of the first polysilicon layer 4, and an upper oxide film 5C is formed on the subfloor film 5B to form the upper oxide film 5C and the nitride film ( The dielectric film 5 consisting of 5B and the lower oxide film 5A is completed. FIG. 2 (d) shows the state in which the second polysilicon layer 8, the dielectric film 5 and the first polysilicon layer 4 are patterned by a self-aligned etching method using the second polysilicon layer mask M2. Illustrated. At this time, ion implantation is not performed properly at the interface between the active region and the field oxide film 2, so that a damaged region as shown by arrow A is generated, and an oxide film as shown by arrow B is formed on one side of the field oxide film 2 above. Residue is generated. This makes it difficult to etch due to the step after forming the third polysilicon layer.

따라서 본 발명은 제1폴리실리콘층 마스크를 이용하여 제1폴리실리콘층을 소정두께 식각한 후 산화공정을 실시하여 산화막을 형성하고, 제2폴리실리콘층 형성후 자기정합 식각방법으로 패터닝하여 액티브 영역의 손상 및 필드 산화막 상에 산화막의 잔류물이 남지 않도록 할 수 있는 반도체 소자의 제조방법을 제공하는 것을 그 목적으로 한다.Therefore, in the present invention, the first polysilicon layer is etched by using a first polysilicon layer mask, and then, an oxide layer is formed by performing an oxidation process. It is an object of the present invention to provide a method for manufacturing a semiconductor device which can prevent the damage and the residue of the oxide film on the field oxide film.

상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 제조방법은 필드 산화막이 형성된 실리콘 기판의 전체 상부면에 터널 산화막과 제1폴리실리콘층과 유전체 막을 이루는 하부 산화막 및 질화막을 순차적으로 형성하는 단계와; 제1폴리실리콘층 마스크를 이용하여 질화막, 하부 산화막 및 제1폴리실리콘층을 순차적으로 패터닝 하는 단계와; 실리콘 기판을 전체 상부면에 산화공정을 실시하여 소정두께 식각된 제1폴리실리콘층을 산화막으로 변화시키고 질화막 상에 상부 산화막을 형성하여 유전체막을 완성하는 단계와; 실리콘 기판의 전체 상부면에 제2폴리실리콘층을 형성하는 단계와; 제2폴리실리콘층 마스크를 이용한 자기정합 식각방법으로 제2폴리실리콘층, 유전체막, 산화막 및 제1폴리실리콘층을 패터닝하는 단계로 이루어지며 상기 제1폴리실리콘층은 전체 두께의 1/2 내지 2/3 식각된다.A method of manufacturing a semiconductor device according to the present invention for achieving the above object comprises the steps of sequentially forming a lower oxide film and a nitride film forming a tunnel oxide film, a first polysilicon layer and a dielectric film on the entire upper surface of the silicon substrate on which the field oxide film is formed; ; Sequentially patterning the nitride film, the lower oxide film, and the first polysilicon layer using the first polysilicon layer mask; Performing an oxidation process on the entire upper surface of the silicon substrate to convert the first polysilicon layer etched into a predetermined thickness into an oxide film and forming an upper oxide film on the nitride film to complete the dielectric film; Forming a second polysilicon layer on the entire upper surface of the silicon substrate; Patterning the second polysilicon layer, the dielectric film, the oxide film, and the first polysilicon layer by a self-matching etching method using a second polysilicon layer mask, wherein the first polysilicon layer is 1/2 to the entire thickness; 2/3 is etched.

제1도는 일반적인 반도체 소자의 제조방법을 설명하기 위한 레이아웃도.1 is a layout for explaining a method of manufacturing a general semiconductor device.

제2(a)도 내지 제2(d)도는 종래 반도체 소자의 제조방법을 설명하기 위하여 제1도의 A-A을 따라 절취한 단면도.2 (a) to 2 (d) are cross-sectional views taken along the line A-A of FIG. 1 to explain a conventional method for manufacturing a semiconductor device.

제3(a)도 내지 제3(c)도는 본 발명에 따른 반도체 소자의 제조방법을 설명하기 위하여 제1도의 A-A을 따라 절취한 단면도.3 (a) to 3 (c) are cross-sectional views taken along the line A-A of FIG. 1 to illustrate a method of manufacturing a semiconductor device according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

M1 : 제1폴리실리콘층 마스크 M2 : 제2폴리실리콘층 마스크M1: first polysilicon layer mask M2: second polysilicon layer mask

1 및 11 : 실리콘 기판 2 및 12 : 필드 산화막1 and 11: silicon substrate 2 and 12: field oxide film

3 및 13 : 터널 산화막 4 및 14 : 제1폴리실리콘층3 and 13: tunnel oxide film 4 and 14: first polysilicon layer

5 및 15 : 유전체막 5A 및 15A : 하부 산화막5 and 15: dielectric film 5A and 15A: lower oxide film

5B 및 15B : 질화막 5C 및 15C : 상부 산화막5B and 15B: nitride film 5C and 15C: upper oxide film

7 및 17 : 산화막 8 및 18 : 제2폴리실리콘층7 and 17: oxide film 8 and 18: second polysilicon layer

이하, 본 발명에 따른 반도체 소자의 제조방법을 첨부도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

제3(a)도 내지 제3(d)도는 반도체 소자의 제조방법을 설명하기 위한 소자의 단면도로서, 제3(a)도는 필드 산화막(12)이 형성된 실리콘 기판(11)의 전체 상부면에 터널 산화막(13)과 제1폴리실리콘층(14)과 유전체 막을 이루는 하부 산화막(15A) 및 질화막(15B)을 순차적으로 형성한 후 제1폴리실리콘층 마스크(M1)를 이용하여 질화막(15B), 하부 산화막(15A) 및 제1폴리실리콘층(14)을 순차적으로 식각한 상태를 도시한다. 상기 제1폴리실리콘층(14)은 전체 두께의 1/2 내지 2/3 정도 식각된다.3A to 3D are cross-sectional views of a device for describing a method of manufacturing a semiconductor device. FIG. 3A is a view showing the entire upper surface of the silicon substrate 11 on which the field oxide film 12 is formed. The lower oxide film 15A and the nitride film 15B forming the tunnel oxide film 13, the first polysilicon layer 14, and the dielectric film are sequentially formed, and then the nitride film 15B is formed using the first polysilicon layer mask M1. , The lower oxide film 15A and the first polysilicon layer 14 are sequentially etched. The first polysilicon layer 14 is etched about 1/2 to 2/3 of the total thickness.

제3(b)도는 실리콘 기판(11)의 전체 상부면에 산화공정을 실시한 후 실리콘 기판(11)의 전체 상부면에 제2폴리실리콘층(18)을 형성한 상태를 도시한다. 상기 산화공정에 의해 소정두께 식각된 제1폴리실리콘층(14)은 산화막(17)으로 변화되고, 질화막(15B) 상에는 상부 산화막(15C)이 형성되어 상부 산화막(15C), 질화막(15B) 및 하부 산화막(15A)으로 이루어지는 유전체막(15)이 완성된다.FIG. 3 (b) shows a state in which the second polysilicon layer 18 is formed on the entire upper surface of the silicon substrate 11 after the oxidation process is performed on the entire upper surface of the silicon substrate 11. The first polysilicon layer 14 etched by a predetermined thickness by the oxidation process is converted into an oxide film 17, and an upper oxide film 15C is formed on the nitride film 15B to form the upper oxide film 15C, the nitride film 15B, and the like. The dielectric film 15 composed of the lower oxide film 15A is completed.

제3(c)도는 제2폴리실리콘층 마스크(M2)를 이용한 자기정합 식각방법으로 제2폴리실리콘층(18), 유전체막(15), 산화막(17) 및 제1폴리실리콘층(14)을 패터닝한 상태를 도시한다. 이때, 액티브 영역은 산화막(17)이 소정두께 남아있으며 화살표 C로 도시된 바와같이 손상되지 않고, 필드 산화막(12)의 일측 상부에는 화살표 D로 도시된 바와같은 산화막 잔류물이 남지 않는다.3C shows a second polysilicon layer 18, a dielectric film 15, an oxide film 17, and a first polysilicon layer 14 by a self-aligned etching method using a second polysilicon layer mask M2. The state which patterned is shown. At this time, in the active region, the oxide film 17 remains a predetermined thickness and is not damaged as shown by arrow C, and no oxide residue as shown by arrow D is left on one side of the field oxide film 12.

상술한 바와같이 본 발명에 의하면 제1폴리실리콘층 마스크를 이용하여 제1폴리실리콘층을 소정두께 식각한 후 산화공정을 실시하여 산화막을 형성하고, 제2폴리실리콘층 형성후 자기정합 식각방법으로 패터닝하여 액티브 영역의 손상 및 필드 산화막 상에 산화막 잔류물이 형성되는 것을 방지하며 또한 필드 산화막의 손실을 방지할 수 있는 효과가 있다.As described above, according to the present invention, the first polysilicon layer is etched using a first polysilicon layer mask, and then an oxide film is formed by performing an oxidation process, and after forming the second polysilicon layer, a self-aligned etching method is performed. Patterning prevents damage to the active region and formation of oxide residues on the field oxide film, and also prevents loss of the field oxide film.

Claims (2)

반도체 소자의 제조방법에 있어서, 필드 산화막이 형성된 실리콘 기판의 전체 상부면에 터널 산화막과 제1폴리실리콘층과 유전체막을 이루는 하부 산화막 및 질화막을 순차적으로 형성하는 단계와; 제1폴리실리콘층 마스크를 이용하여 질화막, 하부 산화막 및 제1폴리실리콘층을 순차적으로 패터닝 하는 단계와; 상기 실리콘 기판의 전체 상부면에 산화공정에 의해 소정두께 식각된 상기 제1폴리실리콘층을 산화막으로 변화시키고 상기 질화막 상에 상부 산화막을 형성하여 유전체막을 완성하는 단계와; 상기 실리콘 기판의 전체 상부면에 제2폴리실리콘층을 형성하는 단계와; 제2폴리실리콘층 마스크를 이용한 자기정합 식각방법으로 상기 제2폴리실리콘층, 유전체막, 산화막 및 제1폴리실리콘층을 패터닝하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 제조방법.A method of manufacturing a semiconductor device, comprising: sequentially forming a lower oxide film and a nitride film forming a tunnel oxide film, a first polysilicon layer, and a dielectric film on an entire upper surface of a silicon substrate on which a field oxide film is formed; Sequentially patterning the nitride film, the lower oxide film, and the first polysilicon layer using the first polysilicon layer mask; Converting the first polysilicon layer etched by a predetermined thickness into an oxide film on the entire upper surface of the silicon substrate and forming an upper oxide film on the nitride film to complete a dielectric film; Forming a second polysilicon layer on the entire upper surface of the silicon substrate; And patterning the second polysilicon layer, the dielectric film, the oxide film, and the first polysilicon layer by a self-matching etching method using a second polysilicon layer mask. 제1항에 있어서, 상기 제1폴리실리콘층은 전체 두께의 1/2 내지 2/3 식각되는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the first polysilicon layer is etched in 1/2 to 2/3 of an entire thickness thereof.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9167857B2 (en) 2008-08-18 2015-10-27 Electronics And Telecommunications Research Institute Waist belt for automatically measuring waist circumference

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