TW317617B - - Google Patents

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Publication number
TW317617B
TW317617B TW085112945A TW85112945A TW317617B TW 317617 B TW317617 B TW 317617B TW 085112945 A TW085112945 A TW 085112945A TW 85112945 A TW85112945 A TW 85112945A TW 317617 B TW317617 B TW 317617B
Authority
TW
Taiwan
Prior art keywords
signal
bus
data
timepiece
frequency
Prior art date
Application number
TW085112945A
Other languages
English (en)
Chinese (zh)
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Application granted granted Critical
Publication of TW317617B publication Critical patent/TW317617B/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Logic Circuits (AREA)
TW085112945A 1995-11-03 1996-10-22 TW317617B (enExample)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/552,657 US5781765A (en) 1995-11-03 1995-11-03 System for data synchronization between two devices using four time domains

Publications (1)

Publication Number Publication Date
TW317617B true TW317617B (enExample) 1997-10-11

Family

ID=24206241

Family Applications (1)

Application Number Title Priority Date Filing Date
TW085112945A TW317617B (enExample) 1995-11-03 1996-10-22

Country Status (4)

Country Link
US (1) US5781765A (enExample)
EP (1) EP0772133A3 (enExample)
JP (1) JP3616468B2 (enExample)
TW (1) TW317617B (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6493407B1 (en) * 1997-05-27 2002-12-10 Fusion Micromedia Corporation Synchronous latching bus arrangement for interfacing discrete and/or integrated modules in a digital system and associated method
US6266799B1 (en) * 1997-10-02 2001-07-24 Xaqti, Corporation Multi-phase data/clock recovery circuitry and methods for implementing same
US6000022A (en) 1997-10-10 1999-12-07 Micron Technology, Inc. Method and apparatus for coupling signals between two circuits operating in different clock domains
US6434684B1 (en) * 1998-09-03 2002-08-13 Micron Technology, Inc. Method and apparatus for coupling signals across different clock domains, and memory device and computer system using same
US6311285B1 (en) * 1999-04-27 2001-10-30 Intel Corporation Method and apparatus for source synchronous transfers at frequencies including an odd fraction of a core frequency
US7007187B1 (en) * 2000-06-30 2006-02-28 Intel Corporation Method and apparatus for an integrated circuit having flexible-ratio frequency domain cross-overs
US6949955B2 (en) * 2003-11-24 2005-09-27 Intel Corporation Synchronizing signals between clock domains
US10025343B2 (en) 2011-12-28 2018-07-17 Intel Corporation Data transfer between asynchronous clock domains
US10401427B2 (en) 2016-11-18 2019-09-03 Via Alliance Semiconductor Co., Ltd. Scannable data synchronizer
US9793894B1 (en) 2016-11-18 2017-10-17 Via Alliance Semiconductor Co., Ltd. Data synchronizer for registering a data signal into a clock domain
US9768776B1 (en) * 2016-11-18 2017-09-19 Via Alliance Semiconductor Co., Ltd. Data synchronizer for latching an asynchronous data signal relative to a clock signal

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4893271A (en) * 1983-11-07 1990-01-09 Motorola, Inc. Synthesized clock microcomputer with power saving
JPH07112147B2 (ja) * 1989-11-13 1995-11-29 三菱電機株式会社 半導体集積回路
US5448715A (en) * 1992-07-29 1995-09-05 Hewlett-Packard Company Dual clock domain interface between CPU and memory bus
US5471587A (en) * 1992-09-30 1995-11-28 Intel Corporation Fractional speed bus coupling
US5422914A (en) * 1993-09-07 1995-06-06 Motorola, Inc. System and method for synchronizing data communications between two devices operating at different clock frequencies
US5600824A (en) * 1994-02-04 1997-02-04 Hewlett-Packard Company Clock generating means for generating bus clock and chip clock synchronously having frequency ratio of N-1/N responsive to synchronization signal for inhibiting data transfer

Also Published As

Publication number Publication date
US5781765A (en) 1998-07-14
JPH09167134A (ja) 1997-06-24
EP0772133A2 (en) 1997-05-07
JP3616468B2 (ja) 2005-02-02
EP0772133A3 (en) 1997-10-22

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees