TW308716B - Chemical mechanical polishing process combined with etch back - Google Patents

Chemical mechanical polishing process combined with etch back Download PDF

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TW308716B
TW308716B TW85111794A TW85111794A TW308716B TW 308716 B TW308716 B TW 308716B TW 85111794 A TW85111794 A TW 85111794A TW 85111794 A TW85111794 A TW 85111794A TW 308716 B TW308716 B TW 308716B
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Taiwan
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patent application
dielectric layer
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chemical mechanical
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TW85111794A
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Chinese (zh)
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Yeong-Shenq Hwang
Long-Sheng You
Jih-Juang Hwang
Charng-Song Lin
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Taiwan Semiconductor Mfg
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Abstract

A chemical mechanical polishing process combined with etch backcomprises of the following steps: (1) forming one surface planar layer on one substrate, in which the substrate includes one metal pattern; (2) forming one first dielectric on the surface planar surface; (3) using chemical mechanical polishing(CMP) to remove partial first dielectric; (4) etching back partial first dielectric; (5) forming one second dielectric on the first dielectric.

Description

B7 五、發明説明() 5 -1發明領域: 本發明係爲半導體製程中的化學機械研磨法,特别是 關於結合回钱法的化學機械研磨製程方法。 5 - 2發明背景: 隨著半導體製程尺寸已縮小,矽晶片電路圖形的處理 變成是此項技術成敗的關鍵。對於元件電路圈形在微影製 程中只能容忍些微的非平坦度以防引起微距控制 (cntical dimens ion)的負面影響,因此,平坦化也變得 十分需要。在積體電路製程中,金屬内連線及淺溝渠的平 坦化是特别得重要。目前,有數個方法已發展出來如偏向 沉積{bias deposition)、光阻回蝕法(reb)、化學機械研 磨法(CM P)。化學機械研磨法(CMp丨是現在唯一能夠提供 半導鱧製程中達全面平坦化(G|〇b le planarization)的一 項新技術。 經濟部中央榡準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 在下列文章中將會仔細討論傳統使用化學機械研磨 法(C Μ P)來達成平坦化的製程及所碰到的問題。首先,形 成如第一圖所示之結構。圖中第一金屬層12形成於底材 1〇之上’然後沉積一層電衆增強氧化(Plasma-enchanced oxide)層14於第一金屬層12上,再來鍍一旋塗式玻璃 本紙張尺度適用中國國家標準(CNS ) A4規格(2!0χ 297公;| ) ^^716 A7 B7 經濟部中央標準局員工消費合作社印袋 五、發明説明() (Spin-〇n-glass)層16於電漿增強氧化層14上的溝褙 内;而後,再沉積一正矽酸乙酯層18於旋塗式玻璃 (Spin-on-glass)層16及電漿增強氡化層14上。通常’ 沉積一正矽酸乙酯層18的同時會產生隙洞15於正石夕酸 乙酯層18内。之後,使用化學機械斫磨法研磨正矽酸乙 酯層18以使正矽酸乙酯層18變薄而形成較薄之正矽酸 乙酯層18A如第二圈中所示之結構。從圖中不難發現隙 洞15的頂端已被磨掉少許,這會導致下一步形成第二金 屬層20時隙洞15的頂端爆掉而產生一氣泡25如第三圖 所示之。圈中一層電漿增強氧化(Plasma-enchanced oxide)層22沉積於第二金屬層20上,再來鍍一旋塗式玻 璃(Spin-on-g丨ass)層24於電漿增強氧化層22上的溝槽 内。氣泡25的產生是因爲隙洞内可能殘存未完全反應之 有機物。因爲第一次蝕刻爲低溫製程不會引起爆炸,但若 未被氧化層封住’則後續之光阻製程可能再滲入其它有機 物質且無法被洗掉(因爲太窄太深)故後續之金屬濺等 &lt;如 献)及金屬姓刻{反應氣體不同且溫度高)以及氧化層^積 等製程爲高溫環境尤其是鈦之化性很活潑且隙洞内·^又 被後續製程污杂(如果陳洞未封住,或封的不夠厚,而在 金屬過度蝕刻時被打開)則會引起爆炸而產生隙洞。氣泡 25的產生很容易造成後續製程的不便且影響產品品質。 爲了避免此現象的發生,通常解決之道是在使用化學 機械研磨法研磨正矽酸乙酯層18時過度地研磨 各紙張尺/lit财 ϋ ® ^WTcNsTA4ii~ (請先閱讀背面之注意事項再填离本頁) 訂 線 經濟部中央標準局員工消費合作社印製 Μ ____Β7 _ 五、發明説明() polish)正矽酸乙酯層18,使得正矽酸乙酯層18變更薄 形成較薄之正矽酸乙酯層18B如第四圈中所示之結構, 圈中虛線部分係爲原18A之部分。化學機械研磨法過度 地研磨的用意是故意將介窗層《Via layer即正矽酸乙酯層&gt; 多磨掉一些·以便可以回鍍《沉積)一層電漿增強氧化 (Plasma-enchanced oxide)層而將隙洞封住,因爲介窗 層之總厚度被要求在某一固定厚度。但爲了能增加回沉積 氡化層之厚度必須讓化學機械研磨多磨一些以使隙洞不 會在後績過程中因過度蝕刻而再度被打開。然後,沉積一 電漿增強氧化層26於正矽酸乙酯層18B之上。如此_ 來,已被磨掉許多之隙洞15洞口將被電漿增強氧化 《Plasma-enchanced oxide}層26封掉以防爆掉產生氣泡 25。但是,若使光軍對準曝光的步進機(Stepper)機台機 種{如ASM stepper PAS 5500系列,纣準方法爲:〇n- axis alignmant method )之對準標諸 34{Alignment mark) ,.位於同一晶片之大片平坦區域内30&lt;如第六圖所示)的 k話,過度地研磨正矽酸乙酯層18之同時會產生對準窗 32(Alignment window}&quot;中間凹下效應 &lt;Dishing effect)&quot;。第六圈所示爲ASMstepper所使用之晶片。其 中晶片30上有兩個對準窗32 ,而窗内各有一對準標兹 34,晶片30其它部分爲製作產品部分。一般情形,過度 地研磨正矽酸乙酯層18之厚度越多則對準窗之&quot;中間凹 下效應&quot;會越嚴重。第七圈至第十二圏所示爲對準窗之&quot;中 間凹下效應&quot;所衍生之問題。第七圖至第九圈所示爲大量 本紙張尺度適用中國國家梯準(CN’S M4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) . -In I I I n I 1 -- ill. - - I— -- i f — I- 1 I —1 ml I- I . I. Ir 308716 at B7 經濟部中央標準局員工消費合作社印製 五、發明説明() 過度地研磨正石夕酸乙酯層18之情形的剖面結構圖。大量 過度地研磨28正砍酸乙蜡層18使正矽酸乙酯層18變成 正矽酸乙醋層18C時,對準窗之&quot;中間w下效應&quot;嚴重而 導致磨損晶片上對準窗32内的對準標誌34如第七圈所 示。接著,'儿積電漿增強氧化&lt;Plasma-enchancedoxide&gt; 層26於正碎酸乙酯層18C之上,此時被磨損之對準標誌 34已被覆蓋如第八圖所示。但在後續之介窗蝕刻29(Via etch)後’被磨損之對準標誌34露出如第九圈。已磨損之 對準標誌34使得對準標誌喪失其功用。第十圖至第十二 圈所示爲只有少量過度地研磨正矽酸乙酯層之情形的剖 面結構圖。少量過度地研磨28A正矽酸乙酯層18使正石夕 酸乙酯層18變成正&gt;6夕酸乙酯層18D時,對準窗之&quot;中間 凹下效應&quot;輕微發生如第十圏所示。接著,沉積電漿增強 氧化(Plasma-enchanced oxide)層26於正矽酸乙酯層 18D之上,此時對準標誌34被覆蓋如第十一圖所示。但 在後續之介窗蝕刻29A(Via etch)後,對準標誌34仍被 覆蓋如第十二圖所示。這是因爲正矽酸乙酯層18D於對 準窗32内過厚。一旦此太厚之正矽酸乙酯未被介窗麵刻 (Via etch)時蝕刻乾淨’則再下層(金屬層}濺鍍時,則無 法依對準標誌形狀復蓋導致對準不良。 這種看似簡單的平坦化製程,化學機械研磨法 &lt;CMP)’卻產生上述之非常難以解決的問題,例如,内金 屬介電層過薄、製程中及後段製程中的爆炸問題'以及對 本紙張尺度適用中國國家標华(CNS ) A4規格(210X297公釐) (請先閱讀背面之注意事項再填寫本頁} •裝B7 5. Description of the invention () 5 -1 Field of the invention: The present invention is a chemical mechanical polishing method in the semiconductor manufacturing process, in particular, a chemical mechanical polishing manufacturing method combined with a cash back method. 5-2 Background of the invention: As the size of semiconductor processes has shrunk, the processing of silicon wafer circuit patterns has become the key to the success or failure of this technology. In the lithography process, the loop shape of the component circuit can only tolerate a slight degree of non-flatness to prevent the negative effects of macroscopic control (cntical dimens ion). Therefore, flattening has also become very necessary. The flattening of metal interconnects and shallow trenches is particularly important in integrated circuit manufacturing processes. At present, several methods have been developed such as bias deposition, photoresist etching (reb), chemical mechanical grinding (CM P). The chemical mechanical polishing method (CMp 丨 is now the only new technology that can provide G | 〇b le planarization) in the semiconducting snakehead process. Printed by the Consumer Cooperative of the Central Bureau of Economics of the Ministry of Economic Affairs (please read first (Notes on the back and then fill in this page) In the following article, we will discuss the process and problems encountered by traditional chemical mechanical polishing (CP) to achieve planarization. First, the formation is shown in the first figure. In the figure, the first metal layer 12 is formed on the substrate 10, and then a Plasma-enchanced oxide layer 14 is deposited on the first metal layer 12, and then a spin-on glass is plated This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (2! 0χ 297 g; |) ^^ 716 A7 B7 Printed Bag for Employees Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of Invention () (Spin-〇n-glass) Layer 16 in the trench on the plasma enhanced oxide layer 14; then, an orthosilicate layer 18 is deposited on the spin-on-glass layer 16 and the plasma enhanced radon layer 14 . Normally, the deposition of an orthosilicate layer 18 will occur at the same time The hole 15 is inside the orthosilicate layer 18. After that, the orthosilicate layer 18 is polished by chemical mechanical polishing to thin the orthosilicate layer 18 to form a thinner orthosilicate layer. The layer 18A has the structure shown in the second circle. It is not difficult to find from the figure that the top of the slot 15 has been worn away a little, which will cause the top of the slot 15 of the second metal layer 20 to be formed in the next step to burst and produce a The bubble 25 is shown in the third figure. A layer of plasma-enchanced oxide layer 22 in the circle is deposited on the second metal layer 20, and then a spin-on glass (Spin-on-g 丨 ass) is plated. ) The layer 24 is in the groove on the plasma-enhanced oxide layer 22. The bubbles 25 are generated because there may be incompletely reacted organic matter in the cavity. Because the first etching is a low temperature process, it will not cause an explosion, but if it is not The oxide layer is sealed ', then the subsequent photoresist process may infiltrate other organic substances and cannot be washed away (because it is too narrow and too deep) so the subsequent metal splash etc. & metal engraving {reaction gas and temperature High) and oxide layer ^ accumulation processes such as high temperature environment, especially the chemical nature of titanium is very active · ^ Cave and the gap has been a subsequent pollution heteroaryl process (Chen hole if not sealed, capped or not thick enough, and is turned on when over-etching of the metal) will cause an explosion gap hole is generated. The generation of bubbles 25 can easily cause inconvenience in subsequent processes and affect product quality. In order to avoid this phenomenon, the usual solution is to excessively grind each paper ruler when using the chemical mechanical grinding method to grind the ethyl orthosilicate layer 18 / litica ^ WTcNsTA4ii ~ (Please read the precautions on the back first (Fill away from this page) Printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs _____ Β7 _ V. Description of invention () polish) The ethyl orthosilicate layer 18 makes the ethyl orthosilicate layer 18 change thin to form a thinner The ethyl orthosilicate layer 18B has the structure shown in the fourth circle, and the dotted part in the circle is the part of the original 18A. The purpose of excessive polishing by chemical mechanical polishing is to deliberately rub off the via layer "Via layer" or "orthosilicate layer" so that it can be re-plated "deposition" a layer of plasma-enchanced oxide (Plasma-enchanced oxide) layer The gap is sealed because the total thickness of the via layer is required to be at a fixed thickness. However, in order to increase the thickness of the re-deposited radon layer, the chemical mechanical grinding must be polished more so that the gap will not be opened again due to excessive etching during the subsequent process. Then, a plasma enhanced oxide layer 26 is deposited on the layer of ethyl orthosilicate 18B. In this way, many gaps 15 that have been worn away will be sealed by plasma enhanced oxidation Plasma-enchanced oxide layer 26 to explode and generate bubbles 25. However, if you want to align Guangjun with the exposed Stepper machine model (such as ASM stepper PAS 5500 series, the standard method is: 〇n-axis alignmant method), the alignment marks are 34 {Alignment mark), . In the large flat area of the same wafer 30 <as shown in the sixth figure) k, excessive polishing of the ethyl orthosilicate layer 18 will produce an alignment window 32 (Alignment window) &quot; &lt; Dishing effect) &quot;. The sixth circle shows the chip used by ASMstepper. There are two alignment windows 32 on the wafer 30, and each of the windows has an alignment mark 34, and the other parts of the wafer 30 are the parts for manufacturing products. In general, the more the thickness of the ethyl orthosilicate layer 18 is excessively polished, the more severe the "winding effect" in the alignment window. The seventh circle to the twelfth circle show the problems arising from the "intermediate depression effect" of the alignment window. The seventh picture to the ninth circle show a large number of paper standards applicable to China's national standards (CN'S M4 specifications (210 X 297 mm) (please read the precautions on the back before filling this page). -In III n I 1 -ill.--I—-if — I- 1 I — 1 ml I- I. I. Ir 308716 at B7 Printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs V. Description of invention () Excessive grinding of orthostat Cross-sectional structure diagram of the situation of the ethyl silicate layer 18. When excessively grinding 28 the ethyl acetate wax layer 18 to change the ethyl orthosilicate layer 18 into the ethyl orthosilicate layer 18C, align the "center" of the window The "lower effect" is so severe that the alignment mark 34 in the alignment window 32 on the worn wafer is shown in the seventh circle. Next, the "Plasma-enchanced oxide" layer 26 is made of orthotropic acid On the ester layer 18C, the worn alignment mark 34 has been covered as shown in the eighth figure. However, after the subsequent window etching 29 (Via etch), the worn alignment mark 34 is exposed as the ninth Circle. The worn alignment mark 34 makes the alignment mark lose its function. The tenth to twelfth circles show only a small amount of The cross-sectional structure diagram of the case where the ethyl orthosilicate layer is ground. A small amount of excessive grinding of the 28A ethyl orthosilicate layer 18 makes the ortho-ethyl silicate layer 18 become normal &gt; 6 ethyl silicate layer 18D. The quasi-window's "middle depression effect" occurs slightly as shown in the tenth ring. Then, a plasma-enchanced oxide layer 26 is deposited on the ethyl orthosilicate layer 18D, at which time it is aligned The mark 34 is covered as shown in the eleventh picture. However, after the subsequent window etching 29A (Via etch), the alignment mark 34 is still covered as shown in the twelfth picture. This is because the ethyl orthosilicate layer 18D is too thick in the alignment window 32. Once this too thick ethyl orthosilicate is not etched when it is etched through the via window (Via etch), then the next layer (metal layer) is sputtered and cannot be aligned. Coverage of the mark shape leads to poor alignment. This seemingly simple planarization process, chemical mechanical polishing &lt; CMP) ', causes the above-mentioned problems that are very difficult to solve, for example, the inner metal dielectric layer is too thin, the process And the explosion problem in the post-stage process' and the application of China National Standard (CNS) A4 specification (2 10X297mm) (Please read the precautions on the back before filling out this page) • Install

t y I I 線- A7 B7 五、發明説明() 準標語喪失其功用導致發晶片—致小 不夠的問題。 5-3發明目的及概述: 本發明的主要目的爲結合回钱祛於化學機械研磨法 (Chemical mechanical polishingj的製程中以便解決先 前技術所1生的爆炸及平坦度問題、對準標誌的功能喪 失、成本過於昂贵的困擾。 本發明之方法包含下列主要步猓爲以化學機械研磨 法(Chemical mechanical polishing)除去部分内金屬介 電層《如正矽酸乙酯層 &gt; ;然後,再以回蝕法&lt;EtcJl back} 除去部分内金屬介電層。再來,形成一氧化物層於該内金 屬介電層上。 5-4圖式簡單説明: 經濟部中央標準局員工消費合作社印袋 第一圏至第六闺所示爲傳統之化學機械研磨法各階段之 剖面結構圈。 第七圏至第九圖所示爲大量過度地研磨内金屬介電層時 對準窗的剖面結構圖。 第十圖至第十二圖所示爲只有少量過度地研磨内金屬介 電層時對準窗的剖面結構圖 第十三圖至第十六圖所示爲本發明製程各階段之晶片剖 本紙張尺度適用中國國家標準(CNS ) A4規格(2〗0X297公釐) ^ 装------訂----線_ (請先閱讀背面之注意事項再填寫本頁)t y I I line-A7 B7 V. Description of the invention () The slogan loses its function and leads to the issue of chip-to-small issue. 5-3 Purpose and Summary of the Invention: The main purpose of the present invention is to combine money back in the process of chemical mechanical polishing (Chemical Mechanical Polishing) in order to solve the explosion and flatness problems caused by the prior art, and the loss of the function of the alignment mark 3. The cost is too expensive. The method of the present invention includes the following main steps: removing part of the inner metal dielectric layer "such as ethyl orthosilicate layer" by chemical mechanical polishing; Etching &lt; EtcJl back} Remove part of the inner metal dielectric layer. Next, form an oxide layer on the inner metal dielectric layer. 5-4 Brief description of the diagram: Printed bag of the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs The first to sixth figures show the cross-sectional structure circles of each stage of the traditional chemical mechanical polishing method. The seventh to ninth figures show the cross-sectional structure diagrams of the alignment window when the inner metal dielectric layer is excessively ground The tenth to twelfth figures show the cross-sectional structure of the alignment window when there is only a small amount of excessive grinding of the inner metal dielectric layer. The thirteenth to sixteenth figures show the process of the present invention. The chip profile of the segment is applicable to the Chinese National Standard (CNS) A4 specification (2〗 0X297mm) ^ Packing ------ Order ---- line _ (please read the precautions on the back before filling this page )

五、發明説明() 經濟部中央禕隼局員工消費合作社印製 面結構圈。 第十七圈至第十九圈所示爲在操作本發明之製程時對準 窗之剖面結構圈。 5 - 5發明詳細説明: 本發明主要利用回钱珐之技術取代傳統之化學機械 研磨法過度研磨之技術以改善前迷之爆炸及對準窗之&quot;中 間凹下效應〃之問題° 第十三圖至第十六圖所示爲本發明製程各暗段之晶 片剖面結構圖。第十三圖所示爲已形成一内金屬介電層 48之晶片剖面結構圈。圈中第一金屬層42形成於底材 40之上,然後沉積一層電漿增強氡化(Plasma-enchanced oxide}層44於第一金屬層42上,再來鍍一旋塗式玻璃 &lt;Spin-on-glass)層46於電漿增強氧化層44上的溝播 内;而後,再沉.積一内金屬介電層48於旋塗式玻璃 •&gt;e. (Spin-on-glass)層16及電漿増強氧化層14上。通常, 一内金屬介電層48爲正石夕酸乙酯層且厚度約爲22000-33000A。一般,沉積一内金曷介電層48的同時會產生 隙洞45於内金屬介電層48内。第十四圖所示爲已完成 本發明製程之第一階段之晶片剖面結構圖。本發明製程之 第一階段爲第一次除去部分内金屬介電層48,其中除去 部分内金屬介電層的厚度約爲15000-25000A。此步骤 本纸張尺度適用中國國家梂準(CNS ) A4規格(210X297^~y -----------絮------訂---ΊΙΊ J--線一I (請先M讀背面之注意事項再填艿本頁) A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明() 係使用化學機械研磨法(CMP)研磨厚度約爲22000-3 3000 A之内金屬介電層48以形成内金屬介電層48E。 通常内金屬介電層48E含有隙洞45。 第十五圈所示爲已完成本發明製程之第二階段之晶 片剖面結構圖。本發明製程之第二階段爲第二次除去部分 該内金屬介電層48E ,其中除去部分内金屬介電層48e 的厚度約爲1500-4000A。此步驟係使用回蝕法蝕刻厚度 約爲7000-14000A之内金屬介電層48E以形成内金屬介 電層48F。通常,回蝕法&lt;Etch bac|〇係爲反應性離子蝕 刻法(Reactive ion etch)。反應性離子蝕刻法係使用使用 含碳、氟之電漿蝕刻,其中含碳、氟之電漿包含 CF4,CHF3,Ar等。其操作條件如下:CF4,CHF3,Ar氣體流 量約爲 35-45sccm,35-45sccm,300-400sccm 溫度 控制於攝氏60-1 00度之間。最後,形成_氧化物層Μ 於内金屬介電層48F上如第十六圏所示。此氧化物層使 用電漿增強化學氣栢沉積法&lt;PECVD丨沉積而成。通常此氧 化物層爲電漿增強氧化物層(PE〇xide}且厚度約《1〇〇〇· :000埃。本發明之製程係針對化學機械研磨法使用的機 台機種(如ASM Stepper)之對準標誌位於同—晶片《如第 六圈所示)所設計,故在操作本發明之製程時可保持對準 窗内的對準標誌完整又不致喪失對準標誌之功能。第十七 圈至第十九圈所示爲在操作本發明之製程時對準窗之剖 本紙張尺度賴( cns ) μ規格 ^IT---;------- —.4.1 (請先閲讀背面之注意事項再填寫本頁) +叫! ινιΛ^„.·.·»ι 經濟部中央標準局員工消費合作杜印製 A7 B7 五、發明説明() 面結構圖。第十七圈所示爲當己完成使用化學機械研磨法 &lt;CMP)第一次地除去部分内金屬介電層時對準窗之剖面 結構圈。此時,於對準窗上亦覆蓋一層内金屬介電層 48E。然後’進行回蝕法50蝕刻該内金屬介電層48 E以 形成内金屬介電層48F如第十七圈中虛線所劃。回蝕法 50蝕刻後,對準窗32之對準標誌34會因對準窗32之&quot;中 間凹下效應w而露出内金屬介電層48F ,但是回蝕法5〇 不會彳H壞到對準標达34。之後’形成一氣化物層56於 該内金屬介電層48F上,此時氧化物層56亦將完整之對 準標达34覆蓋住如第十八圖所示。如此—來,當進行後 續之介層蝕刻步驟時’完整之對準標誌34又會露出,不 致於喪失對準標誌之功能囡而導致矽晶片一致性的偏 差。 本發明的主要特徵爲結合回蝕法於化學機械研磨法 (Chemical mechanical polishing)的製程中。縮短化學 機械研磨法的時間可減少其成本,因爲化學機械研磨法卷 一項成本非常昂贵的製程。再者,回蝕法會保持對準標誌 的完整性並且可清除隙洞内的殘留物及改善隙洞口的二 糙不平以便獲得較厚且平坦的氧化物層避免爆炸發生於 完成化學機械研磨法後的製程中。如此一來,本發明可藉 著回蝕法來補償原先化學機械研磨法製程中對矽晶片一 致性的偏差。 本纸張尺度適用中國國参標準(CNS ) A4規格(2!〇X 297公慶) 1 I I 訂 I | : Ί 線 — (請先閲讀背面之注意事項再填寫本頁) A7 B7 五、發明説明() 本發明雖以一較佳實例闞明如上,然其並非用以限定 本發明精神與發明實體’僅止於此一實施例爾’而熟悉此 領域技藝者,在不脱離本發明之精神與範圍内所作之修 改,均應包含在下述之申請專利範圍内° 批水 訂 ^ .. 線 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消费合作社印製 10 本紙張尺度適用中國國家標準(CTNS ) Λ4規格(210X 297公釐)Fifth, the invention description () The Ministry of Economic Affairs Central Falcon Bureau Employee Consumer Cooperative printed the surface structure circle. The seventeenth circle to the nineteenth circle show the cross-sectional structure circles of the alignment window when operating the process of the present invention. 5-5 Detailed description of the invention: The present invention mainly uses the technique of cash-back enamel to replace the traditional chemical mechanical polishing method of over-grinding technology to improve the explosion of the previous fan and the problem of "the middle concave effect" of the alignment window ° Tenth Figures 3 to 16 show the cross-sectional structure of wafers in the dark sections of the manufacturing process of the present invention. Figure 13 shows a wafer cross-section structure ring in which an inner metal dielectric layer 48 has been formed. The first metal layer 42 in the circle is formed on the substrate 40, and then a layer 44 of plasma enhanced radon (Plasma-enchanced oxide) is deposited on the first metal layer 42, and then a spin-on glass is applied &lt; Spin -on-glass) layer 46 in the trench on the plasma-enhanced oxide layer 44; then, re-sink. Deposit an inner metal dielectric layer 48 on the spin-on glass • &gt; e. (Spin-on-glass) On the layer 16 and the plasma oxide layer 14 is strong. Generally, an inner metal dielectric layer 48 is an orthoethyl silicate layer and has a thickness of about 22000-33000A. Generally, the deposition of an inner gold dielectric layer 48 will produce a cavity 45 in the inner metal dielectric layer 48 at the same time. Figure 14 is a cross-sectional view of a wafer that has completed the first stage of the process of the present invention. The first stage of the process of the present invention is the first removal of a portion of the metal dielectric layer 48, wherein the thickness of the removed portion of the metal dielectric layer is about 15000-25000A. In this step, the paper standard is applicable to China National Standards (CNS) A4 specification (210X297 ^ ~ y ----------- Cool ------ order --- ΊΙΊ J-- 线 一 I (Please read the precautions on the back before filling in this page) A7 B7 Printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of invention () The thickness of the polishing is about 22000-3 3000 using chemical mechanical polishing (CMP) The inner metal dielectric layer 48 of A is to form the inner metal dielectric layer 48E. Generally, the inner metal dielectric layer 48E contains the holes 45. The fifteenth circle shows the cross-sectional structure of the wafer that has completed the second stage of the manufacturing process of the present invention The second stage of the manufacturing process of the present invention is to remove part of the inner metal dielectric layer 48E for the second time, wherein the thickness of the removed part of the inner metal dielectric layer 48e is about 1500-4000A. This step is to use an etch back method to etch a thickness of about 7000-14000A of the inner metal dielectric layer 48E to form the inner metal dielectric layer 48F. Generally, the etch back method &lt; Etch bac | is a reactive ion etching method. The reactive ion etching method is used Etching with plasma containing carbon and fluorine, which contains CF4, CHF3, Ar, etc. The conditions are as follows: CF4, CHF3, Ar gas flow rate is about 35-45sccm, 35-45sccm, 300-400sccm The temperature is controlled between 60-100 degrees Celsius. Finally, an oxide layer M is formed on the inner metal dielectric layer 48F The above is shown on the sixteenth ring. This oxide layer is deposited using plasma enhanced chemical vapour deposition method <PECVD 丨. Usually this oxide layer is a plasma enhanced oxide layer (PE〇xide) and the thickness is about "100.000: Angstrom. The process of the present invention is designed for the alignment marks of the machine models (such as ASM Stepper) used in the chemical mechanical polishing method-the wafer" as shown in the sixth circle ", so When operating the process of the present invention, the alignment mark in the alignment window can be kept intact without losing the function of the alignment mark. Circles 17 to 19 show the alignment window during operation of the process of the invention. Cut paper size (cns) μ specifications ^ IT ---; -------. 4.1 (please read the precautions on the back and then fill out this page) + Call! ΙνιΛ ^ „.. ·» ι A7 B7 printed by the consumer cooperation of the Central Bureau of Standards of the Ministry of Economic Affairs. V. Description of the invention () Surface structure diagram. Shown is the cross-sectional structural ring of the alignment window when the chemical mechanical polishing method (CMP) is used to remove part of the internal metal dielectric layer for the first time. At this time, an internal metal dielectric layer is also covered on the alignment window 48E. Then, an etch-back method 50 is performed to etch the inner metal dielectric layer 48E to form an inner metal dielectric layer 48F as indicated by the broken line in the seventeenth circle. After etching back 50, the alignment mark 34 of the alignment window 32 will expose the inner metal dielectric layer 48F due to the &quot; recess effect w &quot; of the alignment window 32, but the etching back method 50 will not cause damage To align the mark up to 34. After that, a vapor layer 56 is formed on the inner metal dielectric layer 48F. At this time, the oxide layer 56 also covers the complete alignment mark 34 as shown in FIG. In this way, when the subsequent interlayer etching step is performed, the complete alignment mark 34 will be exposed again, so as not to lose the function of the alignment mark and cause the deviation of the consistency of the silicon wafer. The main feature of the present invention is to combine the etch-back method in the process of chemical mechanical polishing. Shortening the time of the chemical mechanical polishing method can reduce its cost, because the chemical mechanical polishing method is a very expensive process. Furthermore, the etch-back method will maintain the integrity of the alignment mark and can remove residues in the cavity and improve the roughness of the opening of the cavity in order to obtain a thick and flat oxide layer to prevent explosions from occurring after completing the chemical mechanical grinding method After the process. In this way, the present invention can compensate the deviation of the consistency of the silicon wafer in the original chemical mechanical polishing process by the etch-back method. This paper scale is applicable to the Chinese National Ginseng Standard (CNS) A4 specification (2! 〇X 297 gala) 1 II Order I |: Ί line — (Please read the precautions on the back before filling this page) A7 B7 V. Invention Explanation () Although the present invention is described above as a preferred example, it is not intended to limit the spirit of the present invention and the invention entity 'only ends with this embodiment.' Those who are familiar with the art in this field, without departing from the present invention The amendments made within the spirit and scope should be included in the scope of the following patent applications ° Approval of water ^ .. line (please read the precautions on the back before filling out this page) Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 10 The size of this paper is in accordance with Chinese National Standard (CTNS) Λ4 specification (210X 297mm)

Claims (1)

3〇pTT6一— &amp; 3: 13¾ .¾ - ij A8 B8 C8 D8 六、申請專利範圍 E-?.; h -r\ '[!:( 1. 一種結合回蝕法的化學機械研磨製程方法,包含下列 ^ m I#步裸: (請先閱讀背面之注意事項再填寫本頁) 貧W形成一表面平坦層於一底材上,其中該底材包含一金屬圈 if η· 年形; 容3 丨形成於一第一介電層於該表面平坦層之上; 使用化學機械研磨法(CMP)除去部分該第一介電層; 予P f哲回姓部分該第一介電層;以及 正fe 。之形成一第二介電層於該第一介電層上。 2.如申請專利範团第1項所述之方法,其中形成上述之 表面平坦層包含: 沉積一等角二氧化矽層於上述之底材之上; 沉積一旋塗式玻璃層於該等角二氧化矽層之上;以及 以等角二氧化矽層爲蝕刻終點蝕刻該旋塗式玻璃層。 3·如申請專利範圍第1項所述之方法,其中上述之第一 介電層包含正矽酸乙酯層。 4. 如申請專利範圍第1項所述之方法,其中上述之第一 介電層之厚度约爲22000-33000A。 經濟部中央標準局員工消費合作社印製 5. 如申請專利範園第1項所述之方法,其中使用化學機 械研磨法(CM P)除去上述之第一介電層之厚度約爲 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) c m及A r氣體流量約爲 Λ8 B8 C8 1)8 •申請專利範圍 1 5000-25000A ° 6. 如申請專利範国第1項所述之方法,其中回蝕上述之 第一介電層之厚度約爲1500-4000A。 7. 如申請專利範園第1項所述之方法,其中上述之回钱 法(Etch back)係爲反應性離子蝕刻法(Reactive i〇n etch) 〇 8. 如申請專利範国第7項所述之方法,其中上述之反應 性離子蝕刻法包含使用含碳、氟之電漿。 9. 如申請專利範团第8項所述之方法,其中上述之含 碳、氟之電漿包含CF4,CHF3,Ar等。 1〇.如申請專利範圍第9項所迷之方法,其中上述之 CF4,C2Fe氣體流量約爲35_45sc 300-400sccm 〇 11·如申請專利範圓第7項所述之方法,其中上述之反應 性離子飪刻法的操作溫度控制於槔氏6〇1〇〇度之間。 12.如申請專利範項所述之方法 介電層的厚度約爲1000_3000埃。 $ 一 — — — —— — I I H 訂 . . M— I 線 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標隼局員工消費合作社印製 wml*i III.I. -屮 * A8 B8 C8 D8 六、申請專利範圍 13.如申請專利範園第1項所述之方法’其中上述(第一 介霆層包含使用電漿增強化學氣相沉積法&lt;PECVD)沉 積。 第 之 述 上 中 其 〇 , 法-s 方 X 之EO d P *&quot;(. 所層 項物 1» 化 第氡 面强 範增 考 0 專雩 請含 申包 如層 •電 14介 經濟部中央標準局員工消費合作社印製 15· —種結合回蝕法的化學機械研磨製程方法’其中該 結合回蝕法的化學機械研磨製程方法使用的機台機種之 對準標誌34位於同一晶片上,包含下列步踩: 形成一表面平坦層於一底材上,其中該底材包含積逋電路 装置(丨ntegrated circuit devices}及金屬内連線’ 形成於一第一介電層於該表面平坦層之上; 第一次除去厚度約1 5000-25000A之第一介電層以化學 機械研磨法完成,其中該第一介電層内有隙洞,其中該第 一介雹層位於旋塗式玻璣層及電漿增強氧化層上; 第二次除去厚度約1 500-4000A之該第一介電層以回蝕 法完成;以及 形成一重漿增強氧化物層於該第一介電層上以電漿增強 化學氣相沉積法&lt; P E C V D)完成。 16.如申請專利範園第15項所述之方法,其中上述之回 蝕法(Etch back)係爲反應性離子蝕刻法(Reactive ion 本紙張尺度適用中國國家標準(CNS ) A4規格(210X 297公釐) --------—裝------訂一—: I,--- 線 (請先閱讀背面之注意事項再填寫本頁) 8 8 8 8 ABCD 六、申請專利範圍 etch) ° 17_如申請專利範園第16項所述之方法,其中上述之反 應性離子蝕刻法包含使用含碳、氟之電漿。 18. 如申請專利範圍第17項所述之方法,其中上述之含 碳、氟之電漿包含CF4, CHF3,Ar等。 19. 如申請專利範圍第18項所述之方法,其中上述之 CF4,C2F6氣體流量約爲35-45sccm及Ar氣體流量約爲 300-400sccm ° 20. 如申請專利範園第16項所述之方法,其中上述之反 應性離子蝕刻法的操作溫度控制於攝氏60-1 00度之間。 ^ -裝 訂 ^ ^ : 氣 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐)3〇pTT6 1-&amp; 3: 13¾ .¾-ij A8 B8 C8 D8 VI. Patent application scope E-?.; H -r \ '[!: (1. A chemical mechanical grinding process method combining etch back method , Including the following ^ m I # step naked: (please read the precautions on the back before filling in this page) to form a flat surface layer on a substrate, where the substrate contains a metal ring if η · year shape; Content 3 丨 is formed on a first dielectric layer on the flat surface layer; using chemical mechanical polishing (CMP) to remove part of the first dielectric layer; give the first part of the first dielectric layer; And positive fe. Forming a second dielectric layer on the first dielectric layer. 2. The method as described in item 1 of the patent application group, wherein forming the above-mentioned flat surface layer includes: depositing an isometric angle two The silicon oxide layer is on the above substrate; a spin-on glass layer is deposited on the isometric silicon dioxide layer; and the spin-on glass layer is etched with the isometric silicon dioxide layer as the etching end point. The method as described in item 1 of the patent application scope, wherein the first dielectric layer comprises ethyl orthosilicate 4. The method as described in item 1 of the patent application scope, where the thickness of the first dielectric layer is about 22000-33000A. Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. If applied for patent The method described in item 1, wherein the thickness of the first dielectric layer removed by the chemical mechanical polishing method (CM P) is about the size of this paper and the Chinese National Standard (CNS) A4 specification (210X297 mm) cm and Ar The gas flow rate is about Λ8 B8 C8 1) 8 • Patent application range 1 5000-25000A ° 6. The method as described in item 1 of the patent application model country, in which the thickness of the above-mentioned first dielectric layer is about 1500- 4000A. 7. The method as described in item 1 of the patent application park, where the above-mentioned Etch back method is the reactive ion etching method (Reactive i〇n etch) 〇8. If the application for patent application is item 7 In the method described above, the above-mentioned reactive ion etching method includes using a plasma containing carbon and fluorine. 9. The method as described in item 8 of the patent application group, wherein the above-mentioned plasma containing carbon and fluorine includes CF4, CHF3, Ar, etc. 1〇. The method as claimed in item 9 of the patent application range, wherein the above-mentioned CF4, C2Fe gas flow rate is about 35_45sc 300-400sccm 〇11 · The method as described in patent application item 7, wherein the above-mentioned reactivity The operating temperature of the ion cooking engraving method is controlled between 60,100 degrees Celsius. 12. The method as described in the patent application. The thickness of the dielectric layer is about 1000-3000 angstroms. $ 一 — — — —— — IIH order.. M—I line (please read the notes on the back before filling out this page) Printed by the Ministry of Economic Affairs, Central Standard Falcon Bureau Employee Consumer Cooperatives wml * i III.I.-屮 * A8 B8 C8 D8 6. Scope of patent application 13. The method as described in item 1 of the patent application park, where the above (first dielectric layer includes the use of plasma enhanced chemical vapor deposition & PECVD) deposition. The first statement is the best. The EO d P of the law-s side X * &quot; (. Layered items 1 »Huadi radon surface strong Fan Zengkao 0. Please include the application package such as layer • Electricity 14 medium economy Printed by the Ministry of Central Standards Bureau Employee Consumer Cooperatives 15-a chemical mechanical polishing process method combined with etch-back method 'where the alignment mark 34 of the machine model used in the chemical mechanical polishing process method combined with etch-back method is located on the same wafer , Including the following steps: forming a flat surface layer on a substrate, wherein the substrate includes integrated circuit devices (integrated circuit devices) and metal interconnections' formed on a first dielectric layer on the surface flat Above the layer; the first removal of the first dielectric layer with a thickness of about 15000-25000A is accomplished by chemical mechanical polishing, wherein the first dielectric layer has a cavity, and the first dielectric layer is located in the spin-on type On the glass layer and the plasma-reinforced oxide layer; the second removal of the first dielectric layer with a thickness of about 1500-4000A is completed by etch-back; and forming a heavy paste-reinforced oxide layer on the first dielectric layer Plasma-enhanced chemical vapor deposition &lt; P ECVD) completed 16. The method as described in item 15 of the patent application park, wherein the above-mentioned Etch back (Etch back) method is reactive ion etching method (Reactive ion This paper scale is applicable to China National Standard (CNS) A4 Specification (210X 297mm) --------— installed ------ order one :: I, --- line (please read the precautions on the back before filling this page) 8 8 8 8 ABCD 6. Patent application scope (etch) ° 17_ The method as described in item 16 of the patent application park, wherein the above-mentioned reactive ion etching method includes the use of plasma containing carbon and fluorine. 18. If the patent application scope is 17th The method according to item, wherein the above-mentioned plasma containing carbon and fluorine includes CF4, CHF3, Ar, etc. 19. The method according to item 18 of the patent application scope, wherein the gas flow rate of the above CF4, C2F6 is about 35- The flow rate of 45sccm and Ar gas is about 300-400sccm ° 20. The method as described in item 16 of the patent application park, wherein the operating temperature of the above-mentioned reactive ion etching method is controlled between 60-100 degrees Celsius. ^- Binding ^ ^: Gas (please read the precautions on the back before filling this page) Ministry of Economic Affairs Central Standards Co-op staff paper printed this scale applicable to Chinese National Standard (CNS) A4 size (210X297 mm)
TW85111794A 1996-09-26 1996-09-26 Chemical mechanical polishing process combined with etch back TW308716B (en)

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