CN1185080C - Method for monitoring measuring chemicomechanical grinding - Google Patents
Method for monitoring measuring chemicomechanical grinding Download PDFInfo
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- CN1185080C CN1185080C CNB021031541A CN02103154A CN1185080C CN 1185080 C CN1185080 C CN 1185080C CN B021031541 A CNB021031541 A CN B021031541A CN 02103154 A CN02103154 A CN 02103154A CN 1185080 C CN1185080 C CN 1185080C
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Abstract
The present invention relates to a method for monitoring and measuring the thickness change of a film structure of a semiconductor, which is characterized in that the thickness change of a film structure of an element area on a semiconductor is measured and monitored by a test area on the semiconductor in the grinding process of a chemical machine. The method has the steps: etching the film structure in the test area; ensuring that the pattern density of the etched film structure in the test area essentially approximates to the pattern density of the film structure in the element area so as to essentially emulate the thickness change of the film structure in the element area in a grinding technology of a chemical machine.
Description
Technical field
The present invention relates to a kind of semiconductor making method,, change in order to control measurement semiconductive thin film thickness of structure particularly about a kind of flatening process that is used in the semiconductor technology.
Background technology
Along with semiconductor fabrication has been developed to very lagre scale integrated circuit (VLSIC) (ultra largescale integration; ULSI) stage, can comprise on the chip of single IC for both reach millions of, or even tens million of elements.Therefore on the integrated circuit (IC) chip as transistor, capacitor, conductor are online, and area of isolation etc., all must its size of reduction, with the more highdensity chip of manufacturing.In order to produce the element of following sub-micron (sub-micrometer) size and smaller szie, must overcome as flatening process, etch process, and challenge such as photoetching process, form the element and the chip of high-reliability.
Existing technology at integrated circuit is the active region of definition integrated circuit, the active region of decision on semiconductor wafer, and each active region is the fabrication region of an integrated circuit, on semiconductor wafer, make many active regions simultaneously, and form many integrated circuits simultaneously.Generally speaking, the method for definition active region has multiple, comprises that forming field oxide centers on whole active region, perhaps form shallow trench isolation from around each active region, or make element on silicon oxide layer, and silicon oxide layer becomes best insulating barrier.
With the existing integrated circuits manufacturing technology, form the mode that field oxide defines the active region, can waste too many area, make the integrated level of integrated circuit to improve, and on earth silicon material, form the technology of element, full maturity not makes shallow ditch groove separation process become the most ripe isolation technology of a kind of current technology as yet.
Shallow trench isolation technology (shallow trench isolation; STI) be on semiconductor wafer, to form earlier shallow trench, the backfill silica material as insulating material, is removed the silica material at semiconductor wafer surface then to groove then, just, form a smooth shallow trench and insert at the silica material on surface, active region.Below with reference to the general shallow trench isolation technology of description of drawings.
See also Fig. 1, form a pad oxide 110 on the surface of semiconductor substrate 100, again with suitable chemical vapour deposition technique (CVD), as plasma enhanced CVD (PECVD) method, on pad oxide 110, form a silicon nitride layer 120, the layer that stops as grinding technics or etch process prevents among shallow ditch groove separation process, hurts the semiconductor substrate 100 of the fabrication region of integrated circuit.After pad oxide 110 and silicon nitride layer 120 forms, utilize traditional photo etched mask and etch process on this stack layer, to form patterned light blockage layer (not shown in the diagram come out), utilize the silicon nitride layer 120 of this patterning photoresist layer etching bottom again.Divest after the photoresist layer, down be etched into a plurality of shallow channel isolation areas as etching mask with the silicon nitride layer after the etching 120.Shallow channel isolation area can be described as non-activated areas (non-active area), shallow trench isolation between the zone then be active region (active area).Since the different designs of integrated circuit, the difference that active region and non-activated areas all can have width not wait.
Consult Fig. 2, this figure has shown the step that forms backing layer in the sidewall and the bottom of shallow trench region with for example thermal oxidation method.In addition, silicon oxide layer 130 then forms in the shallow trench of non-activated areas and on the silicon nitride layer 120 of active region with high density plasma CVD method (HDPCVD).HDPCVD Guttae Phacosylini silane (SiH
4), oxygen (O
2) and argon reacting gass such as (Ar) in reative cell, form the induction type coupled plasma source so that form the plasma of higher density.Simultaneously, the uniformity of film that the method deposited and inconsistent, its deposition velocity on the sidewall than the deposition velocity on the plane slowly many.If the width of groove is not for the moment, the film of HDP can insert in the narrower groove and its deposit thickness and groove width irrelevant.Because the configuration of surface of whole silicon oxide layer 130 is uneven, be recessed in the shallow trench zone, and the silicon oxide layer above silicon nitride layer 120 is protruding.This is because the deposition of silicon oxide layer 130 has the excellent step spreadability when forming, and can rise and fall along with the height of bottom pattern and do variation, forms rough configuration of surface (topography).
After silicon oxide layer deposited 130, must remove the silicon oxide layer 130 on silicon nitride layer 120, insert to form smooth groove, make things convenient for the integrated circuit technology of back.Usually the method for planarization silicon oxide layer 130 is to use chemical mechanical milling tech, or the use that mixes of chemical mechanical milling tech and etch process, reaches the purpose of whole flattening surface.The most normal now comprehensive flatening process that uses is chemical mechanical milling tech, can effectively polish silicon oxide layer 130 though carry out this kind technology, but the carrying out of the technology time is difficult to control, the very difficult control of the milling time of semiconductor wafer just.
Above-described shallow ditch groove separation process must accurately be controlled the milling time of chemical mechanical milling tech after silica material is inserted groove, form a smooth silica and insert among shallow trench.Yet according to the characteristic of chemical mechanical milling tech, grinding rate and bottom pattern have connection, that is to the large-area more mill layer for the treatment of, its grinding rate is more little.Otherwise, treat that the mill aspect is long-pending more little, its grinding rate is then big more.Influence in one's power, because semiconductor wafer surface grinding rate inequality, cause the semiconductor wafer surface overmastication (over-polishing) of part, and the semiconductor wafer surface of part grinds not enough (under-polishing), very difficult on the speed control.
On the other hand, general conventional art is controlled above-mentioned abrasive method and is utilized an optical measurement mechanism, to a certain test zone (the process control andmonitor key of the wafer in grinding; PCM key), carry out the synchro measure thickness of this region surface film thickness, whether the thickness that is ground rete with the decision semiconductor wafer surface has arrived at terminal point (endpoint), to stop grinding.Particularly, because this test zone (PCM key) is a certain specific region on the wafer, and the element region that contains circuit pattern on this test zone and the wafer has identical membrane structure and thickness, yet, this test zone do not present the shape that has an even surface owing to not having any circuit pattern, as showing the vertical view of this test zone among Fig. 3 A, Fig. 3 B then shows the schematic cross-section of this test zone.This has the test zone of flat surfaces control measurement, in order to the film surface varied in thickness that tool in the dummy wafer element area just rises and falls, the phenomenon of emulation distortion often takes place easily.More particularly, owing to the grinding rate that grinds this test zone with chemical mechanical milling method grinds this element area serves as slow, therefore when being ground to the grinding stop layer of this test zone, with respect to the overmastication usually of this element area, cause the damage of this element area and influence the due function of this element area.
From the above, general traditional chemical mechanical milling tech need be found out its indivedual suitable milling times with experimental technique at different wafer pattern designs.Thus, make that the interdependency of chemical mechanical milling tech and wafer product is very high, be difficult to reach mass-produced purpose.Therefore, how accurately the grinding rate and the time of emulation chemical mechanical milling tech, improve the flatening process of semiconductor wafer, and then effectively improve the semiconductor wafer yield and output is crucial.
Summary of the invention
The purpose of this invention is to provide a kind of control measurement semiconductive thin film thickness of structure changing method.
Another object of the present invention provides a kind of control measurement semiconductive thin film thickness of structure changing method, and it is used in the flatening process in the semiconductor technology, in order to the grinding endpoint of accurate control chemical mechanical milling tech.
In order to achieve the above object, the invention provides a kind of control measurement semiconductive thin film thickness of structure changing method, this semiconductor has an element region and a test section at least, wherein this element region has identical membrane structure with this test section, and this test section is in chemical mechanical milling tech, in order to the varied in thickness of this element region membrane structure of control measurement, this method comprises following steps at least: the pattern density that calculates this element region membrane structure; The membrane structure of this test section of etching makes the pattern density essence of this test section membrane structure after the etching be similar to the pattern density of this element region membrane structure, is beneficial to the varied in thickness of this element region membrane structure of essence emulation in the chemical mechanical milling tech; And grind this semiconductor, and measure the varied in thickness of this test section membrane structure.
Flattening method of the present invention is measured the varied in thickness of element region membrane structure on the monitoring semiconductor wafer by the test section on the semiconductor in chemical mechanical milling tech.This method comprises following steps at least: after at first calculating the pattern density of this element region membrane structure, with this pattern density is the membrane structure of reference value etching test section, make the pattern density essence of test section membrane structure after the etching be similar to the pattern density of element region membrane structure, be beneficial to the varied in thickness of this element region membrane structure of essence emulation in the chemical mechanical milling tech.In the technology of grinding this semiconductor wafer,,, make and grind the grinding stop layer that ends at this element region film at last with speed or the time that accurate control overall chip is ground by measuring the varied in thickness of this test section membrane structure.
Generally speaking, the integrated circuit (IC) design that on semiconductor wafer, includes many different pattern density, when therefore practical application is of the present invention, above-mentioned test zone pattern density can be according to actual state, select pattern density the most representative in numerous element areas as the reference standard value, as the foundation of handling the test zone density of film.In addition, the method that discloses according to the present invention can avoid traditional chemical mechanical milling tech needs at different wafer pattern designs, constantly seeks element area and the test zone correlation of milling time to each other repeatedly with experimental technique.Only need pattern properties with element area to be passed on the membrane structure of test zone just the accurately change in film thickness in monitoring element zone, reduce the interdependency of chemical mechanical milling tech and wafer product, to reach the purpose of wafer volume production.
Description of drawings
The present invention is described in detail below in conjunction with drawings and Examples:
Fig. 1 shows in the traditional handicraft, forms the schematic cross-section of shallow ditch groove structure on semiconductor substrate;
Fig. 2 shows in the traditional handicraft, forms backing layer and the schematic cross-section of silicon oxide layer on shallow ditch groove structure;
Fig. 3 A shows in the traditional handicraft, the vertical view of test zone;
Fig. 3 B shows in the traditional handicraft, the schematic cross-section of test zone;
Fig. 4 shows among the present invention, the schematic cross-section of element area after the equalization processing is waited to grind block on the semiconductor wafer;
Fig. 5 shows among the present invention, the process margin graph of a relation of element area film thickness and test zone film thickness on the semiconductor wafer;
Fig. 6 A shows among the present invention, had the vertical view of patterning test zone film surface pattern;
Fig. 6 B shows among the present invention, had the schematic cross-section of patterning test zone film surface pattern;
Fig. 7 shows among the present invention that the element area of semiconductor wafer is finished the schematic cross-section after the grinding.
Symbol description among the figure:
100 pad oxides of the semiconductor-based ends 110
120 silicon nitride layers, 130 silicon oxide layers
200 pad oxides of the semiconductor-based ends 210
220 silicon nitride layers, 230 silicon oxide layers
Embodiment
A kind of control measurement semiconductive thin film thickness of structure changing method is provided among the present invention, to eliminate the problem of wayward grinding stop layer in the traditional chemical mechanical milling tech, make the element area of semiconductor wafer can bring into play its proper function, and provide subsequent technique required high flat degree surface.
As described in background of invention, the present invention also utilizes an optical measurement mechanism, carry out the synchro measure thickness of this region surface film thickness at a certain specific test region on the semiconductor wafer in the grinding technics (PCM key), whether the thickness that is ground rete with the decision semiconductor wafer surface has arrived at terminal point (endpoint), and stops grinding technics.In an embodiment of the present invention, this test area size can be a certain specific zone that is about 360 μ m, wide about 120 μ m on the semiconductor wafer, be equivalent to the size in an element zone, but the area of this test zone is not restricted to this area size.
Do not limiting under spirit of the present invention and the range of application, follow-uply will utilize semiconductor shallow trench technology as discussed previously, introduce enforcement of the present invention with cooperation, and those skilled in the art, when utilizing identical method, apply to semi-conductive various flatening process.
As shown in Figure 4, the surface of semiconductor base material 200 comprises a pad oxide 210 at least and a silicon nitride layer 220 is formed on the pad oxide 210, and wherein silicon nitride layer 220 is as the etch stop layer in the chemical grinding technology of the present invention.In addition, after pad oxide 210 and silicon nitride layer 220 formation, utilize traditional photo etched mask and etch process on semiconductor substrate 200, to form a plurality of shallow channel isolation areas.Because the different designs of integrated circuit, shallow channel isolation area active region size to each other is not equal, and part is big, the less zones of different of part and form.Therefore follow-up when inserting dielectric insulation layer 230, for example in the shallow trench of non-activated areas and on the silicon nitride layer 220 of active region, form silicon oxide layer with high density plasma CVD method (HDPCVD), this dielectric insulation layer 230 rises and falls except that the height of following the bottom pattern and forms the rough configuration of surface (topography), and the dielectric insulation layer 230 of shallow channel isolation area top also presents the uneven situation of area size.
From the above, according to the characteristic of chemical mechanical milling tech, when grinding this dielectric insulation layer 230, large-arealy more treat that its grinding rate of mill layer is more little.Otherwise, treat that the mill aspect is long-pending more little, its grinding rate is then big more.The present invention is for improving the uneven shortcoming of semiconductor wafer surface grinding rate, before carrying out chemical mechanical milling tech, utilize a photoetching process to make that the volume size of each silicon oxide layer block 230 that each shallow ditch groove structure top is remaining is close in fact, the square afterwards chemical mechanical milling tech that carries out.
More particularly, utilize mask define pattern on silicon oxide layer 230, be etched in the silicon oxide layer 230 on the silicon nitride layer 220 then, expose the part surface of silicon nitride layer 220, and make each remaining silicon oxide layer block 230 big or small essence of each shallow ditch groove structure top after the etching close.Use the advantage of this road etch process, it is close to be that in advance the silicon oxide layer 230 on etches both silicon nitride layer 220 surfaces makes last waiting grind the block size, overcome the situation that causes subregion overmastication, subregion to grind deficiency because waiting to grind block size inequality and take place, improve the flatness of semiconductor wafer monolithic film membrane.
Yet, if only carry out above-mentioned processing of waiting to grind the block equalization for element area on the semiconductor wafer, membrane structure with respect to optics test zone on the semiconductor wafer (PCM key) still keeps smooth film surface and any similar processing is not arranged, when then carrying out follow-up chemical mechanical milling tech, because element area and the test zone otherness of Thinfilm pattern between the two will more strengthen, and cause the phenomenon of test zone emulation distortion even more serious.More particularly, if for element area wait grind the zone the not processing of averaging, only because the big or small uneven surface characteristic of uneven and area of element area Thinfilm pattern, membrane structure with optic test zone flat condition just is enough to produce the situation of grinding thickness emulation distortion, and element area on the infringement semiconductor wafer.If the uneven shortcoming of the grinding rate on surface to be ground in the element area on the solution semiconductor wafer, handle and wait to grind the block equalization, then on the contrary more enlarged elements zone and test zone between the two the otherness of Thinfilm pattern characteristic (both pattern densities than in addition differ to 10
2Grade doubly), the element region film thickness is with the situation of easier generation overmastication.
For instance, if silicon oxide layer 230 thickness to be ground in element area and the test zone are all 1925 dusts, in the traditional chemical mechanical milling tech, for prevent to take place the situation of above-mentioned overmastication in element area, the process margin of test zone thin-film grinding in grinding technics (process window) may be restricted to 1925 dusts～1000 dusts.That is when silicon oxide layer 230 thickness of test zone were ground to 1000 dusts, the silicon oxide layer 230 in the element area had been ground fully and has been removed, and stops on the surface of silicon nitride layer 220.Treat the process margin graph of a relation of wear down film in element area and the test zone, can utilize the straight line A explanation of Fig. 5, wherein the transverse axis of Fig. 5 is represented and is treated the wear down film thickness in the test zone, treat the wear down film thickness in the longitudinal axis representation element zone, when transverse axis (test zone) treat that the wear down film thickness is 1000 dusts the time, the wear down film thickness for the treatment of of the longitudinal axis (element area) is 0 dust.
The feature that the present invention had one of them, it is the semiconductor wafer testing zone that changes traditional tool flat surfaces, and on this test zone, carry out Thinfilm pattern to handle, make it have the pattern density (patterndensity) of or essence close (compatible) identical with element area.More particularly, when waiting on the element area to grind the processing of block equalization, be synchronized with on the membrane structure of this test zone and also carry out identical photoetching process, make that the element area Thinfilm pattern after the etching is identical with the Thinfilm pattern of test zone.After Fig. 6 A shows this test zone film of photoetching, after the vertical view of this Thinfilm pattern, Fig. 6 B then show this test zone film of photoetching, the pattern schematic cross-section of this test zone film surface.Thus, when carrying out chemical mechanical milling tech, the varied in thickness of control and measuring zone membrane structure is the varied in thickness of emulation element zone membrane structure accurately, makes grinding accurately end at the grinding stop layer, and for example silicon nitride layer 220.In other words, when silicon oxide layer 230 thickness of test zone were ground to 0 dust, the silicon oxide layer 230 in the element area had also been ground fully and has been removed, as shown in Figure 7.Therefore, the process margin of above-mentioned thin-film grinding can significantly enlarge, and will expand as 1925 dusts～0 dust with the precedent process margin, that is process margin will move to straight line B from the straight line A of Fig. 5, and enlarge the safe determination range of chemical mechanical milling tech.
If because the element area area is not identical with the test zone area, or the membrane structure of element area is when comparatively complicated, cause and to carry out the photoetching process identical in this test zone with the element area membrane structure, after the present invention then utilizes the pattern density of computing element zone protrusion, the pattern density that essence is close is passed on the film surface of test zone, with the purpose of the film thickness of reaching essence emulation element zone.More particularly, wait to grind region area A by what the element area projection was tried to achieve in calculating
1Account for the ratio D (D=A of integral member region area At
1/ At) after, as a reference data value, suitably handle the Patternized technique of test zone with this ratio D, make the pattern density essence of handling the back test zone be similar to the pattern density of element area.Show according to actual experiment, in 10 times of scopes that are not more than this ratio D, handle the Thinfilm pattern density of test zone, all can obtain the change in film thickness in accurate emulation element zone, improve the shortcoming of traditional simulation distortion.
The present invention with preferred embodiment explanation as above; only be used to use and help to understand enforcement of the present invention; non-in order to limit spirit of the present invention; and those skilled in the art are after comprehension spirit of the present invention; in not breaking away from spiritual scope of the present invention; change retouching and the variation that is equal to is replaced when doing some, its scope of patent protection when with claims and in conjunction with specification and accompanying drawing the person of being defined be as the criterion.
Claims (10)
1. control measurement semiconductive thin film thickness of structure changing method, this semiconductor has an element region and a test section at least, wherein this element region has identical membrane structure with this test section, and this test section is in chemical mechanical milling tech, varied in thickness in order to this element region membrane structure of control measurement is characterized in that: this method comprises following steps at least:
Calculate the pattern density of this element region membrane structure;
The membrane structure of this test section of etching makes the pattern density of this test section membrane structure after the etching be not more than 10 times of pattern density of this element region membrane structure, is beneficial to the varied in thickness of this element region membrane structure of emulation in the chemical mechanical milling tech; And
Grind this semiconductor, and measure the varied in thickness of this test section membrane structure.
2. method as claimed in claim 1 is characterized in that: also be contained in and form a plurality of shallow ditch groove structures in the semiconductor substrate of this element region, the semiconductor substrate of this test section then has a flat surfaces.
3. method as claimed in claim 1, it is characterized in that: above-mentioned membrane structure also comprises one second dielectric layer of one first dielectric layer and this first dielectric layer top, and this second dielectric layer between each these shallow ditch groove structure of this element region of etching forms a plurality of second dielectric layer blocks, makes each these second dielectric layer block equal and opposite in direction of each these shallow ditch groove structures top.
4. method as claimed in claim 3 is characterized in that: the pattern density of this element region membrane structure of aforementioned calculation is to calculate the second dielectric block area shared ratio in this element region entire area.
5. method as claimed in claim 3 is characterized in that: the first above-mentioned dielectric layer is a silicon nitride layer, as the cmp stop layer.
6. method as claimed in claim 3 is characterized in that: the second above-mentioned dielectric layer also comprises and utilizes the high density plasma CVD method to deposit an insulating oxide.
7. semiconductor planarization process with a plurality of shallow ditch groove structures, this semiconductor has an element region and a test section at least, wherein this element region has this a plurality of shallow ditch groove structures, and this test section has a flat surfaces, this element region has identical membrane structure with this test section, this membrane structure comprises one second dielectric layer of one first dielectric layer and this first dielectric layer top at least, in chemical mechanical milling tech, this test section is in order to the varied in thickness of this element region membrane structure of control measurement, and this method comprises following steps at least:
This second dielectric layer between each these shallow ditch groove structure of this element region of etching forms a plurality of second dielectric layer blocks, makes each these second dielectric layer block equal and opposite in direction of each these shallow ditch groove structure top;
Calculate the pattern density of this element region membrane structure;
The membrane structure of this test section of etching makes the pattern density of this test section membrane structure after the etching be not more than 10 times of pattern density of this element region membrane structure, is beneficial to the varied in thickness of this element region membrane structure of emulation in the chemical mechanical milling tech; And
Grind this semiconductor, and measure the varied in thickness of this test section membrane structure, make to grind to stop at this first dielectric layer surface.
8. method as claimed in claim 7 is characterized in that: the pattern density of this element region membrane structure of aforementioned calculation is to calculate the second dielectric block area shared ratio in this element region entire area.
9. method as claimed in claim 7 is characterized in that: the first above-mentioned dielectric layer is a silicon nitride layer, as the cmp stop layer.
10. method as claimed in claim 7 is characterized in that: the second above-mentioned dielectric layer also comprises and utilizes the high density plasma CVD method to deposit an insulating oxide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021031541A CN1185080C (en) | 2002-01-31 | 2002-01-31 | Method for monitoring measuring chemicomechanical grinding |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021031541A CN1185080C (en) | 2002-01-31 | 2002-01-31 | Method for monitoring measuring chemicomechanical grinding |
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| CN1435297A CN1435297A (en) | 2003-08-13 |
| CN1185080C true CN1185080C (en) | 2005-01-19 |
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| US8545289B2 (en) * | 2011-04-13 | 2013-10-01 | Nanya Technology Corporation | Distance monitoring device |
| CN102810492B (en) * | 2011-06-03 | 2015-08-05 | 中国科学院微电子研究所 | Process monitoring method after metal gate CMP |
| CN105304564B (en) * | 2014-07-10 | 2018-05-04 | 中芯国际集成电路制造(上海)有限公司 | The production method and its wordline CMP measuring structures of separate grid type memory |
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