CN105304564B - The production method and its wordline CMP measuring structures of separate grid type memory - Google Patents
The production method and its wordline CMP measuring structures of separate grid type memory Download PDFInfo
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- CN105304564B CN105304564B CN201410328596.8A CN201410328596A CN105304564B CN 105304564 B CN105304564 B CN 105304564B CN 201410328596 A CN201410328596 A CN 201410328596A CN 105304564 B CN105304564 B CN 105304564B
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Abstract
This application provides the production method and its wordline CMP measuring structures of a kind of separate grid type memory.The separate grid type memory includes the first substrate and sets multiple first grid structures on the first substrate and the first word line polysilicon layer, and the first spacing of first grid structure is L1, the second spacing of first grid structure is L2, and L1＜ L2, wordline CMP measuring structures include：Second substrate, the second substrate and the first substrate are integrated setting or relatively independent setting；Multiple second grid structures, are arranged equally spaced on the second substrate, spacing L3, and L1≤L3≤L2；Second word line polysilicon layer, is arranged on the second substrate between second grid structure.During CMP, the second grid structure of measuring structure is similar to the stress and polishing process of first grid structure, can accurately reflect first grid structure and the CMP effects of the first word line polysilicon layer, and can strengthen the measurement accuracy for measuring base station.
Description
Technical field
This application involves technical field of manufacturing semiconductors, in particular to a kind of making of separate grid type memory
Method and its wordline CMP measuring structures.
Background technology
The memory device of stored data is still maintained when nonvolatile semiconductor memory member is powered off.In general, non-volatile deposit
Memory device includes, such as (electric erasable is writable read-only to be deposited by EPROM (erasable writable read-only storage) device, EEPROM
Reservoir) device, SRAM and flash memory.
Separate grid type memory is a kind of non-volatile burst flash memory, its functional area includes memory cell areas and position
In the peripheral circuit region of memory cell areas periphery, wherein control gate is distributed in memory cell areas；And wordline (WL, Word
Line) polysilicon is distributed in memory cell areas and peripheral circuit region, and is used as the erasing grid of memory cell areas
The grid of (Erase Gate), selection gate (Select Gate) and peripheral circuit region.
At present, the prior art generally makes wordline using wordline production method as shown in Figure 1, is specially：First, there is provided
Chip as shown in Figure 2, the chip are divided into memory cell areas I ' and peripheral circuit region II ', and wherein memory cell areas I ' has control
It is silicon nitride layer 12 ' at the top of grid 11 ' processed and control gate；Fig. 3 institutes are formed in the upper wafer surface deposit polycrystalline silicon shown in Fig. 2
The first layer polysilicon membrane 13 ' shown；Formed in the upper surface cvd silicon oxide of the first layer polysilicon membrane 13 ' shown in Fig. 3
Silica separation layer 14 ', and photoresist layer is covered in the silica upper surface of deposition, which is exposed and then is incited somebody to action
The photoresist layer of the silicon oxide surface of memory cell areas I ' removes, and exposes silicon oxide layer separation layer 14 ', forms the photoetching shown in Fig. 4
Glue-line 15 '；Chip shown in Fig. 4 is etched, when the silica separation layer 14 ' not being covered by photoresist stops after completion of the reaction
Only etch, obtain having the chip of cross-section structure shown in Fig. 5；The photoresist layer 15 ' of Fig. 5 is removed, in the chip first shown in Fig. 5
The upper surface deposit polycrystalline silicon of layer polysilicon membrane 13 ' and oxide-isolation layer 14 ', forms the second layer polysilicon shown in Fig. 6
Film 16 '；Wordline chemically mechanical polishing (CMP) is carried out to the chip shown in Fig. 6, the control gate 11 ' of memory cell areas I ' is pushed up
The silicon nitride in portion exposes the upper surface of polysilicon membrane, then stops wordline chemically mechanical polishing, obtain with section knot shown in Fig. 7
The chip of structure.
In above-mentioned CMP process, chemically mechanical polishing effect is supervised using traditional optical measurement platform
Control, because traditional optical measures the requirement that base station reflects light, at present frequently with single III ' conductization of plane gaskets
Learn the measuring structure of mechanical polishing effect.Although plane gaskets III ' are ground at the same time in polishing process with memory cell areas,
Since it does not have the control gate and word line structure of memory cell areas I ', after the second polysilicon membrane is formed, its surface
Form and memory cell areas configuration of surface simultaneously differ, and cause its polishing effect with memory cell areas I ' also and differ, because
This measuring structure cannot accurately reflect the polishing effect of CMP, and then be difficult to realize the effective monitoring to CMP processes.
The content of the invention
The application aims to provide the production method and its wordline CMP measuring structures of a kind of separate grid type memory, with solution
The problem of wordline CMP measuring structures certainly of the prior art are difficult to effective monitoring CMP processes.
To achieve these goals, according to the one side of the application, there is provided a kind of word of separate grid type memory
Line CMP measuring structures, separate grid type memory include the multiple first grid knots of the first substrate and setting on the first substrate
Structure and the first word line polysilicon layer, the spacing between first grid structure is different, wherein the first spacing is L1, the second spacing is L2,
And L1＜ L2, wordline CMP measuring structures include：Second substrate, the second substrate and the first substrate are integrated setting or relatively independent set
Put；Multiple second grid structures, are arranged equally spaced on the second substrate, spacing L3, and L1≤L3≤L2；Second wordline is more
Crystal silicon layer, is arranged on the second substrate between second grid structure.
Further, above-mentioned L3=(L1+L2)/2。
Further, the CD of above-mentioned first grid structure is W1, the CD of second grid structure is W2, and W2≧W1。
Further, above-mentioned CMP measurement structures are first direction along the distribution arrangement of second grid structure, with first direction
The direction vertical with the upper surface of the second substrate is second direction, and the axis face of second grid structure in a second direction is symmetrically set
Put.
Further, above-mentioned second grid structure includes grid and the side wall on gate lateral wall, side wall axial plane in
It is symmetrical arranged.
Further, above-mentioned grid includes what is set successively away from the second substrate：First insulating layer, is arranged on the second substrate
On；First polysilicon layer, is arranged on the first insulating layer；Second insulating layer, is arranged on the first polysilicon layer；Second polysilicon
Layer, is set over the second dielectric；Hard mask layer, is arranged on the second polysilicon layer, the upper surface of hard mask layer and the second lining
The upper surface at bottom is parallel.
Further, above-mentioned side wall includes：First side wall, is arranged on the second insulating layer, the second polysilicon layer and hard mask
On the side wall of layer；Second side wall, is arranged on the first insulating layer, the first polysilicon layer and the exposed side wall of the first side wall.
Further, above-mentioned first insulating layer is oxide skin(coating)；Second insulating layer for silicon oxide layer, silicon nitride layer, ON layers
Or ONO layer.
Further, above-mentioned hard mask layer includes the first silicon nitride layer, the oxidation set successively away from the second polysilicon layer
Silicon layer.
Further, above-mentioned hard mask layer further includes the second silicon nitride layer for being arranged on silicon oxide layer upper surface.
Further, above-mentioned second word line polysilicon layer includes：Wordline grid oxygen oxide layer, be arranged on second grid structure it
Between the second substrate on；Polysilicon layer, is arranged in the wordline grid oxygen oxide layer between second grid structure.
Further, above-mentioned second substrate is wholely set with the first substrate.
According to the another aspect of the application, there is provided a kind of production method of separate grid type memory, the production method
Including：Step S1, makes the multiple first grid structures and the first word line polysilicon layer of separate grid type memory, first grid
Spacing between structure is different, wherein the first spacing is L1, the second spacing is L2, and L1＜ L2；Step S2, to separate grid type
Second word line polysilicon layer of the first word line polysilicon layer of memory and above-mentioned wordline CMP measuring structures carries out CMP；Step
S3, measures the wordline CMP measurement structures after CMP.
Further, above-mentioned production method further includes the manufacturing process of wordline CMP measuring structures, manufacturing process and separate gate
The first grid structure of pole formula memory and the manufacturing process of the first word line polysilicon layer are carried out at the same time.
Further, above-mentioned steps S3 is measured using scatterometry measurements.
Using the technical solution of the application, the height of second grid structure and the first grid structure of separable grid memory
Degree almost it is consistent, structure is similar, and be distributed spacing approach, therefore after wordline polysilicon deposition caused surface topography with
Memory cell areas is suitable, so that during CMP, the second grid structure of measuring structure and the stress of first grid structure and throwing
Photoreduction process is similar, can accurately reflect first grid structure and the CMP effects of the first word line polysilicon layer；And above-mentioned measurement knot
The second grid structure equidistantly distributed of structure, can strengthen the measurement accuracy for measuring base station, realize accurate measurement.
Brief description of the drawings
The accompanying drawings which form a part of this application are used for providing further understanding of the present application, and the application's shows
Meaning property embodiment and its explanation are used to explain the application, do not form the improper restriction to the application.In the accompanying drawings：
Fig. 1 shows the flow chart of the wordline production method of separate grid type memory in the prior art；
Fig. 2 to Fig. 7 shows the wafer cross structural representation for implementing to be obtained after each step of wordline production method shown in Fig. 1
Figure；
Fig. 2 shows the cross-sectional view for the chip that the prior art is provided；
Fig. 3 shows the section after the upper wafer surface deposit polycrystalline silicon shown in Fig. 2 forms first layer polysilicon membrane
Structure diagram；
Fig. 4 is shown sequentially forms oxide-isolation layer and light in the upper surface of the first layer polysilicon membrane shown in Fig. 3
Cross-sectional view after photoresist layer；
Fig. 5 shows the cross-sectional view after being etched to the chip shown in Fig. 4；
Fig. 6 shows the photoresist layer shown in removal Fig. 5 and in the first layer polysilicon membrane and oxide-isolated of chip
The upper surface deposit polycrystalline silicon of layer forms the cross-sectional view after second layer polysilicon membrane；
Fig. 7, which is shown, carries out the chip shown in Fig. 6 the cross-sectional view after wordline chemically mechanical polishing；
Fig. 8 shows the cross-sectional view for the wordline CMP measuring structures that a kind of preferred embodiment of the application provides；
Fig. 9 shows the flow of the production method for the separate grid type memory that a kind of preferred embodiment of the application provides
Figure；
Figure 10 to Figure 29 shows that the making that a kind of preferred embodiment of the application provides has wordline CMP amounts shown in Fig. 8
Cross-sectional view after each step of geodesic structure, wherein,
Figure 10 shows the cross-sectional view for the second substrate that above-mentioned preferred embodiment is provided, second substrate
It is divided into storage circuit area, peripheral circuit region and measuring structure area；
Figure 11 is shown sequentially forms the first insulating layer, the first polysilicon layer, second on the second substrate shown in Figure 10
Cross-sectional view after insulating layer, the second polysilicon layer and hard mask layer；
Figure 12 shows the cross-sectional view formed on the hard mask shown in Figure 11 after the first photoresist mask；
Figure 13 is shown to be performed etching to be formed successively to the hard mask layer in Figure 12, the second polysilicon layer and the second insulating layer
Cross-sectional view after first cascade structure；
Figure 14 shows the cross-sectional view after forming the first side wall in the first cascade structure both sides shown in Figure 13；
Figure 15 shows the cross-sectional view formed on the side of the first side wall shown in Figure 14 after sacrificing side wall；
Figure 16 shows that in the memory cell areas medium spacing shown in Figure 15 be L1Adjacent stepped construction between and part
Cross-sectional view after second photoresist mask is set in one stepped construction；
Figure 17 shows and performs etching to sacrificing side wall under the protection of the second photoresist mask shown in Figure 16 and remove the
Cross-sectional view after two photoresist masks；
Figure 18 is shown to be performed etching to obtain first grid knot to the first polysilicon layer shown in Figure 17 and the first insulating layer
Cross-sectional view after structure and second grid structure；
Figure 19 shows sacrifice side wall the first insulating layer remaining with possibility shown in removal Figure 18 and in the first side wall side
The cross-sectional view after the second side wall is formed on face；
Figure 20 shows the cross-sectional view set in the structure shown in Figure 19 after the 3rd photoresist mask, this
The opening of three photoresist masks is positioned at the second photoresist mask position shown in Figure 16；
Figure 21 is shown carries out ion implanting shape under the protection of the 3rd photoresist mask shown in Figure 20 to the first substrate
Into the cross-sectional view after ion implanted region；
Figure 22 shows to etch under the protection of the 3rd photoresist mask shown in Figure 21 and is not protected by the 3rd photoresist mask
Cross-sectional view after second side wall of shield；
Figure 23 shows the 3rd photoresist mask for removing Figure 22 and forms the cross-sectional view after side wall grid oxide layer；
After Figure 24 shows that thermal oxide is carried out to the first substrate shown in Figure 23, the second substrate surface forms combined oxidation silicon layer
Cross-sectional view；
Figure 25 shows above the ion implanted region of the memory cell areas shown in Figure 24 and ion implanted region both sides and leans on
Half of first grid superstructure of nearly ion implanted region sets the cross-sectional view after the 4th photoresist mask；
Figure 26 shows and the structure shown in Figure 25 is performed etching under the protection of the 4th photoresist mask shown in Figure 25
Cross-sectional view afterwards；
Figure 27 shows the 4th photoresist mask removed shown in Figure 26 and forms word in the first substrate, the second substrate surface
Cross-sectional view after wiregrating oxygen oxide layer；
After Figure 28 shows that deposit polycrystalline silicon forms polysilicon layer on the first substrate and the second substrate shown in Figure 27
Cross-sectional view；And
Figure 29 shows the cross-sectional view carried out to the polysilicon layer shown in Figure 28 after CMP.
Embodiment
It is noted that described further below is all illustrative, it is intended to provides further instruction to the application.It is unless another
Indicate, all technical and scientific terms used herein has usual with the application person of an ordinary skill in the technical field
The identical meanings of understanding.
It should be noted that term used herein above is merely to describe embodiment, and be not intended to restricted root
According to the illustrative embodiments of the application.As used herein, unless the context clearly indicates otherwise, otherwise singulative
Be also intended to include plural form, additionally, it should be understood that, when in the present specification using belong to "comprising" and/or " bag
Include " when, it indicates existing characteristics, step, operation, device, component and/or combinations thereof.
For the ease of description, spatially relative term can be used herein, as " ... on ", " ... top ",
" ... upper surface ", " above " etc., for describing such as a device shown in the figure or feature and other devices or spy
The spatial relation of sign.It should be appreciated that spatially relative term is intended to comprising the orientation except device described in figure
Outside different azimuth in use or operation.For example, if the device in attached drawing is squeezed, it is described as " in other devices
It will be positioned as " under other devices or construction after the device of part or construction top " or " on other devices or construction "
Side " or " under other devices or construction ".Thus, exemplary term " ... top " can include " ... top " and
" in ... lower section " two kinds of orientation.The device can also other different modes positioning (being rotated by 90 ° or in other orientation), and
And respective explanations are made to the opposite description in space used herein above.
As background technology is introduced, the wordline CMP processes of existing separate grid type memory, used wordline
CMP measuring structures are planar structure, it is difficult to reflect the real structure of separated grid, therefore cannot have to wordline CMP processes
Effect monitoring, in order to solve the problems, such as that as above, present applicant proposes the wordline CMP measuring structures and word of a kind of separate grid type memory
Line CMP method for measurement.
The wordline CMP measuring structures such as Fig. 8 for the separate grid type memory that one of which preferred embodiment is provided
Shown, which includes the first substrate 10 and the multiple first grid structures 11 being arranged on the first substrate 10
With the first word line polysilicon layer 12, the spacing between multiple first grid structures 11 is different, wherein the first spacing is L1, between second
Away from for L2, and L1＜ L2, wordline CMP measuring structures include the second substrate 20,21 and second wordline polycrystalline of multiple second grid structures
Silicon layer 22, the second substrate 20 and the first substrate 10 are integrated setting or relatively independent setting, and second grid structure 21 is equally spacedly
It is arranged on the second substrate 20, spacing L3, and L1≤L3≤L2；Second word line polysilicon layer 22 is arranged on second grid structure
On the second substrate 20 between 21.
Measuring structure with said structure, second grid structure 21 therein and the first grid of separable grid memory
The height of pole structure 11 is almost consistent, and structure is similar, and is distributed spacing and approaches, therefore produced by after wordline polysilicon deposition
Surface topography it is suitable with memory cell areas so that during CMP, the second grid structure 21 and first grid of measuring structure
The stress and polishing process of structure 11 are similar, can accurately reflect 11 and first word line polysilicon layer 12 of first grid structure
CMP effects；And 21 equidistantly distributed of second grid structure of above-mentioned measuring structure, the measurement that can strengthen measurement base station are accurate
Property, realize accurate measurement.Second substrate 20 of the wordline CMP measuring structures of the application and the first lining of separate grid type memory
Bottom 10, which can be wholely set, relatively independent to be set, and when being wholely set, make the first grid of separate grid type memory
Wordline CMP measuring structures, during relatively independent setting, wordline CMP are made while 11 and first word line polysilicon layer 12 of pole structure
Measurement independently makes relative to separate grid type memory, in order to preferably detect the effect of wordline CMP preferably both one
Body is set.
The application is in order to preferably reflect the CMP effects of the first grid structure 11 of different spacing, by the of measuring structure
The spacing of two gate structures 21 is arranged to L3=(L1+L2)/2。
The application is in order to make second grid structure 21 provide accurate, strong optical signal to measure base station, by above-mentioned second
The upper surface of gate structure 21 is arranged to the surface parallel with the upper surface of the second substrate 20.
In the application another preferred embodiment, distribution arrangement of the CMP measurement structures along second grid structure 21
For first direction, the direction vertical with the upper surface of first direction and the second substrate 20 is second direction, second grid structure 21
Axis face in a second direction is symmetrical arranged.Above-mentioned symmetrically arranged second grid structure 21 more meets the light reflection for measuring base station
It is required that therefore, the measuring structure obtained on the basis of it is more accurate.
The first grid structure 11 of separate grid type memory of the prior art includes stacked grid and positioned at stacked gate
The side wall 202 of pole both sides, the application is in order to more accurately reflect the wordline CMP of separate grid type memory as a result, it is preferred that
Two gate structures 21 include grid 211 and the side wall 212 on 211 side wall of grid, and in order to preferably meet to measure base station
Requirement, side wall 212 is symmetrical arranged along axis face.
Also for the first grid structure 11 for imitating separate grid type memory, as shown in Figure 8 (Figure 12 can be combined),
It is preferred that the gate structure 211 of the wordline CMP measuring structures of the application includes the first insulation set successively away from the second substrate 20
The 111, first polysilicon layer 112 of layer, the second insulating layer 113, the second polysilicon layer 114 and hard mask layer 115, the first insulating layer
111 are arranged on the second substrate 20；First polysilicon layer 112 is arranged on the first insulating layer 111；Second insulating layer 113 is set
On the first polysilicon layer 112；Second polysilicon layer 114 is arranged on the second insulating layer 113；Hard mask layer 115 is arranged on
On two polysilicon layers 114, and the upper surface of hard mask layer 115 is parallel with the upper surface of the second substrate 20.Wherein, the first insulating layer
111 be silicon oxide layer；Second insulating layer 113 is silicon oxide layer, silicon nitride layer, ON layers or ONO layer, those skilled in the art should
It is clear that the ON layers of double-decker formed for silicon oxide layer and silicon nitride layer, ONO layer is silica, silicon nitride and silica shape
Into sandwich structure.
It is preferred that above-mentioned side wall 212 includes the first side wall 121 and the second side wall 123, with reference to figure 8 (with reference to referring to Figure 11 and
12), the first side wall 121 is arranged on the side wall of the second insulating layer 113, the second polysilicon layer 114 and hard mask layer 115；Second
Side wall 123 is arranged on the exposed side wall of the first insulating layer 111, the first polysilicon layer 112 and the first side wall 121.
The hard mask layer 115 of the application can be that single layer structure can also be double-deck or sandwich construction, preferably above-mentioned mask
Layer includes the first silicon nitride layer, the silicon oxide layer set successively away from the second polysilicon layer 114.Further preferred above-mentioned hard mask
Layer 115 further includes the second silicon nitride layer for being arranged on silicon oxide layer upper surface.
The second word line polysilicon layer 22 of the application is also similar to 12 structure of the first word line polysilicon layer of the prior art,
Wordline grid oxygen oxide layer 221 and polysilicon layer 222 are preferably included, wordline grid oxygen oxide layer 221 is arranged on second grid structure 21
Between the second substrate 20 on；Polysilicon layer 222 is arranged in the wordline grid oxygen oxide layer 221 between second grid structure 21.
The application another preferred embodiment provides a kind of production method of separate grid type memory, the making
Method includes：Step S1, makes 11 and first word line polysilicon layer 12 of multiple first grid structures of separate grid type memory,
Spacing between first grid structure 11 is different, wherein the first spacing is L1, the second spacing is L2, and L1＜ L2；Step S2 is right
Second wordline polysilicon of the first word line polysilicon layer 12 of separate grid type memory and the wordline CMP measuring structures of the application
Layer 22 carries out CMP；Step S3, measures the wordline CMP measurement structures after CMP.
Due to the second grid structure 21 and the first grid structure of separable grid memory of the measuring structure of the application
11 structure is similar, and height is almost consistent, and is distributed spacing and approaches, therefore the caused surface after wordline polysilicon deposition
Pattern is suitable with memory cell areas, so that during CMP, second grid structure 21 and the first grid structure 11 of measuring structure
Stress and polishing process it is similar, the CMP effects of 11 and first word line polysilicon layer 12 of first grid structure can be accurately reflected；
And 21 equidistantly distributed of second grid structure of above-mentioned measuring structure, can strengthen the measurement accuracy for measuring base station, realize
Accurate measurement；And above-mentioned measurement process is measured using the scatterometry base station for being currently used for measuring critical size.
In order to more accurately simulate the knot of the 11 and first wordline polycrystal layer of first grid structure of separate grid type memory
Structure, preferably above-mentioned production method further include the manufacturing process of wordline CMP measuring structures, manufacturing process and separate grid type memory
The manufacturing process of 11 and first word line polysilicon layer 12 of first grid structure be carried out at the same time.The preferred above-mentioned steps S3 of the application is adopted
Measured with scatterometry measurements (Scatterometry).
Now, the illustrative embodiments according to the application are more fully described with reference to the accompanying drawings.However, these are exemplary
Embodiment can be implemented by many different forms, and should not be construed to be limited solely to embodiment party set forth herein
Formula.It should be appreciated that thesing embodiments are provided so that disclosure herein is thoroughly and complete, and these are shown
The design of example property embodiment is fully conveyed to those of ordinary skill in the art, in the accompanying drawings, for the sake of clarity, expands layer
With the thickness in region, and make identical device is presented with like reference characters, thus description of them will be omitted.
Wherein, by taking the first substrate 10 and the second substrate 20 are wholely set as an example, that is, it is carried out at the same time separate grid type memory
The manufacturing process of 11 and first word line polysilicon layer 12 of first grid structure and the manufacturing process of wordline CMP measuring structures be
Example, idiographic flow are as shown in Figure 9.
First, there is provided semiconductor base as shown in Figure 10, the semiconductor base include storage circuit area I, peripheral circuit
Area and measuring structure area II (wherein peripheral circuit region is not shown), wherein, second substrate of semiconductor in corresponding storage circuit area is
First substrate 10 of the application separate grid type memory, second substrate of semiconductor in corresponding measuring structure area measure for the application
Second substrate 20 of structure.
Then, the first insulating layer more than 111, first is sequentially formed on the first substrate 10 and the second substrate 20 shown in Figure 10
Crystal silicon layer 112, the second insulating layer 113, the second polysilicon layer 114 and hard mask layer 115, formation have cross-section structure shown in Figure 11
Device.Wherein, the first insulating layer 111 is silicon oxide layer；Second insulating layer 113 for silicon oxide layer, silicon nitride layer, ON layers or
ONO layer, it should be clear to those skilled in the art that the ON layers of double-decker formed for silicon dioxide layer and silicon nitride layer, ONO
The sandwich structure that layer is silica, silicon nitride and silica are formed.Hard mask layer 115 is included successively away from the second polysilicon layer
114 the first silicon nitride layers set, silicon oxide layer.Further preferred above-mentioned hard mask layer 115, which further includes, is arranged on silicon oxide layer
Second silicon nitride layer of upper surface.
Then, photoresist is set on the hard mask 115 shown in Figure 11, processing is then patterned to photoresist, is obtained
To the first photoresist mask 31 being spaced apart shown in Figure 12, wherein, graphical rear remaining first light of memory cell areas
The spacing of photoresist mask 31 differs, wherein, the first spacing is L1, the second spacing is L2, and L1＜ L2；And it is located at measuring structure area
The spacing of photoresist mask be all mutually L3.Relation between above-mentioned spacing is L1≤L3≤L2, preferably L3=(L1+L2)/2。
Under the protection of the first photoresist mask 31 shown in Figure 12, to the hard mask layer 115 in Figure 12, the second polysilicon
114 and second insulating layer 113 of layer performs etching successively, obtains the spaced first cascade structure 41 shown in Figure 13, preferably
The etching process is implemented using dry etching.With reference to figure 8 and Figure 13, it can be seen that the first cascade structure 41 of memory cell areas
Between 8 medium spacing of gap corresponding diagram be L1Or L2Position, and the spacing phase between the first cascade structure 41 in measuring structure area
Together, L and in the interstitial site corresponding diagram 83Position.
After removing above-mentioned first photoresist mask 31, formed in 41 both sides of first cascade structure shown in Figure 13 shown in Figure 14
The first side wall 121, which can be the composite bed of silicon oxide layer, silicon nitride layer or silica and silicon nitride,
For example the silicon oxide layer and silicon nitride layer outwards set gradually by inner side forms first side wall 121, wherein the first side wall 121
Generation type is implemented using deposition commonly used in the art, etching mode, and details are not described herein.
Formed after the first side wall 121, the sacrifice side wall shown in Figure 15 is formed in 121 side of the first side wall shown in Figure 14
122, consisting of silicon oxide layer, generation type is method commonly used in the art, such as the side using above-mentioned the first side wall of formation 121
Method.
Then, in the first polysilicon layer 112 shown in Figure 15, first cascade structure 41, the first side wall 121 and sacrifice side wall
Photoresist is set on 122, processing is then patterned to photoresist, obtains the second photoresist mask 32 shown in Figure 16.By
As can be seen that the second photoresist mask 32 is only stored in memory cell areas in Figure 16, and it is L to be covered in spacing1Adjacent stacking
Between structure and on segments first layer stack structure 41, remainder is all exposed.
Under the protection of the second photoresist mask 32 shown in Figure 16, etch Figure 16 shown in not by the second photoresist mask
The sacrifice side wall 122 of 32 protections, it is preferred to use wet etching implements the etching process, and above-mentioned second photoetching is removed after the completion of etching
Glue mask 32, obtains the unilateral sacrifice side wall 122 on the inside of 41 small spacing of first cascade structure as shown in figure 17, can be seen by Figure 17
Go out one side sacrifice side wall 122 and exist only in memory cell areas.
The first polysilicon layer 112 shown in Figure 17 and the first insulating layer 111 are performed etching successively, obtained shown in Figure 18
First grid structure 11 and second grid structure 21, it is preferred to use dry etching is implemented.As seen from Figure 18, positioned at the first side
First polysilicon layer 112 of the second grid structure 21 of the lower section of wall 121 is symmetrical arranged.
The unilateral side wall 122 of sacrificing removed using wet etching shown in Figure 18 (at this time may remaining first insulating layer 111
Also be removed) and 121 side of the first side wall in figure 18 on form the second side wall 123 shown in Figure 19.Wherein the second side wall
123 forming methods are also method commonly used in the art, such as forming method of first side wall 121 with sacrificing side wall 122.
In the first substrate 10 shown in Figure 19 and the second substrate 20, the first side wall 121, the second side wall 123, first grid knot
Photoresist is set in structure 11 and second grid structure 21, processing is then patterned to the photoresist, is formed shown in Figure 20
3rd photoresist mask 33, wherein, the opening that the 3rd photoresist is formed is positioned at the position corresponding to the second photoresist mask 32.
Under the protection of the 3rd photoresist mask 33 shown in Figure 20, ion note is carried out to the first substrate 10 shown in Figure 20
Enter, form the ion implanted region 13 shown in Figure 21.As seen from Figure 21, except memory cell areas small pitch portions second
Substrate 10 is exposed, and other parts are all in the protection of the 3rd photoresist mask 33, and therefore, ion implanting is to except small spacing
The first substrate 10 and the second substrate 20 outside part do not have an impact.
Continue under the protection of the 3rd photoresist mask 33, etch the second side wall do not protected by the 3rd photoresist mask 33
123, until exposing first of the first grid structure 11 (the first grid structure 11 indicated referring to Figure 18) shown in Figure 21
112 side wall of polysilicon, forms the structure shown in Figure 22.Equally because the protection of the 3rd photoresist mask 33, the measurement in Figure 22
123 structure of the second side wall of 21 both sides of second grid structure of structure is not removed, still keeps being symmetrical arranged.
The 3rd photoresist mask 33 shown in Figure 22 is removed, and in the top of first grid structure shown in Figure 22 11, the first side
Wall 121, the second side wall 123, first grid structure 11 112 side wall of the first polysilicon on, the first substrate 10,20 and of the second substrate
Deposition oxide in second grid structure 21, forms the side wall grid oxide layer 124 shown in Figure 23.
The composite oxygen SiClx shown in Figure 24 is formed to the first substrate 10 shown in Figure 23, the progress thermal oxide of 20 surface of the second substrate
Layer 223, this combined oxidation silicon layer 223 also can as the gate oxygen structure of peripheral circuit region part component part or all
(not shown).Because small the first substrate of pitch portions 20 in memory cell areas I is ion implanted region 13, therefore in thermal oxide
Oxidation rate is very fast relative to the first not ion implanted substrate 20 in journey, so as to form circular projection (dome).And measure
II second substrate 10 of structural area is not injected into ion, therefore oxide layer is more smooth, therefore will not be to the measurement of measurement base station
It can have an impact.
Photoresist is set on 223 upper surface of silicon oxide layer of Figure 24,124 surface of side wall grid oxide layer, then to the photoresist
It is patterned processing, is formed above the ion implanted region 13 positioned at memory cell areas shown in Figure 25 and ion implanted region 13
Both sides and the 4th photoresist mask 34 above half of first grid structure 11 of ion implanted region 13.
Under the protection of the 4th photoresist mask 34, the structure shown in Figure 25 is performed etching, forms cuing open shown in Figure 26
Face structure, wherein, due to the presence of the 4th photoresist mask 34 so that the 11 top section quilt of first grid structure after etching
Etching, and the top of the second grid structure 21 in measuring structure area is etched at the same time, therefore the top of second grid structure 21 is still
It is relatively flat, it is symmetrical set, in addition, the side wall gate oxide in Figure 25 is also partially etched, and the first substrate 10 and second
Exposed silicon oxide layer is all etched on substrate 20.
After completing above-mentioned etching, remove the 4th photoresist mask 34 shown in Figure 26 and carry out thermal oxide, exposed
First substrate 10,20 surface of the second substrate form the wordline grid oxygen oxide layer 221 shown in Figure 27.
Then, on the first substrate 10 and the second substrate 20 shown in Figure 27 deposit polycrystalline silicon formed it is more shown in Figure 28
Crystal silicon layer 222, polysilicon layer 222 therein are formed (two before and after the dotted line expression in Figure 27 preferably through polysilicon deposition twice
The line of demarcation of the polysilicon of secondary deposition), the 221 composition amount of polysilicon layer 222 and wordline grid oxygen oxide layer positioned at memory cell areas
The precursor of first word line polysilicon layer 12 of geodesic structure, polysilicon layer 222 and wordline grid oxygen oxide layer positioned at measuring structure area
221 form the precursor of the second word line polysilicon layer 22 of measuring structure.Due to memory cell areas first grid structure 11 and measure
The second grid structure 21 of structural area have passed through same production process, therefore its physical property is identical, is then passed through again
The first word line polysilicon layer 12 and the physical property of the second word line polysilicon layer 22 that identical deposition process is formed are also identical
's.
Then, CMP is carried out to the polysilicon layer 22 shown in Figure 28, forms the device with cross-section structure shown in Figure 29.Position
The first wordline that polysilicon layer 222 in memory cell areas forms measuring structure after CMP with wordline grid oxygen oxide layer 221 is more
Crystal silicon layer 12, the polysilicon layer 222 positioned at measuring structure area form measuring structure after CMP with wordline grid oxygen oxide layer 221
The second word line polysilicon layer 22.Due to 20 surfacing of the second substrate in measuring structure area, second grid structure 11 it is symmetrical and
Periodic arrangement, therefore, when being measured using it as measurement sample, can reflect CMP planarization degree and effect exactly；And
Since measuring structure area and memory cell areas experienced identical manufacture craft, the measurement knot provided using measuring structure
Fruit can accurately, truly reflect the polishing and effect of the wordline CMP of memory cell areas.
Described above is only the method that the application preferably makes wordline CMP measuring structures, those skilled in the art
The combination of this area conventional technology can be used individually to carry out the making of wordline CMP measuring structures, details are not described herein.
It can be seen from the above description that the application the above embodiments realize following technique effect：
1), there is the measuring structure of said structure, second grid structure therein and the first of separable grid memory
The structure of gate structure is similar, and height is almost consistent, and is distributed spacing and approaches, therefore produced by after wordline polysilicon deposition
Surface topography it is suitable with memory cell areas so that during CMP, second grid structure and the first grid knot of measuring structure
The stress and polishing process of structure are similar, can accurately reflect first grid structure and the CMP effects of the first word line polysilicon layer；
2), the second grid structure of above-mentioned measuring structure is equidistantly symmetrical, can strengthen the measurement standard for measuring base station
True property, realizes accurate measurement.
The foregoing is merely the preferred embodiment of the application, the application is not limited to, for the skill of this area
For art personnel, the application can have various modifications and variations.It is all within spirit herein and principle, made any repair
Change, equivalent substitution, improvement etc., should be included within the protection domain of the application.
Claims (15)
1. a kind of wordline CMP measuring structures of separate grid type memory, the separate grid type memory includes the first substrate
With multiple first grid structures and the first word line polysilicon layer being arranged on first substrate, multiple first grid knots
Spacing between structure is different, wherein the first spacing is L1, the second spacing is L2, and L1＜ L2, it is characterised in that the wordline CMP
Measuring structure includes：
Second substrate, second substrate are integrated setting or relatively independent setting with first substrate；
Multiple second grid structures, are arranged equally spaced on second substrate, and the spacing is L3, and L1≤L3≤L2；
Second word line polysilicon layer, is arranged on second substrate between the second grid structure.
2. wordline CMP measuring structures according to claim 1, it is characterised in that the L3=(L1+L2)/2。
3. wordline CMP measuring structures according to claim 1, it is characterised in that the CD of the first grid structure is W1,
The CD of the second grid structure is W2, and W2≧W1。
4. wordline CMP measuring structures according to claim 1, it is characterised in that the CMP measurement structures are along described second
The distribution arrangement of gate structure is first direction, and the direction vertical with the upper surface of the first direction and second substrate is
Second direction, the axis face of the second grid structure in a second direction are symmetrical arranged.
5. wordline CMP measuring structures according to claim 4, it is characterised in that the second grid structure includes grid
With the side wall on the gate lateral wall, the side wall is symmetrical arranged along the axis face.
6. wordline CMP measuring structures according to claim 5, it is characterised in that the grid is included successively away from described
What the second substrate was set：
First insulating layer, is arranged on second substrate；
First polysilicon layer, is arranged on first insulating layer；
Second insulating layer, is arranged on first polysilicon layer；
Second polysilicon layer, is arranged on second insulating layer；
Hard mask layer, is arranged on second polysilicon layer, and the upper surface of the hard mask layer is upper with second substrate
Surface is parallel.
7. wordline CMP measuring structures according to claim 6, it is characterised in that the side wall includes：
First side wall, is arranged on the side wall of second insulating layer, second polysilicon layer and the hard mask layer；
Second side wall, is arranged on first insulating layer, the first polysilicon layer and the exposed side wall of the first side wall.
8. wordline CMP measuring structures according to claim 6, it is characterised in that first insulating layer is oxide skin(coating)；
Second insulating layer is silicon oxide layer, silicon nitride layer, ON layers or ONO layer.
9. wordline CMP measuring structures according to claim 6, it is characterised in that the hard mask layer includes remote successively
The first silicon nitride layer, the silicon oxide layer of the second polysilicon layer setting.
10. wordline CMP measuring structures according to claim 9, it is characterised in that the hard mask layer, which further includes, to be arranged on
Second silicon nitride layer of the silicon oxide layer upper surface.
11. wordline CMP measuring structures according to claim 1, it is characterised in that the second word line polysilicon layer bag
Include：
Wordline grid oxygen oxide layer, is arranged on second substrate between second grid structure；
Polysilicon layer, is arranged in the wordline grid oxygen oxide layer between the second grid structure.
12. wordline CMP measuring structures according to any one of claim 1 to 11, it is characterised in that second substrate
It is wholely set with first substrate.
13. a kind of production method of separate grid type memory, it is characterised in that the production method includes：
Step S1, makes the multiple first grid structures and the first word line polysilicon layer of the separate grid type memory, described
Spacing between multiple first grid structures is different, wherein the first spacing is L1, the second spacing is L2, and L1＜ L2；
Any one of step S2, the first word line polysilicon layer and claim 1 to 11 to separate grid type memory institutes
Second word line polysilicon layer of the wordline CMP measuring structures stated carries out CMP；
Step S3, measures the wordline CMP measurement structures after CMP.
14. production method according to claim 13, it is characterised in that the production method further includes the wordline CMP
The manufacturing process of measuring structure, the manufacturing process and the first grid structure and the first wordline of the separate grid type memory
The manufacturing process of polysilicon layer is carried out at the same time.
15. production method according to claim 13, it is characterised in that the step S3 uses the scatterometry measurements amount of progress
Survey.
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| CN1435297A (en) * | 2002-01-31 | 2003-08-13 | 旺宏电子股份有限公司 | Method for monitoring measuring chemicomechanical grinding |
| CN102522354A (en) * | 2012-01-12 | 2012-06-27 | 中国科学院微电子研究所 | Method and device for extracting square resistances of interconnection lines |
| CN102810492A (en) * | 2011-06-03 | 2012-12-05 | 中国科学院微电子研究所 | Processing procedure monitoring method after CMP for metal gate |
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| US20070082490A1 (en) * | 2005-10-06 | 2007-04-12 | Chun-Ting Hu | Apparatus of chemical mechanical polishing and chemical mechanical polishing process |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1435297A (en) * | 2002-01-31 | 2003-08-13 | 旺宏电子股份有限公司 | Method for monitoring measuring chemicomechanical grinding |
| CN102810492A (en) * | 2011-06-03 | 2012-12-05 | 中国科学院微电子研究所 | Processing procedure monitoring method after CMP for metal gate |
| CN102522354A (en) * | 2012-01-12 | 2012-06-27 | 中国科学院微电子研究所 | Method and device for extracting square resistances of interconnection lines |
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