CN105304564A - Preparation method of separate gate type memory and word line CMP measurement structure thereof - Google Patents
Preparation method of separate gate type memory and word line CMP measurement structure thereof Download PDFInfo
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Abstract
The invention provides a preparation method of a separate gate type memory and a word line CMP measurement structure thereof. The separate gate type memory comprises a first substrate and a plurality of first gate structures and first word line polysilicon layers which are arranged on the first substrate, wherein a first distance of the first gate structures is L1, a second distance of the first gate structures is L2, L1 is smaller than L2, the word line CMP measurement structure comprises: a second substrate, the second substrate and the first substrate, which are integrally arranged or relatively independently arranged; a plurality of second gate structures which are equidistantly arranged on the second substrate, wherein the distance of the second gate structures is L3, and L3 is not smaller than L1 and is not larger than L2; a second word line polysilicon layer arranged on the second substrate between the second gate structures. In a CMP process, the stress and polishing processes of the second gate structures and the first gate structures of the measurement structure are similar, the CMP effect of the first gate structures and the first word line polysilicon layers can be accurately reflected, and the measurement accuracy of a measurement base station can be reinforced.
Description
Technical field
The application relates to technical field of manufacturing semiconductors, in particular to a kind of manufacture method and wordline CMP measuring structure thereof of separate grid type memory.
Background technology
Still the memory device of stored data is kept when nonvolatile semiconductor memory member is power-off.Usually, nonvolatile semiconductor memory member comprises, such as EPROM (erasable write read-only memory) device, EEPROM (electric erasable can write read-only memory) device, SRAM and flash memory.
Separate grid type memory is a kind of non-volatile burst flash memory, and its functional area comprises memory cell areas and is positioned at the peripheral circuit region of memory cell areas periphery, and wherein control gate is distributed in memory cell areas; And wordline (WL, WordLine) polysilicon all has distribution in memory cell areas and peripheral circuit region, and be used as memory cell areas erasing grid (EraseGate), select grid (SelectGate) and the grid of peripheral circuit region.
At present, prior art generally adopts wordline manufacture method as shown in Figure 1 to make wordline, be specially: first, wafer is as shown in Figure 2 provided, this wafer is divided into memory cell areas I ' and peripheral circuit region II ', and wherein memory cell areas I ' has control gate 11 ' and control gate top is silicon nitride layer 12 '; Upper wafer surface deposit spathic silicon shown in Fig. 2 forms the ground floor polysilicon membrane 13 ' shown in Fig. 3; The upper surface cvd silicon oxide of the ground floor polysilicon membrane 13 ' shown in Fig. 3 forms silica separator 14 ', and cover photoresist layer at the silica upper surface of deposition, this photoresist layer is exposed and then the photoresist layer of memory cell areas I ' silicon oxide surface is removed, expose silicon oxide layer separator 14 ', form the photoresist layer 15 ' shown in Fig. 4; Wafer shown in Fig. 4 is etched, when silica separator 14 ' not covered by photoresist stops etching after completion of the reaction, obtains having the wafer of cross-section structure shown in Fig. 5; Remove the photoresist layer 15 ' of Fig. 5, the wafer ground floor polysilicon membrane 13 ' shown in Fig. 5 and the upper surface deposit spathic silicon of oxide-isolation layer 14 ', form the second layer polysilicon membrane 16 ' shown in Fig. 6; Wordline chemico-mechanical polishing (CMP) is carried out to the wafer shown in Fig. 6, the silicon nitride at the control gate 11 ' top of memory cell areas I ' exposes the upper surface of polysilicon membrane, then stop wordline chemico-mechanical polishing, obtain having the wafer of cross-section structure shown in Fig. 7.
In above-mentioned CMP (Chemical Mechanical Polishing) process, traditional optical measurement platform is adopted to monitor chemico-mechanical polishing effect, because traditional optical measures base station to the requirement of light reflection, adopt single plane gaskets III ' as the measuring structure of chemico-mechanical polishing effect so normal at present.Although plane gaskets III ' is polished with memory cell areas in polishing process simultaneously, but because it does not have control gate and the word line structure of memory cell areas I ', therefore after the second polysilicon membrane is formed, its configuration of surface is not identical with memory cell areas configuration of surface, cause it also not identical with the polishing effect of memory cell areas I ', therefore this measuring structure accurately can not reflect the polishing effect of CMP, and then is difficult to realize the effective monitoring to CMP process.
Summary of the invention
The application aims to provide a kind of manufacture method and wordline CMP measuring structure thereof of separate grid type memory, to solve the problem that wordline CMP measuring structure of the prior art is difficult to effective monitoring CMP process.
To achieve these goals, according to an aspect of the application, provide a kind of wordline CMP measuring structure of separate grid type memory, separate grid type memory comprises the first substrate and the multiple first grid structure arranged on the first substrate and the first wordline polysilicon layer, spacing between first grid structure is different, and wherein the first spacing is L
1, the second spacing is L
2, and L
1< L
2, wordline CMP measuring structure comprises: the second substrate, and the second substrate and the first substrate are integrated and arrange or relatively independent setting; Multiple second grid structure, is arranged on the second substrate equally spacedly, and spacing is L
3, and L
1≤ L
3≤ L
2; Second wordline polysilicon layer, is arranged on the second substrate between second grid structure.
Further, above-mentioned L
3=(L
1+ L
2)/2.
Further, the CD of above-mentioned first grid structure is W
1, the CD of second grid structure is W
2, and W
2≤ W1.
Further, above-mentioned CMP measurement structure is first direction along the distribution arrangement of second grid structure, and the direction vertical with the upper surface of the second substrate with first direction is second direction, and second grid structure is symmetrical arranged along the axis face of second direction.
Further, above-mentioned second grid structure comprises grid and is positioned at the side wall on gate lateral wall, and side wall is symmetrical arranged along axis face.
Further, above-mentioned grid comprise successively away from second substrate arrange: the first insulating barrier, is arranged on the second substrate; First polysilicon layer, is arranged on the first insulating barrier; Second insulating barrier, is arranged on the first polysilicon layer; Second polysilicon layer, is arranged over the second dielectric; Hard mask layer, is arranged on the second polysilicon layer, and the upper surface of hard mask layer is parallel with the upper surface of the second substrate.
Further, above-mentioned side wall comprises: the first side wall, is arranged on the sidewall of the second insulating barrier, the second polysilicon layer and hard mask layer; Second side wall, is arranged on the exposed sidewall of the first insulating barrier, the first polysilicon layer and the first side wall.
Further, above-mentioned first insulating barrier is oxide skin(coating); Second insulating barrier is silicon oxide layer, silicon nitride layer, ON layer or ONO layer.
Further, above-mentioned hard mask layer comprises successively away from the first silicon nitride layer, silicon oxide layer that the second polysilicon layer is arranged.
Further, above-mentioned hard mask layer also comprises the second silicon nitride layer being arranged on silicon oxide layer upper surface.
Further, above-mentioned second wordline polysilicon layer comprises: wordline grid oxygen oxide layer, is arranged on the second substrate between second grid structure; Polysilicon layer, is arranged in the wordline grid oxygen oxide layer between second grid structure.
Further, above-mentioned second substrate and the first substrate are wholely set.
According to the another aspect of the application, provide a kind of manufacture method of separate grid type memory, this manufacture method comprises: step S1, make multiple first grid structure and the first wordline polysilicon layer of separate grid type memory, spacing between first grid structure is different, and wherein the first spacing is L
1, the second spacing is L
2, and L
1< L
2; Step S2, carries out CMP to the first wordline polysilicon layer of separate grid type memory and the second wordline polysilicon layer of above-mentioned wordline CMP measuring structure; Step S3, measures structure to the wordline CMP after CMP and measures.
Further, above-mentioned manufacture method also comprises the manufacturing process of wordline CMP measuring structure, and the first grid structure of manufacturing process and separate grid type memory and the manufacturing process of the first wordline polysilicon layer are carried out simultaneously.
Further, above-mentioned steps S3 adopts scatterometry measurements to measure.
The technical scheme of application the application, second grid structure is close to consistent with the height of the first grid structure of separable grid memory, structural similarity, and distribute spacing is close, therefore the surface topography produced after wordline polysilicon deposition is suitable with memory cell areas, thus in CMP process, the second grid structure of measuring structure is similar to the stressed of first grid structure and polishing process, accurately can reflect the CMP effect of first grid structure and the first wordline polysilicon layer; And the second grid structure of above-mentioned measuring structure equidistantly distributes, the measurement accuracy measuring base station can be strengthened, realize accurate measurement.
Accompanying drawing explanation
The Figure of description forming a application's part is used to provide further understanding of the present application, and the schematic description and description of the application, for explaining the application, does not form the improper restriction to the application.In the accompanying drawings:
Fig. 1 shows the flow chart of the wordline manufacture method of separate grid type memory in prior art;
The wafer cross structural representation that Fig. 2 to Fig. 7 obtains after showing and implementing each step of wordline manufacture method shown in Fig. 1;
Fig. 2 shows the cross-sectional view of the wafer that prior art provides;
Fig. 3 shows the cross-sectional view after the upper wafer surface deposit spathic silicon shown in Fig. 2 forms ground floor polysilicon membrane;
Fig. 4 shows the cross-sectional view after the upper surface of the ground floor polysilicon membrane shown in Fig. 3 forms oxide-isolation layer and photoresist layer successively;
Fig. 5 shows the cross-sectional view after etching the wafer shown in Fig. 4;
Fig. 6 shows and removes the photoresist layer shown in Fig. 5 and cross-sectional view after the upper surface deposit spathic silicon of the ground floor polysilicon membrane of wafer and oxide-isolation layer forms second layer polysilicon membrane;
Fig. 7 shows and carries out the cross-sectional view after wordline chemico-mechanical polishing to the wafer shown in Fig. 6;
Fig. 8 shows the cross-sectional view of the wordline CMP measuring structure that a kind of preferred implementation of the application provides;
Fig. 9 shows the flow chart of the manufacture method of the separate grid type memory that a kind of preferred implementation of the application provides;
The making that Figure 10 to Figure 29 shows a kind of preferred implementation of the application to be provided has the cross-sectional view after each step of the measuring structure of wordline CMP shown in Fig. 8, wherein,
Figure 10 shows the cross-sectional view of the second substrate that above-mentioned preferred implementation provides, and this second substrate is divided into memory circuit district, peripheral circuit region and measuring structure district;
Figure 11 shows the cross-sectional view to form the first insulating barrier, the first polysilicon layer, the second insulating barrier, the second polysilicon layer and hard mask layer successively on the second substrate shown in Figure 10 after;
Figure 12 shows the cross-sectional view to form the first photoresist mask on the hard mask shown in Figure 11 after;
Figure 13 shows and carries out etching the cross-sectional view after forming first cascade structure successively to the hard mask layer in Figure 12, the second polysilicon layer and the second insulating barrier;
Figure 14 shows the cross-sectional view after the first cascade structure both sides shown in Figure 13 form the first side wall;
Figure 15 shows and form the cross-sectional view after sacrificing side wall on the side of the first side wall shown in Figure 14;
It is L that Figure 16 shows spacing in the memory cell areas shown in Figure 15
1adjacent layer stack structure between and segments first layer stack structure is arranged the cross-sectional view after the second photoresist mask;
Figure 17 shows and etches and cross-sectional view after removing the second photoresist mask sacrificing side wall under the protection of the second photoresist mask shown in Figure 16;
Figure 18 shows and etches the cross-sectional view after obtaining first grid structure and second grid structure to the first polysilicon layer shown in Figure 17 and the first insulating barrier;
Figure 19 shows and removes the sacrifice side wall shown in Figure 18 and first insulating barrier that may remain and cross-sectional view form the second side wall on the first side wall side after;
Figure 20 shows the cross-sectional view to arrange the 3rd photoresist mask in the structure shown in Figure 19 after, and the opening of the 3rd photoresist mask is positioned at the second photoresist mask position shown in Figure 16;
Figure 21 show under the protection of the 3rd photoresist mask shown in Figure 20, the first substrate to be carried out ion implantation form ion implanted region after cross-sectional view;
Figure 22 shows and etches not by the cross-sectional view after the second side wall of the 3rd photoresist mask protection under the protection of the 3rd photoresist mask shown in Figure 21;
Figure 23 shows and removes the 3rd photoresist mask of Figure 22 and the cross-sectional view after forming sidewall grid oxide layer;
Figure 24 shows and the first substrate shown in Figure 23, the second substrate surface is carried out to thermal oxidation and form the cross-sectional view after combined oxidation silicon layer;
Figure 25 shows above the ion implanted region of the memory cell areas shown in Figure 24 and both sides, ion implanted region and cross-sectional view after half first grid superstructure of ion implanted region arranges the 4th photoresist mask;
Figure 26 shows the cross-sectional view after etching the structure shown in Figure 25 under the protection of the 4th photoresist mask shown in Figure 25;
Figure 27 shows and removes the 4th photoresist mask shown in Figure 26 and cross-sectional view after the first substrate, the second substrate surface form wordline grid oxygen oxide layer;
Figure 28 shows the cross-sectional view after the first substrate shown in Figure 27 and the second deposited on substrates polysilicon form polysilicon layer; And
Figure 29 shows and carries out the cross-sectional view after CMP to the polysilicon layer shown in Figure 28.
Embodiment
It is noted that following detailed description is all exemplary, be intended to provide further instruction to the application.Unless otherwise, all technology used herein and scientific terminology have the identical meanings usually understood with the application person of an ordinary skill in the technical field.
It should be noted that used term is only to describe embodiment here, and be not intended to the illustrative embodiments of restricted root according to the application.As used herein, unless the context clearly indicates otherwise, otherwise singulative is also intended to comprise plural form, in addition, it is to be further understood that, when use belongs to " comprising " and/or " comprising " in this manual, it indicates existing characteristics, step, operation, device, assembly and/or their combination.
For convenience of description, here can usage space relative terms, as " ... on ", " in ... top ", " at ... upper surface ", " above " etc., be used for the spatial relation described as a device shown in the figure or feature and other devices or feature.Should be understood that, space relative terms is intended to comprise the different azimuth in use or operation except the described in the drawings orientation of device.Such as, " in other devices or structure below " or " under other devices or structure " will be positioned as after if the device in accompanying drawing is squeezed, being then described as the device of " above other devices or structure " or " on other devices or structure ".Thus, exemplary term " in ... top " can comprise " in ... top " and " in ... below " two kinds of orientation.This device also can other different modes location (90-degree rotation or be in other orientation), and relatively describe space used here and make respective explanations.
Introduce as background technology, the wordline CMP process of existing separate grid type memory, the wordline CMP measuring structure adopted is planar structure, be difficult to the real structure reflecting separated grid, therefore effective monitoring can not be carried out to wordline CMP process, in order to solve as above problem, present applicant proposes a kind of wordline CMP measuring structure and wordline CMP method for measurement of separate grid type memory.
Wherein a kind of wordline CMP measuring structure of preferred embodiment provided separate grid type memory as shown in Figure 8, this separate grid type memory comprises the first substrate 10 and the multiple first grid structures 11 be arranged on the first substrate 10 and the first wordline polysilicon layer 12, spacing between multiple first grid structure 11 is different, and wherein the first spacing is L
1, the second spacing is L
2, and L
1< L
2wordline CMP measuring structure comprises the second substrate 20, multiple second grid structure 21 and the second wordline polysilicon layer 22, second substrate 20 and the first substrate 10 are integrated and arrange or relatively independent setting, and second grid structure 21 is arranged on the second substrate 20 equally spacedly, and spacing is L
3, and L
1≤ L
3≤ L
2; Second wordline polysilicon layer 22 is arranged on the second substrate 20 between second grid structure 21.
There is the measuring structure of said structure, second grid structure 21 is wherein close to consistent with the height of the first grid structure 11 of separable grid memory, structural similarity, and distribute spacing is close, therefore the surface topography produced after wordline polysilicon deposition is suitable with memory cell areas, thus in CMP process, the second grid structure 21 of measuring structure is similar to the stressed of first grid structure 11 and polishing process, accurately can reflect the CMP effect of first grid structure 11 and the first wordline polysilicon layer 12; And the second grid structure 21 of above-mentioned measuring structure equidistantly distributes, the measurement accuracy measuring base station can be strengthened, realize accurate measurement.Second substrate 20 of the wordline CMP measuring structure of the application can be wholely set with the first substrate 10 of separate grid type memory and also can relatively independently arrange, when being wholely set, wordline CMP measuring structure is made while the first grid structure 11 making separate grid type memory and the first wordline polysilicon layer 12, relatively independent when arranging, wordline CMP measurement independently makes relative to separate grid type memory, and in order to detect the effect of wordline CMP better, preferably both are wholely set.
The spacing of the second grid structure 21 of measuring structure, in order to reflect the CMP effect of the first grid structure 11 of different spacing better, is set to L by the application
3=(L
1+ L
2)/2.
The application provides accurate, strong light signal in order to make second grid structure 21 for measuring base station, and the upper surface of above-mentioned second grid structure 21 is set to the surface parallel with the upper surface of the second substrate 20.
In the application's another preferred embodiment, CMP measurement structure is first direction along the distribution arrangement of second grid structure 21, the direction vertical with the upper surface of the second substrate 20 with first direction is second direction, and second grid structure 21 is symmetrical arranged along the axis face of second direction.Above-mentioned symmetrically arranged second grid structure 21 more meets the light reflection requirement measuring base station, therefore, more accurate with the measuring structure that it obtains for benchmark.
The first grid structure 11 of separate grid type memory of the prior art comprises stacked grid and is positioned at the side wall 202 of stacked grid both sides, the application is in order to reflect the wordline CMP result of separate grid type memory more exactly, the side wall 212 that preferred second grid structure 21 comprises grid 211 and is positioned on grid 211 sidewall, and in order to meet the requirement measuring base station better, side wall 212 is symmetrical arranged along axis face.
The first grid structure 11 in order to imitate separate grid type memory equally, as shown in Figure 8 (can in conjunction with Figure 12), the grid structure 211 of the wordline CMP measuring structure of preferred the application comprises the first insulating barrier 111, first polysilicon layer 112, second insulating barrier 113, second polysilicon layer 114 of arranging away from the second substrate 20 successively and hard mask layer 115, first insulating barrier 111 is arranged on the second substrate 20; First polysilicon layer 112 is arranged on the first insulating barrier 111; Second insulating barrier 113 is arranged on the first polysilicon layer 112; Second polysilicon layer 114 is arranged on the second insulating barrier 113; Hard mask layer 115 is arranged on the second polysilicon layer 114, and the upper surface of hard mask layer 115 is parallel with the upper surface of the second substrate 20.Wherein, the first insulating barrier 111 is silicon oxide layer; Second insulating barrier 113 is silicon oxide layer, silicon nitride layer, ON layer or ONO layer, and those skilled in the art are noted that ON layer is the double-decker that silicon oxide layer and silicon nitride layer are formed, and ONO layer is the sandwich structure that silica, silicon nitride and silica are formed.
Preferred above-mentioned side wall 212 comprises the first side wall 121 and the second side wall 123, and with reference to figure 8 (combining see Figure 11 and 12), the first side wall 121 is arranged on the sidewall of the second insulating barrier 113, second polysilicon layer 114 and hard mask layer 115; Second side wall 123 is arranged on the exposed sidewall of the first insulating barrier 111, first polysilicon layer 112 and the first side wall 121.
The hard mask layer 115 of the application can be single layer structure can be also double-deck or sandwich construction, and preferred above-mentioned mask layer comprises successively away from the first silicon nitride layer, silicon oxide layer that the second polysilicon layer 114 is arranged.Further preferred above-mentioned hard mask layer 115 also comprises the second silicon nitride layer being arranged on silicon oxide layer upper surface.
The second wordline polysilicon layer 22 of the application also with the first wordline polysilicon layer 12 structural similarity of the prior art, preferably include wordline grid oxygen oxide layer 221 and polysilicon layer 222, wordline grid oxygen oxide layer 221 is arranged on the second substrate 20 between second grid structure 21; Polysilicon layer 222 is arranged in the wordline grid oxygen oxide layer 221 between second grid structure 21.
The application's another preferred embodiment provides a kind of manufacture method of separate grid type memory, this manufacture method comprises: step S1, make multiple first grid structures 11 and the first wordline polysilicon layer 12 of separate grid type memory, spacing between first grid structure 11 is different, and wherein the first spacing is L
1, the second spacing is L
2, and L
1< L
2; Step S2, carries out CMP to the second wordline polysilicon layer 22 of the first wordline polysilicon layer 12 of separate grid type memory and the wordline CMP measuring structure of the application; Step S3, measures structure to the wordline CMP after CMP and measures.
Due to the second grid structure 21 of the measuring structure of the application and the structural similarity of the first grid structure 11 of separable grid memory, highly be close to consistent, and distribute spacing is close, therefore the surface topography produced after wordline polysilicon deposition is suitable with memory cell areas, thus in CMP process, the second grid structure 21 of measuring structure is similar to the stressed of first grid structure 11 and polishing process, accurately can reflect the CMP effect of first grid structure 11 and the first wordline polysilicon layer 12; And the second grid structure 21 of above-mentioned measuring structure equidistantly distributes, the measurement accuracy measuring base station can be strengthened, realize accurate measurement; And above-mentioned measurement process adopts the existing scatterometry base station for measuring critical size to carry out measuring.
In order to the structure of the first grid structure 11 and the first wordline polycrystal layer of simulating separate grid type memory more accurately, preferred above-mentioned manufacture method also comprises the manufacturing process of wordline CMP measuring structure, and the first grid structure 11 of manufacturing process and separate grid type memory and the manufacturing process of the first wordline polysilicon layer 12 are carried out simultaneously.The preferred above-mentioned steps S3 of the application adopts scatterometry measurements (Scatterometry) to measure.
Now, the illustrative embodiments according to the application is described with reference to the accompanying drawings in more detail.But these illustrative embodiments can be implemented by multiple different form, and should not be interpreted as being only limited to execution mode set forth herein.Should be understood that, there is provided these execution modes be in order to make the application open thorough and complete, and the design of these illustrative embodiments is fully conveyed to those of ordinary skill in the art, in the accompanying drawings, for the sake of clarity, expand the thickness in layer and region, and use the device that identical Reference numeral represents identical, thus will omit description of them.
Wherein, be wholely set for the first substrate 10 and the second substrate 20, namely carry out the first grid structure 11 of separate grid type memory and the manufacturing process of the first wordline polysilicon layer 12 and the manufacturing process of wordline CMP measuring structure is example simultaneously, and idiographic flow as shown in Figure 9.
First, semiconductor base is as shown in Figure 10 provided, this semiconductor base comprises memory circuit district I, peripheral circuit region and measuring structure district II (wherein peripheral circuit region is not shown), wherein, semiconductor second substrate in corresponding storage circuit district is the first substrate 10 of the application's separate grid type memory, and semiconductor second substrate in corresponding amount geodesic structure district is the second substrate 20 of the application's measuring structure.
Then, the first substrate 10 shown in Figure 10 and the second substrate 20 form the first insulating barrier 111, first polysilicon layer 112, second insulating barrier 113, second polysilicon layer 114 and hard mask layer 115 successively, form the device with cross-section structure shown in Figure 11.Wherein, the first insulating barrier 111 is silicon oxide layer; Second insulating barrier 113 is silicon oxide layer, silicon nitride layer, ON layer or ONO layer, those skilled in the art are noted that ON layer is the double-decker that silicon dioxide layer and silicon nitride layer are formed, and ONO layer is the sandwich structure that silica, silicon nitride and silica are formed.Hard mask layer 115 comprises successively away from the first silicon nitride layer, silicon oxide layer that the second polysilicon layer 114 is arranged.Further preferred above-mentioned hard mask layer 115 also comprises the second silicon nitride layer being arranged on silicon oxide layer upper surface.
Then, hard mask 115 shown in Figure 11 arranges photoresist, then graphical treatment is carried out to photoresist, obtain the first photoresist mask 31 spaced apart shown in Figure 12, wherein, memory cell areas graphical after remaining first photoresist mask 31 spacing not etc., wherein, the first spacing is L
1, the second spacing is L
2, and L
1< L
2; And the spacing being positioned at the photoresist mask in measuring structure district is all L mutually
3.Pass between above-mentioned spacing is L
1≤ L
3≤ L
2, preferred L
3=(L
1+ L
2)/2.
Under the protection of the first photoresist mask 31 shown in Figure 12; hard mask layer 115, second polysilicon layer 114 in Figure 12 and the second insulating barrier 113 are etched successively; obtain the spaced first cascade structure 41 shown in Figure 13, preferably adopt dry etching to implement this etching process.With reference to figure 8 and Figure 13, can find out, in the gap corresponding diagram 8 between the first cascade structure 41 of memory cell areas, spacing is L
1or L
2position, and spacing between the first cascade structure 41 in measuring structure district is identical, and L in this interstitial site corresponding diagram 8
3position.
After removing above-mentioned first photoresist mask 31, first cascade structure 41 both sides shown in Figure 13 form the first side wall 121 shown in Figure 14, this first side wall 121 can be the composite bed of silicon oxide layer, silicon nitride layer or silica and silicon nitride, the silicon oxide layer such as outwards set gradually by inner side and silicon nitride layer form this first side wall 121, deposition, etching mode that wherein the generation type of the first side wall 121 adopts this area conventional carry out implementing, and do not repeat them here.
After forming the first side wall 121, the first side wall 121 side shown in Figure 14 forms the sacrifice side wall 122 shown in Figure 15, and it consists of silicon oxide layer, and generation type is this area common method, such as adopts the method for above-mentioned formation first side wall 121.
Then, the first polysilicon layer 112 shown in Figure 15, first cascade structure 41, first side wall 121 and sacrifice side wall 122 arrange photoresist, then graphical treatment is carried out to photoresist, obtain the second photoresist mask 32 shown in Figure 16.As can be seen from Figure 16, the second photoresist mask 32 is only kept at memory cell areas, and to cover spacing be L
1adjacent layer stack structure between and on segments first layer stack structure 41, remainder is all exposed.
Under the protection of the second photoresist mask 32 shown in Figure 16; shown in etching Figure 16 not by sacrifice side wall 122 that the second photoresist mask 32 is protected; preferred employing wet etching implements this etching process; etch the above-mentioned second photoresist mask 32 of rear removal; obtain the one-sided sacrifice side wall 122 inside first cascade structure 41 Small Distance as shown in figure 17, this one-sided sacrifice side wall 122 is only present in memory cell areas as seen from Figure 17.
Successively the first polysilicon layer 112 shown in Figure 17 and the first insulating barrier 111 are etched, obtain the first grid structure 11 shown in Figure 18 and second grid structure 21, preferably adopt dry etching to implement.As seen from Figure 18, the first polysilicon layer 112 being positioned at the second grid structure 21 below the first side wall 121 is symmetrical arranged.
Wet etching is used to remove the one-sided sacrifice side wall 122 (first insulating barrier 111 that now may remain also is removed) shown in Figure 18 and the first side wall 121 side in figure 18 forms the second side wall 123 shown in Figure 19.Wherein the second side wall 123 forms method is also this area common method, such as the first side wall 121 and the formation method of sacrificing side wall 122.
The first substrate 10 shown in Figure 19 and the second substrate 20, first side wall 121, second side wall 123, first grid structure 11 and second grid structure 21 arrange photoresist, then graphical treatment is carried out to this photoresist, form the 3rd photoresist mask 33 shown in Figure 20, wherein, the opening that the 3rd photoresist is formed is positioned at the position corresponding to the second photoresist mask 32.
Under the protection of the 3rd photoresist mask 33 shown in Figure 20, ion implantation is carried out to the first substrate 10 shown in Figure 20, form the ion implanted region 13 shown in Figure 21.As seen from Figure 21; except the second substrate 10 of the Small Distance part of memory cell areas is exposed; other parts are all in the protection of the 3rd photoresist mask 33, and therefore, ion implantation does not have an impact to the first substrate 10 except Small Distance part and the second substrate 20.
Continue under the protection of the 3rd photoresist mask 33; etching is not by the second side wall 123 that the 3rd photoresist mask 33 is protected; until expose the first polysilicon 112 sidewall of the first grid structure 11 (the first grid structure 11 see Figure 18 indicates) shown in Figure 21, form the structure shown in Figure 22.Same because the protection of the 3rd photoresist mask 33, the second side wall 123 structure of second grid structure 21 both sides of the measuring structure in Figure 22 is not removed, and still keeps being symmetrical arranged.
Remove the 3rd photoresist mask 33 shown in Figure 22, and on the first polysilicon 112 sidewall of the structure 11 of first grid shown in Figure 22 top, the first side wall 121, second side wall 123, first grid structure 11, in the first substrate 10, second substrate 20 and second grid structure 21 deposition oxide, form the sidewall grid oxide layer 124 shown in Figure 23.
Carry out thermal oxidation to the first substrate 10, second substrate 20 surface shown in Figure 23 and form the combined oxidation silicon layer 223 shown in Figure 24, this combined oxidation silicon layer 223 also can be used as part or all (not shown) of the gate oxygen structure of peripheral circuit region part components and parts.Because memory cell areas I Small Distance part first substrate 20 is ion implanted region 13, therefore in thermal oxidation process, oxidation rate is very fast relative to the first substrate 20 without ion implantation, thus forms circular projection (dome).And measuring structure district II second substrate 10 is not injected into ion, therefore oxide layer is comparatively smooth, therefore can not have an impact to the measurement performance measuring base station.
On silicon oxide layer 223 upper surface of Figure 24, sidewall grid oxide layer 124 surface, photoresist is set, then graphical treatment is carried out to this photoresist, form above the ion implanted region 13 being positioned at memory cell areas shown in Figure 25 and both sides, ion implanted region 13 and the 4th photoresist mask 34 above half first grid structure 11 of ion implanted region 13.
Under the protection of the 4th photoresist mask 34; structure shown in Figure 25 is etched; form the cross-section structure shown in Figure 26; wherein; due to the existence of the 4th photoresist mask 34; first grid structure 11 top section after making to etch is etched; and the top of the second grid structure 21 in measuring structure district is etched simultaneously; therefore the top of second grid structure 21 is still more smooth; be symmetrical set; in addition, the sidewall gate oxide in Figure 25 is also partially etched, and on the first substrate 10 and the second substrate 20, exposed silicon oxide layer is all etched.
After completing above-mentioned etching, remove the 4th photoresist mask 34 shown in Figure 26 and carry out thermal oxidation, forming the wordline grid oxygen oxide layer 221 shown in Figure 27 on the first exposed substrate 10, second substrate 20 surface.
Then, on the first substrate 10 shown in Figure 27 and the second substrate 20 deposit spathic silicon formed shown in Figure 28 polysilicon layer 222, polysilicon layer 222 is wherein formed (dotted line in Figure 27 represents the line of demarcation of the polysilicon of twice deposition in front and back) preferably through twice polysilicon deposition, be positioned at the precursor that the polysilicon layer 222 of memory cell areas and wordline grid oxygen oxide layer 221 form the first wordline polysilicon layer 12 of measuring structure, be positioned at the precursor that the polysilicon layer 222 in measuring structure district and wordline grid oxygen oxide layer 221 form the second wordline polysilicon layer 22 of measuring structure.Because the second grid structure 21 in memory cell areas first grid structure 11 and measuring structure district have passed through same Making programme, therefore its physical property is identical, and then the first wordline polysilicon layer 12 formed through identical deposition process and the physical property of the second wordline polysilicon layer 22 are also identical.
Then, CMP is carried out to the polysilicon layer 22 shown in Figure 28, form the device with cross-section structure shown in Figure 29.The polysilicon layer 222 being positioned at memory cell areas forms the first wordline polysilicon layer 12 of measuring structure with wordline grid oxygen oxide layer 221 after CMP, and the polysilicon layer 222 being positioned at measuring structure district forms the second wordline polysilicon layer 22 of measuring structure with wordline grid oxygen oxide layer 221 after CMP.Due to the symmetrical and periodic arrangement of second substrate 20 surfacing in measuring structure district, second grid structure 11, therefore, when measuring for measuring sample with it, CMP polishing and effect can be reflected exactly; And experienced by identical manufacture craft due to measuring structure district and memory cell areas, therefore, the measurement that utilization geodesic structure provides accurately, truly can reflect polishing and the effect of the wordline CMP of memory cell areas.
Described above is only the method that the application preferably makes wordline CMP measuring structure, and those skilled in the art can adopt the combination of the technological means of this area routine to carry out separately the making of wordline CMP measuring structure, do not repeat them here.
As can be seen from the above description, the application's the above embodiments achieve following technique effect:
1), there is the measuring structure of said structure, the structural similarity of second grid structure wherein and the first grid structure of separable grid memory, highly be close to consistent, and distribute spacing is close, therefore the surface topography produced after wordline polysilicon deposition is suitable with memory cell areas, thus in CMP process, the second grid structure of measuring structure is similar to the stressed of first grid structure and polishing process, accurately can reflect the CMP effect of first grid structure and the first wordline polysilicon layer;
2), the second grid structure of above-mentioned measuring structure is equidistantly symmetrical, can strengthen the measurement accuracy measuring base station, realize accurate measurement.
The foregoing is only the preferred embodiment of the application, be not limited to the application, for a person skilled in the art, the application can have various modifications and variations.Within all spirit in the application and principle, any amendment done, equivalent replacement, improvement etc., within the protection range that all should be included in the application.
Claims (15)
1. the wordline CMP measuring structure of a separate grid type memory, described separate grid type memory comprises the first substrate and the multiple first grid structure be arranged on described first substrate and the first wordline polysilicon layer, spacing between multiple described first grid structure is different, and wherein the first spacing is L
1, the second spacing is L
2, and L
1< L
2, it is characterized in that, described wordline CMP measuring structure comprises:
Second substrate, described second substrate and described first substrate are integrated and arrange or relatively independent setting;
Multiple second grid structure, be arranged on described second substrate equally spacedly, described spacing is L
3, and L
1≤ L
3≤ L
2;
Second wordline polysilicon layer, is arranged on described second substrate between described second grid structure.
2. wordline CMP measuring structure according to claim 1, is characterized in that, described L
3=(L
1+ L
2)/2.
3. wordline CMP measuring structure according to claim 1, is characterized in that, the CD of described first grid structure is W
1, the CD of described second grid structure is W
2, and W
2≤ W1.
4. wordline CMP measuring structure according to claim 1, it is characterized in that, described CMP measurement structure is first direction along the distribution arrangement of described second grid structure, the direction vertical with the upper surface of described second substrate with described first direction is second direction, and described second grid structure is symmetrical arranged along the axis face of second direction.
5. wordline CMP measuring structure according to claim 4, is characterized in that, described second grid structure comprises grid and is positioned at the side wall on described gate lateral wall, and described side wall is symmetrical arranged along described axis face.
6. wordline CMP measuring structure according to claim 5, is characterized in that, described grid comprise successively away from described second substrate arrange:
First insulating barrier, is arranged on described second substrate;
First polysilicon layer, is arranged on described first insulating barrier;
Second insulating barrier, is arranged on described first polysilicon layer;
Second polysilicon layer, is arranged on described second insulating barrier;
Hard mask layer, is arranged on described second polysilicon layer, and the upper surface of described hard mask layer is parallel with the upper surface of described second substrate.
7. wordline CMP measuring structure according to claim 6, is characterized in that, described side wall comprises:
First side wall, is arranged on the sidewall of described second insulating barrier, described second polysilicon layer and described hard mask layer;
Second side wall, is arranged on the exposed sidewall of described first insulating barrier, the first polysilicon layer and the first side wall.
8. wordline CMP measuring structure according to claim 6, is characterized in that, described first insulating barrier is oxide skin(coating);
Described second insulating barrier is silicon oxide layer, silicon nitride layer, ON layer or ONO layer.
9. wordline CMP measuring structure according to claim 6, is characterized in that, described hard mask layer comprises successively away from the first silicon nitride layer, silicon oxide layer that described second polysilicon layer is arranged.
10. wordline CMP measuring structure according to claim 9, is characterized in that, described hard mask layer also comprises the second silicon nitride layer being arranged on described silicon oxide layer upper surface.
11. wordline CMP measuring structures according to claim 1, is characterized in that, described second wordline polysilicon layer comprises:
Wordline grid oxygen oxide layer, is arranged on described second substrate between second grid structure;
Polysilicon layer, is arranged in the described wordline grid oxygen oxide layer between described second grid structure.
12. wordline CMP measuring structures according to any one of claim 1 to 11, it is characterized in that, described second substrate and described first substrate are wholely set.
The manufacture method of 13. 1 kinds of separate grid type memories, is characterized in that, described manufacture method comprises:
Step S1, makes multiple first grid structure and the first wordline polysilicon layer of described separate grid type memory, and the spacing between described multiple first grid structure is different, and wherein the first spacing is L
1, the second spacing is L
2, and L
1< L
2;
Step S2, carries out CMP to the second wordline polysilicon layer of the wordline CMP measuring structure according to any one of the first wordline polysilicon layer of described separate grid type memory and claim 1 to 11;
Step S3, measures structure to the described wordline CMP after CMP and measures.
14. manufacture methods according to claim 13, it is characterized in that, described manufacture method also comprises the manufacturing process of described wordline CMP measuring structure, and the first grid structure of described manufacturing process and described separate grid type memory and the manufacturing process of the first wordline polysilicon layer are carried out simultaneously.
15. manufacture methods according to claim 13, is characterized in that, described step S3 adopts scatterometry measurements to measure.
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|---|---|---|---|---|
| US20010026364A1 (en) * | 2000-02-20 | 2001-10-04 | Nova Measuring Instruments Ltd. | Test structure for metal CMP process control |
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| US20070082490A1 (en) * | 2005-10-06 | 2007-04-12 | Chun-Ting Hu | Apparatus of chemical mechanical polishing and chemical mechanical polishing process |
| CN102522354A (en) * | 2012-01-12 | 2012-06-27 | 中国科学院微电子研究所 | Method and device for extracting square resistances of interconnection lines |
| CN102810492A (en) * | 2011-06-03 | 2012-12-05 | 中国科学院微电子研究所 | Processing procedure monitoring method after CMP for metal gate |
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2014
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010026364A1 (en) * | 2000-02-20 | 2001-10-04 | Nova Measuring Instruments Ltd. | Test structure for metal CMP process control |
| CN1435297A (en) * | 2002-01-31 | 2003-08-13 | 旺宏电子股份有限公司 | Method for monitoring measuring chemicomechanical grinding |
| US20070082490A1 (en) * | 2005-10-06 | 2007-04-12 | Chun-Ting Hu | Apparatus of chemical mechanical polishing and chemical mechanical polishing process |
| CN102810492A (en) * | 2011-06-03 | 2012-12-05 | 中国科学院微电子研究所 | Processing procedure monitoring method after CMP for metal gate |
| CN102522354A (en) * | 2012-01-12 | 2012-06-27 | 中国科学院微电子研究所 | Method and device for extracting square resistances of interconnection lines |
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