KR102134607B1 - Ssl/gsl gate oxide in 3d vertical channel nand - Google Patents

Abstract

The memory device includes an array of strings of memory cells. The device comprises stacks of conductive strips separated by a plurality of insulating materials and having at least a lower plane of conductive strips, an intermediate plane of the plurality of conductive strips and an upper plane of the conductive strips. A plurality of vertical active strips are formed between the stacks. Charge storage structures are formed in interface regions at intersections between the side surfaces of the conductive strips in the plurality of intermediate planes and the vertical active strips in the plurality of vertical active strips. A gate dielectric having a composition different from the charge storage structures is formed in interface regions at intersections between the vertical active strips and at least one of the upper plane of the conductive strips and the lower plane of the conductive strips.

Description

String selection line/ground selection line gate oxide in 3D vertical channel NAND {SSL/GSL GATE OXIDE IN 3D VERTICAL CHANNEL NAND}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to high density memory devices, and more particularly, to memory devices in which multiple layers of memory cells are arranged to provide a three dimensional (3D) array.

In recent years, 3D memory devices have been developed in a variety of configurations including stacks of conductive strips separated by insulating material and vertical active strips between the stacks. Memory cells comprising charge storage structures are disposed in the interfacial regions between the vertical active strips and the intermediate planes of the conductive strips in the stacks. String select switches are disposed in the interface regions between the vertically active strips and the upper plane of the conductive strips in the stacks. Reference selection switches are arranged in the interface regions between the lower active planes of the conductive strips in the stacks and the vertical active strips. In order to reliably control the operation of the memory cells, it is preferable that the threshold voltages of the string selection switches and the reference selection switches are stable. When the string select switches and the reference select switches include charge storage structures as the memory cells, the string select switches and the reference select switches can be charged such that their threshold voltage can be changed, thereby programming the switches And additional circuitry to erase.

It is desirable to provide a structure for a three-dimensional integrated circuit memory that provides string select switches and reference select switches with stable threshold voltages without requiring additional circuitry to control the threshold voltages while memory cells are programmed or erased.

The memory device includes an array of strings of memory cells. The device is separated by an insulating material and has at least a lower plane (GSL) of conductive strips, a middle plane (WL) of a plurality of conductive strips and a top plane (SSL) of conductive strips. Includes stacks of conductive strips. A plurality of vertical active strips are disposed between the plurality of stacks. Charge storage structures are disposed in interface regions at intersections between the side surfaces of the conductive strips in the plurality of intermediate planes in the stacks and the vertical active strips in the plurality of vertically active strips. Gate dielectrics having a composition different from the charge storage structures are between the vertical active strips in the plurality of active strips and the top surfaces of the conductive strips and side surfaces of the conductive strips in at least one of the bottom surfaces of the conductive strips. Are placed in the interfacial regions at the intersections of.

The device may include silicide formations on the upper plane (SSL) of the conductive strips. The device may include spacers separating the vertical active strips from the upper plane of the conductive strips, and silicide formations on top of the vertical active strips. The gate dielectric may include a layer of silicon oxide thinner than the charge storage structures. The gate dielectric may have a thickness of about seven (7) nanometers.

A reference conductor is disposed within the level between the lower plane of the conductive strips and the integrated circuit board, and is connected to the plurality of vertical active strips. The reference conductor may include an N+ doped semiconductor material.

Methods for manufacturing memory devices as described herein are also provided.

Other aspects and advantages of the invention will be apparent through the following review of the accompanying drawings, detailed description and claims.

According to embodiments of the present invention, a three-dimensional integrated circuit memory device that provides string selection switches and reference selection switches with stable threshold voltages without requiring additional circuitry to adjust threshold voltages while memory cells are programmed or erased. You can implement

1 is a cross-sectional view of a three-dimensional (3D) memory device according to an embodiment of the present invention.
1A is a cross-sectional view of a 3D memory device in accordance with an alternative embodiment of the present invention.
1B is a cross-sectional view of a 3D memory device according to another alternative embodiment of the present invention.
2 is a simplified block diagram of an integrated circuit according to an embodiment of the present invention.
3 is a flow diagram illustrating a method for manufacturing a memory device.
4 to 15 illustrate an example of a process for manufacturing a memory device.
16-27 illustrate an example of an optional process for manufacturing a memory device.

A detailed description of embodiments of the invention is provided with reference to the accompanying drawings. The following description will generally refer to embodiments and methods of a particular structure. It should be understood that the invention is not limited to the embodiments and methods specifically disclosed herein, and that the invention can be implemented using other features, elements, methods and embodiments. Preferred embodiments are described with the intention of illustrating the invention, and do not limit the scope of the invention as defined by the claims. Those skilled in the art will appreciate that various equivalent modifications can be performed from the following description. The same elements in various embodiments are commonly referred to as the same reference numerals.

1 is a cross-sectional view showing a three-dimensional (3D) memory device 100 according to an embodiment of the present invention in an X-Z plane. As illustrated in the embodiment of FIG. 1, memory device 100 includes an array of NAND strings of memory cells formed on an integrated circuit board. The device is separated by an insulating material (e.g. 105, 115, 125, 135, 145, 155), at least a lower plane (GSL) of conductive strips (e.g. 111-114), a plurality of Equipped with intermediate planes WL of conductive strips (e.g. 121-124, 131-134, 141-144), and upper planes (SSL) of conductive strips (e.g. 151-154) It includes a stack of a plurality of conductive strips (strips). A plurality of vertical active strips (eg, 161, 162) are disposed between the stacks. Charge storage structures (eg, 141m, 142m, 143m, 144m) are the side surfaces of the conductive strips in the plurality of intermediate planes in the stacks and the vertical active strips in the plurality of vertical active strips It is disposed within the interface regions at the intersections between. The insulating material (e.g., 170) is adjacent to a stack of conductive strips (e.g., 112, 122, 132, 142, 152) and conductive strips (e.g., 113, 123, 133, 143, 153) ).

The gate dielectric (eg, 111g, 112g, 113g, 114g, 155-158) is the side surfaces of the conductive strips in at least one of the vertical active strips and the upper plane of the conductive strips and the lower plane of the conductive strips. It is disposed in the interfacial regions at the intersections between, so that string select lines (SSL) and ground select lines (GSL) are formed. The gate dielectric (eg, 111g, 112g, 113g, 114g, 155-158) has a different composition than the charge storage structures. The string select lines SSL and the ground select lines GSL formed with the gate dielectric are not chargeable, and thus have fixed threshold voltages.

The gate dielectric may include a layer of silicon oxide material thinner than the charge storage structures. For example, the gate dielectric can have a thickness of about seven (7) nanometers, while the charge storage structures can have a thickness of about twenty (20) nanometers. The string select lines (SSL) and reference select switches formed with the gate dielectric are required to operate memory cells formed with charge storage structures (eg, from about 5V to about 5V). It can operate at a voltage lower than about 20V (eg, 3.3V).

The device may include silicide formations on the top plane of the conductive strips (eg, 191, 193, 195, 197) to reduce the resistance of the conductive strips in the top plane. The device includes spacers (e.g., 181, 183, 185, 187) separating the vertical active strips from the top plane of the conductive strips and silicide formations (e.g., 192, on top of the vertical active strips). 196).

The conductive strips in the stacks of the plurality of conductive strips may be arranged in a Y direction orthogonal to the X-Z plane, and are connected to decoding circuitry in the memory device. A reference conductor (not shown) can be disposed within a level between the lower plane of the conductive strips and the integrated circuit board, and is connected to the plurality of vertically active strips. The reference conductor may include an N+ doped semiconductor material. The memory device may include an overlying patterned conductive layer (not shown) including a plurality of global bit lines connected to the plurality of vertical active strips and connected to sensing circuits.

1A is a cross-sectional view of a 3D memory device in accordance with an alternative embodiment of the present invention. The difference in an alternative embodiment is that a gate dielectric is between the vertical active strips in the plurality of vertical active strips and the side surfaces of the conductive strips in the top plane of the conductive strips (eg 155-158). It is only disposed within the interface regions at the intersections of. Charge storage structures (eg, 111m, 112m, 113m, 114m) are intersections between the vertical active strips in the plurality of vertical active strips and side surfaces of the conductive strips in the lower plane of the conductive strips. In the interfacial regions.

1B is a cross-sectional view of a 3D memory device according to another alternative embodiment of the present invention. One difference in other alternative embodiments is that a gate dielectric (eg, 111g, 112g, 113g, 114g) is the vertical active strips in the plurality of vertical active strips and the conductivity in the lower plane of the conductive strips. It is only disposed within the interfacial regions at the intersections between the side surfaces of the strips. Charge storage structures (eg, 151m, 152m, 153m, 154m) are the intersection between the vertical active strips in the plurality of vertical active strips and side surfaces of the conductive strips in the upper plane of the conductive strips. In the interfacial regions. Another difference in another alternative embodiment is that silicide formations (eg, 192, 196) are formed only on top of the vertical active strips (eg, 161, 162), and the charge storage structures (E.g., 151m, 152m, 153m, 154m), while in the embodiments illustrated in FIGS. 1 and 1A, silicide formations (e.g., 191, 193, 195, 197) are poly It is also formed on the upper plane (SSL) of the conductive strips (for example, 151-154) that may include silicon.

2 is a simplified block diagram of an integrated circuit according to an embodiment of the present invention. In the embodiment shown in Figure 2, the integrated circuit 200, as described herein, at least of the upper plane (SSL) of the conductive strips and the lower plane (GSL) of the conductive strips on the integrated circuit board. It includes a vertical channel memory array 260 implemented with a gate dielectric on top of one. The gate dielectric has a different composition from the charge storage structures implemented on the conductive strip in the plurality of intermediate planes WL.

A row decoder 261 is connected to a plurality of word lines 262 and is disposed along rows in the memory array 260. A column decoder 263 is connected to a plurality of bit lines 264 (or string selection lines SSL as described above), and reads data from the memory cells in the memory array 260. It is arranged along the columns in the memory array 260 for programming. A plane decoder 258 is connected to a plurality of planes in the memory array 260 on string select lines (SSL) 259 (or bit lines as described above). The addresses are provided on the bus 265 to a column decoder 263, a row decoder 261 and a plane decoder 258. The sense amplifiers and data input structures in block 266 are connected to the column decoder 263 via a data bus 267 in this embodiment. Data is entered into the data input structures in block 266 from input/output ports on the integrated circuit 275 via the data input line 271 or from other data sources inside or outside the integrated circuit 275. Is provided on. In the illustrated embodiment, other circuitry 274 may be included on the integrated circuit, such as a general purpose processor or dedicated application circuitry, or a combination of modules that provide system-on-chip functionality maintained by a programmable resistor cell array. Can be. Data is passed through the data output line 272 from the sense amplifiers in block 266 to input/output ports on the integrated circuit 275 or other data destinations inside or outside the integrated circuit 275. Is provided as.

Using a bias aligned state machine 269, a controller implemented in this embodiment regulates the application of a bias array voltage generated or provided through the voltage supply or supplies within block 268, such as read and program voltages. The controller can be implemented using a dedicated logic circuit known in the art. In alternative embodiments, the controller can include a general purpose processor that can be implemented on the same integrated circuit, which runs a computer program that controls the operation of the device. In still other embodiments, a combination of dedicated logic circuitry and a general purpose processor can be utilized for the implementation of the controller.

3 is a flow diagram illustrating a method for manufacturing a vertical channel structure. The method begins with forming a plurality of sacrificial layers separated by insulating layers on an integrated circuit substrate, and at least one of an upper conductive layer and a lower conductive layer (step 310). The sacrificial layers and conductive layers are etched to form first openings (step 320). A gate dielectric layer is formed on at least one side surface of the upper conductive layer and the lower conductive layer in the first openings (step 330). A plurality of vertical active strips are formed in the first openings in which the vertical active strips in the plurality of vertical active strips contact the gate dielectric layer (step 340).

The sacrificial layers and conductive layers are then etched to form second openings between adjacent vertical active strips in the plurality of vertical active strips, whereby the plurality of sacrificial layers are exposed, and thus the upper conductive At least one of a top plane of conductive strips and a bottom plane of conductive strips is formed in at least one of the layer and the bottom conductive layer (step 350). The plurality of sacrificial layers exposed by the second openings are removed to form horizontal openings between the insulating layers (step 360). A memory layer is formed on the side surfaces of the vertical active strips in the horizontal openings (step 370). The planes of the plurality of conductive strips are formed in the horizontal openings. Side surfaces of the conductive strips in the plurality of planes are in contact with the memory layer (step 380). The plurality of planes include intermediate planes WL of the plurality of conductive strips. The planes of the plurality of planes are of the upper plane (SSL) of the conductive strips contacting the memory layer as shown in FIG. 1B and the lower plane (GSL) of the conductive strips contacting the memory layer as shown in FIG. 1A. It can contain one. An insulating material is then formed in the second openings.

The gate dielectric layer has a different composition from the memory layer. The gate dielectric layer may include silicon oxide. The memory layer is, for example, ONO (oxide-nitride-oxide), ONONO (oxide-nitride-oxide-nitride-oxide), SONOS (silicon-oxide-nitride-oxide-silicon), BE-SONOS (bandgap) Modified silicon-oxide-nitride-oxide-silicon), TANOS (tantalum nitride, aluminum oxide, silicon nitride, silicon oxide, silicon), and MA BESONOS (metal-high permittivity bandgap controlled silicon-oxide-nitride-oxide -Silicon), and may include a multilayer dielectric charge storage structure known from flash memory technologies including known flash memory technologies.

The gate dielectric may include a layer of silicon oxide material thinner than the memory layer. For example, the gate dielectric layer may have a thickness of about seven (7) nanometers, while the memory layer may have a thickness of about twenty (20) nanometers.

Spacers may be formed on the sides of the vertical active strips to separate the vertical active strips from the upper plane of the conductive strips. Silicide formations may be formed on top of the vertical active strips. Silicide formations can be formed on the top plane of the conductive strips, for example, during the same process where the silicide formations are formed on a substantial portion of the vertical active strips.

In one embodiment, both the upper plane of the conductive strips and the lower plane of the conductive strips can have side surfaces contacting the gate dielectric layer. In another embodiment, the upper plane of the conductive strips can have side surfaces contacting the gate dielectric layer, while the lower plane of the conductive strips can have side surfaces contacting the memory layer. In another embodiment, the upper plane of the conductive strips can have side surfaces contacting the memory layer, while the lower plane of the conductive strips can have side surfaces contacting the gate dielectric layer.

The method may further include forming the reference conductor within a level between the plurality of sacrificial layers and the conductive layers and the integrated circuit board where a reference conductor is connected to the plurality of vertical active strips. The reference conductor may include an N+ doped semiconductor material.

4-15 illustrate the process flow of an embodiment for manufacturing a memory device. 4 illustrates a cross section in the X-Z plane of a partially fabricated memory device. In the embodiment illustrated in FIG. 4, the memory device selects a plurality of sacrificial layers (eg, 420, 430, and 440) and strings to form word lines WL on the integrated circuit board. And an upper conductive layer (eg, 450) for forming the lines SSL, and a lower conductive layer (eg, 410) for the ground selection line GSL. The sacrificial layers and conductive layers are separated by insulating layers (eg, 405, 415, 425, 435, 445, 455). The plurality of sacrificial layers may include silicon nitride. The upper conductive layer (eg, 450) and the lower conductive layer (eg, 410) may include N+ polysilicon.

A hard mask (eg, 460) is disposed on the sacrificial layers and conductive layers to pattern the sacrificial layers and conductive layers. The hard mask may include polysilicon, which has a higher selectivity than the silicon oxide material used for the sacrificial layers and the oxide material used for the insulating layers.

5 illustrates a step in the process after etching the sacrificial layers and conductive layers using the hard mask to form first openings (eg, 510, 520). For example, the sacrificial layers and the conductive layers may be etched by reactive ion etching (RIE). The first openings are etched through the plurality of sacrificial layers (eg, 420, 430, and 440), the upper conductive layer 450, and the lower conductive layer 410. The first openings are used to form a plurality of vertical active strips.

6 is on the side surfaces (eg, 655, 656, 657, 658) of the top conductive layer in the first openings (eg, 510, 520) and side surfaces of the bottom conductive layer The steps in the process are illustrated after forming a gate dielectric layer (eg, 615, 616, 617, 618). The gate dielectric layer may include a layer of silicon oxide material. The gate dielectric layer has a thickness of about seven (7) nanometers. The layer of silicon oxide material may be formed by thermal oxidation on the upper conductive layer (eg, 450) and the lower conductive layer (eg, 410) in a temperature range of 800°C-900°C. As a result of thermal oxidation, a layer of the silicon oxide material (eg, 661, 663, 665) is also formed on the hard mask (eg, 460). The layer of silicon oxide material is not formed on the plurality of sacrificial layers (eg, 420, 430, 440).

7 illustrates the steps in the process after forming a plurality of vertical active strips (eg, 761, 762) in the first openings. The vertical active strips are on the side surfaces of the upper conductive layer (e.g., 655, 656, 657, 658) and the side surfaces of the lower conductive layer (e.g. 615, 616, 617, 618) It is in contact with the gate dielectric layer formed on it. The plurality of vertical active strips may extend to the reference conductor layer (not shown) below the sacrificial layers and the conductive layers. The hard mask (eg, 460) is planarized using, for example, chemical-mechanical planarization (CMP) suspended in an insulating layer (eg, 455) under the hard mask.

FIG. 8 illustrates the sacrificial layers and conductive layers to form second openings (eg, 810) between adjacent vertical active strips (eg, 761, 762) in the plurality of vertical active strips. After etching, the steps in the process are illustrated. The plurality of sacrificial layers (eg, 420, 430, 440) are exposed by the second openings. An upper plane of the conductive strips (eg, 451-454) and a lower plane of the conductive strips (eg, 411-414) are formed, wherein conductive strips in the upper plane and the lower plane are the Gate dielectric layers (eg, 655-658, 615-618). The conductive strips in the upper plane and the lower plane are in the Y direction orthogonal to the X-Z plane.

9 shows horizontal openings (eg, between the insulating layers (eg, 415, 425, 435, 445)) A step in the process is illustrated after removing the plurality of sacrificial layers exposed by the second openings to form 905). In the process, this step involves horizontal openings (eg, 905) leaving the insulating layers attached to the vertical active strips (eg, 761, 762). The horizontal openings 905 can be used to form word lines WL. The plurality of sacrificial layers may be removed by an etching process using phosphoric acid (H ₃ PO ₄ ) as an etchant. Phosphoric acid (H ₃ PO ₄ ) is used for the silicon nitride material used for the sacrificial layers, for the oxide material used for the insulating layers, and for the N+ polysilicon material used for the upper and lower conductive layers. Has a high selection ratio.

FIG. 10 forms a memory layer (eg, 441m, 442m, 443m, 444m) on side surfaces of the vertical active strips in the horizontal openings, after which the second openings (eg, 810 ) Illustrates a step in the process after depositing a conductive material (eg, 1001) on the memory layer. The conductive material may include titanium nitride (TiN) and tungsten (W). Excess conductive material may remain on the walls of the second openings.

11 illustrates the steps in the process after removing the excess conductive material remaining on the walls of the second openings, for example using isotropic etching. This removal leaves the conductive material only within the horizontal openings. At this stage of the process, a plurality of conductive strips are formed in the horizontal openings. The plurality of planes includes intermediate planes WL of a plurality of conductive strips (eg, 421-424, 431-434, 441-444), wherein side surfaces of the conductive strips in the intermediate planes are the Memory layer. The conductive strips in the plurality of planes are in the Y direction orthogonal to the X-Z plane.

12 illustrates steps in the process after forming an insulating material (eg 1270) in the first openings (eg 810) and over the top insulating layer (eg 455). .

13 shows insulating materials (eg 1270, 455) on the top plane of the conductive strips (eg 451-454) and the top of the vertical active strips (eg 761, 762). The steps in the process are exemplified after etching to stop on the phase. At this stage of the process, stacks of a plurality of conductive strips are formed. Each stack of conductive strips is a bottom plane (GSL) of conductive strips (eg, 411, 412, 413, 414), the middle of a plurality of conductive strips (eg, 441, 442, 443, 444) Planes WL and upper planes SSL of conductive strips (eg, 451, 452, 453, 454). The gate dielectric (eg, 615-618, 655-658) is a side surface of the vertically active strips in the plurality of vertically active strips and the upper plane of the conductive strips and the conductive strips in the lower plane of the conductive strips It is formed in the interfacial regions at the intersections between the fields.

14 shows spacers (eg, 1481, 1483, 1485) to separate the vertical active strips (eg, 761, 762) from the top plane of the conductive strips (eg, 451-454). , 1587). The spacers can be thin dielectric liners and include oxide or silicon nitride materials.

15 forms silicide formations (eg, 1591, 1593, 1595, 1597) on the top plane of the conductive strips (eg 451-454) and/or silicide formations (eg , 1592, 1596 are formed on top of the vertical active strips (eg, 761, 762) to illustrate the steps in the process. The silicide formations may include titanium (Ti), cobalt (Co), and nickel (Ni). The manufacturing process continues to complete the three-dimensional memory array.

16-27 illustrate a process flow of an alternative embodiment for manufacturing a memory device. The exemplary process flow shown in FIGS. 4-15 is between the vertical active strips in the plurality of vertical active strips and the top surfaces of the conductive strips and side surfaces of the conductive strips in the lower plane of the conductive strips. A memory device comprising a gate dielectric is formed in the interface regions at the intersection points. In comparison, an example of the optional process flow shown in FIGS. 16-27 is the intersection between the vertical active strips in the plurality of vertical active strips and the side surfaces of only the conductive strips in the upper plane of the conductive strips. Form a memory device including a gate dielectric in interface regions. In the example of the exemplary process and the optional process flow, the same elements are commonly referred to by the same reference numerals.

16 illustrates a cross section in the X-Z plane of a partially fabricated memory device. In the embodiment shown in FIG. 16, the memory device includes a plurality of sacrificial layers (eg, 420, 430, and 440) and ground selection for forming word lines WL on the integrated circuit board. And a sacrificial layer (eg, 410a) for forming the lines GSL. The sacrificial layers and conductive layers are separated by insulating layers (eg, 405, 415, 425, 435, 445, 455). The sacrificial layer for the word lines WL and the sacrificial layer for the ground selection lines GSL may include silicon nitride. The hard mask (eg, 460) and the upper conductive layer (eg, 450) are as described with reference to FIG. 4.

17 illustrates the steps in the process after etching the sacrificial layer and the conductive layer to form first openings (eg, 510, 520). The first openings are the top conductive layer 450, a plurality of sacrificial layers for the word lines WL (eg, 420, 430 and 440) and the sacrificial for the ground selection lines GSL. It is etched through the layer (eg, 410a). The first openings are used to form a plurality of vertical active strips.

FIG. 18 is in the process after forming a gate dielectric layer on the side surfaces (eg, 655, 656, 657, 658) of the upper conductive layer in the first openings (eg, 510, 520) To illustrate the steps. The gate dielectric layer and the formation of the gate dielectric layer using thermal oxidation are as described in FIG. 6. The thermal oxidation does not form a layer of silicon oxide material on the sacrificial layer (eg, 410a) for the ground selection lines GSL.

19 illustrates a step in the process after forming a plurality of vertical active strips (eg, 761, 762) in the first openings. The vertical active strips are in contact with the gate dielectric layer formed on side surfaces (eg, 655, 656, 657, 658) of the upper conductive layer. The hard mask (eg, 460) is planarized as described in FIG. 7.

20 illustrates the sacrificial layers and conductive layers to form second openings (eg, 810) between adjacent vertically active strips (eg, 761, 762) in the plurality of vertically active strips. After etching, the steps in the process are illustrated. The plurality of sacrificial layers (eg, 420, 430, and 440) for the word lines WL and the sacrificial layer (eg, 410a) bent over the ground selection lines GSL include the second openings. Is exposed by. An upper plane of conductive strips (eg, 451-454) is formed, where the conductive strips in the upper plane contact the gate dielectric layer (eg, 655-658).

21 shows horizontal openings (eg, between the insulating layers (eg, 405, 415, 425, 435, 445)) A step in the process is illustrated after removing the plurality of sacrificial layers exposed by the second openings to form 905). This step in the process involves horizontal openings in between (eg, Leaving insulating layers attached to the vertical active strips (eg, 761, 762) having 905, 906). The horizontal openings 905 may be used to form word lines WL, and the openings 906 may be used to form ground selection lines GSL.

22 is the vertical active strip in the horizontal openings for word lines (eg 441m, 442m, 443m, 444m) and for ground select lines (eg 411m, 412m, 413m, 414m). Forming a buried layer on the side surfaces of the, and through the second openings (eg, 810) the horizontal openings (eg, Steps in the process are illustrated after depositing a conductive material (eg, 1001) in 905, 906. The conductive material may include titanium nitride (TiN) and tungsten (W). Excess conductive material may remain on the walls of the second openings.

Figure 23 illustrates the steps in the process after removing the excess conductive material remaining on the walls of the second openings, for example using anisotropic etching. The removal leaves the conductive material only within the horizontal openings. At this stage in the process, planes of a plurality of conductive strips are formed in the horizontal openings. The plurality of planes are the middle planes WL of the plurality of conductive strips (eg, 421-424, 431-434, 441-444) and the bottom plane of the conductive strips (eg, 411a-414a) (GSL). Side surfaces of the conductive strips in the intermediate planes and in the lower planes contact the memory layer (eg, 441m-444m, 411m-414m).

24 illustrates steps in the process after forming an insulating material (eg 1270) in the second openings (eg 810) and over the top insulating layer (eg 455). .

25 shows the insulating materials (eg, 1270) to stop on the top plane of the conductive strips (eg, 451-454) and on top of the vertical active strips (eg, 761, 762). , 455) after etch. At this stage in the process, a plurality of stacks of conductive strips are formed. Each stack of conductive wire strips includes a bottom plane (GSL) of conductive strips (eg, 411a, 412a, 413a, 414a), a plurality of conductive strips (eg, 441, 442, 443, 444) And the upper plane SSL of the conductive strips (eg, 451, 452, 453, 454). A gate dielectric (eg, 655-658) is formed in interface regions at intersections between the vertical active strips and the side surfaces of the conductive strips in the top plane of the conductive strips. The memory layer comprising charge storage structures (eg, 411m, 412m 413m, 414m) is interfacial regions at intersections between the vertical active strips and side surfaces of the conductive strips in the bottom plane of the conductive strips. Is formed within.

26 shows spacers (eg, 1481, 1483, 1485) to separate the vertical active strips (eg, 761, 762) from the top plane of the conductive strips (eg, 451-454). , 1587). The spacers may be thin dielectric liners, and may include oxide or silicon nitride materials.

FIG. 27 forms silicide formations (eg, 1591, 1593, 1595, 1597) on the top plane of the conductive strips (eg, 451-454) and/or the vertical active strips (eg For example, steps in the process are illustrated after forming silicide formations (eg, 1592, 1596) on top of 761, 762. The silicide formations may include titanium (Ti), cobalt (Co), and nickel (Ni). The manufacturing process continues to complete the three-dimensional memory array.

Although the present invention has been described with reference to preferred embodiments and examples as described above, it will be understood that these embodiments are intended to be illustrative rather than limiting. It should be considered that the modifications and combinations can be easily made to those skilled in the art, and the modifications and combinations can be performed within the scope of the present invention and the scope of the following claims. .

105, 115, 125, 135, 145, 155, 170: insulating material
111-114: Conductive strip
121-124, 131-134, 141-144: Conductive strip
151-154: Conductive strip 161, 162: Vertical active strip
141m, 142m, 143m, 144m: charge storage structure
111g, 112g, 113g, 114g, 155-158: gate dielectric
155-158: Conductive strip 181, 183, 185, 187: Spacer
191, 193, 195, 197: conductive strip 192, 196: silicide formation
111m, 112m, 113m, 114m: charge storage structure
151m, 152m, 153m, 154m: charge storage structure
200: integrated circuit 258: plane decoder
259: String selection line 260: Memory array
261: Low decoder 263: Column decoder
264: Bit line 265: Bus
266: Block 267: Data bus
269: Bias sorting state machine 271: Data input line
272: Data output line 274: Other circuit parts
275: Integrated circuit
405, 415, 425, 435, 445, 455: insulating layer 410: lower conductive layer
410a: victims
411, 412, 413, 414: Conductive strip
411a, 412a, 413a, 414a: Conductive strip
411m-414m, 41m-444m: Memory floor 420, 430, 440: victim
421-424, 431-434, 441-444: Conductive strip
450: Upper conductive layer 451-454: Conductive strip
460: Hard mask 510, 520: First opening
615-618, 655-658: Gate dielectric
661, 663, 665: layer of silicon oxide material
761, 762: Vertical active strip 810: Second opening
905, 906: Horizontal opening 1001: Conductive material
1270: insulating material
1481, 1483, 1485, 1587: Spacer
1591, 1593, 1595, 1597: silicide formation
1592, 1596: silicide formation SSL: string selection line
GSL: Ground selection line WL: Word line

Claims (15)

A memory device comprising an array of strings of memory cells, comprising:
Stacks of conductive strips separated by an insulating material and having at least a lower plane of conductive strips, a middle plane of the plurality of conductive strips and an upper plane of the conductive strips;
A plurality of vertical active strips between the stacks;
Charge storage structures in interface regions at intersections between side surfaces of the conductive strips in the plurality of intermediate planes in the stacks and the vertical active strips in the plurality of vertical active strips; And
Between the side surfaces of the conductive strips in at least one of the top planar surfaces of the conductive strips and the upper plane of the conductive strips and the lower planar surfaces of the conductive strips, having a composition different from the charge storage structures. At the intersections, including the gate dielectric in the interfacial regions,
And the conductive strips in at least one of the upper plane of the conductive strips and the lower plane of the conductive strips comprise a different material than the conductive strips in the plurality of intermediate planes. The memory device of claim 1, comprising silicide formations on the top plane of the conductive strips. The memory device of claim 1, comprising spacers separating the vertical active strips from the top plane of the conductive strips and silicide formations on top of the vertical active strips. The memory device of claim 1, wherein the gate dielectric comprises a layer of silicon oxide material thinner than the charge storage structures. The memory device of claim 1, wherein a reference conductor is disposed in a level between the lower plane of the conductive strips and the integrated circuit board, and is connected to the plurality of vertical active strips. . 6. The memory device of claim 5, wherein the reference conductor comprises an N+ doped semiconductor material. A method for manufacturing a memory device,
Forming a plurality of sacrificial layers separated by insulating layers and an upper conductive layer and a lower conductive layer on the integrated circuit board;
Etching the sacrificial layers and the conductive layers to form first openings;
Forming a gate dielectric layer on side surfaces of the upper conductive layer and the lower conductive layer in the first openings;
Forming the plurality of vertical active strips in the first openings such that the vertical active strips in the plurality of vertical active strips contact the gate dielectric layer;
The sacrificial layers and the conductive layers are etched to form second openings between adjacent vertical active strips in the plurality of vertical active strips, thereby exposing the plurality of sacrificial layers, and thus the upper conductive Forming an upper plane of conductive strips and a lower plane of conductive strips in the layer and the lower conductive layer;
Removing the plurality of sacrificial layers exposed by the second openings to form horizontal openings between the insulating layers;
Forming a memory layer on side surfaces of the vertical active strips in the horizontal openings; And
Forming a plurality of intermediate planes of conductive strips in the horizontal openings, side surfaces of the conductive strips in the plurality of intermediate planes contacting the memory layer,
The gate dielectric layer has a different composition from the memory layer,
The memory device includes a plurality of stacks of conductive strips having at least a lower plane of the conductive strips, a plurality of intermediate planes of the conductive strips, and an upper plane of the conductive strips,
Wherein the conductive strips in at least one of the upper plane of the conductive strips and the lower plane of the conductive strips comprise a different material than the conductive strips in the plurality of intermediate planes. The method of claim 7,
And forming an insulating material in the first openings. The method of claim 7,
Forming spacers separating the vertical active strips from the upper plane of the conductive strips; And
And forming silicide formations on top of the vertical active strips. The method of claim 7,
And forming silicide formations on the top plane of the conductive strips. 8. The method of claim 7, wherein the top plane of the conductive strips has side surfaces contacting the gate dielectric layer. 8. The method of claim 7, wherein the bottom plane of the conductive strips has side surfaces contacting the gate dielectric layer. 8. The method of claim 7, wherein the gate dielectric layer comprises a layer of silicon oxide material thinner than the memory layer. The method of claim 7 including forming a reference conductor within a level between the sacrificial layers and the conductive layers and the integrated circuit board, wherein the reference conductor is the plurality of vertically active strips. The method characterized in that connected to. 15. The method of claim 14, wherein the reference conductor comprises an N+ doped semiconductor material.

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