TW415015B - Method for fabricating shallow trench isolation - Google Patents

Abstract

There is disclosed a method for fabricating a shallow trench isolation indirectly by chemical mechanical polishing. After depositing the oxide material in the shallow trench, the shallow trench isolation having planar level is formed by etching back and the silicon nitride layer at the corner of the active area is exposed. A blanket mask layer is then deposited. After the mask layer is formed, a photoresist layer is formed to remove a portion of the mask layer in the wide active area. The photoresist layer is then stripped and chemical mechanical polishing is performed to remove the mask layer on the narrow active area. The oxide material on the active area is removed by wet etching, and the remained mask layer and the silicon nitride are then etched by wet etching. Finally, the pad oxide layer is removed, so as to complete the method for fabricating the shallow trench isolation indirectly by chemical mechanical polishing in accordance with the present invention.

Description

415013 A7 _ B7 V. Description of the invention () Field of the invention: The present invention relates to a method for manufacturing an integrated circuit, and in particular to an indirect chemical mechanical polishing (CMP) process used in the manufacture of ultra-large integrated circuits. CMP) forming a shallow trench process method. Background of the Invention: In today's semiconductor manufacturing processes, hundreds of thousands of semiconductor elements may be accumulated in a small unit area of 1-2 square centimeters. Today, as semiconductor elements are shrinking, in order to make the transistor and the transistor The operation between them will not be interfered by each other, and proper isolation is an important task. In order to avoid short circuits between components, the process is an isolation process. In the manufacture of many transistor hips, an isolation method called LOCOS uses thermal oxidation to grow thousands of angstroms of silicon dioxide between transistor elements and uses its non-conductivity to produce This insulating layer is also called a field oxide layer. When the semiconducting process is moving towards a higher accumulation level, in order to increase the desired accumulation level of the transistor, another trench iso la ti on technology that replaces LOCOS has also been widely used in the new generation process. . This method uses anisotropic etching to etch a trench, and then fills it with silicon dioxide and other materials to achieve isolation. A process called Shallow Trench Isolation (STI) is applicable to the paper size of China National Standard (CNS) A4 (210 X 297 mm) for line sizes below 0.5 // m. (Please read the note on the back first Please fill in this page again) IIIII · 1 [11-— 1— Printed by A7, Consumer Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs

415015 V. The component application of the invention description () is particularly suitable. Body circuit The active area on the ancestral circuit is usually different in size due to different circuit design and electrical design, and shallow trenches may have different widths. # 然 浅 沟沟 can help increase the integration of semi-conductor components, but it also complicates the transistor process. In the advanced semi-conductor process, complex multilayer circuit designs are often encountered, such as multiple interconnect processes (njuitiievei interconnects). Based on this consideration, when shallow trenches are formed, the deposition and planarization of insulating materials will be the key to good subsequent processes. Traditionally, there are also many techniques for the deposition and flattening of shallow trenches. In shallow trench deposition technology, chemical vapor deposition

Vapor Deposition (CVD) uses a chemical reaction between reactive gases to deposit a thin film ', which has much better material characteristics than the recording method, and is therefore a commonly used technique. The plasma enhanced CVD method (Plasma

Enhanced CVD (PECVD) can also perform varying degrees of ion bombardment on the deposited film, and by controlling the ion bombardment, the film stress can be adjusted 'and the wafer warpage or wafer caused by excessive stress can be reduced. The phenomenon of film peeling. As for the flattening process, there are, for example, Resist Etch Back (REB), Reactive Ion Etching (RIE), and Spin On Glass (Spin On).

Glass, SOG), and Chemical Mechanical Polishing

Pol i shi ng (CMP), etc., can produce different levels of flattening results on the deposited film. This paper size is applicable to China Gujia Standard < CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page) Pack-IΊ I!-Order · ------- -Printed by A7 B7 of the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Invention Description (> Traditional shallow trench isolation process usually uses the technology of chemical mechanical polishing, and chemical polishing is now the only comprehensive ultra-large integrated circuit that can provide A technique for planarization. After depositing insulating materials in shallow trenches, many people use this method to planarize it. For example, it is described in US Patent No. 5494857, named " CHEMICAL MECHANICAL PLANARIZATION OF SHALLOW TRENCHES IN SEMICONDUCTOR SUBSTRATES ", Made by SS Cooperman et al., That is to form shallow trench isolation after etching back insulating materials by chemical mechanical polishing technology. Another example is described in another US patent number 5312512, named " GLOBAL PLANARIZATION USING SOG AND CMPB, by Allman's use of spin-on-glass technology and chemical mechanical polishing to achieve a comprehensive integrated circuit The purpose of smoothing is to smooth. When polishing by chemical mechanical polishing method, multiple parameters will affect the polishing characteristics, such as the slurry characteristics, the pressure on the wafer, the material of the polishing pad, and the size of the particles. Distribution and so on. At the same time, many problems often occur in the CMP process, such as the difficulty of endpoint detection, microscratch on the polished surface, the flatness of the polishing and the pattern, the uneven polishing rate, and the wafer. Issues such as pollution control, etc. "Printed by the Shellfish Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs (please read the note on the back before filling in this page) Although CMP can achieve a comprehensive flattening effect, if shallow trenches rely only on CMP flattening will not only make the process more complicated, but also the above-mentioned problems will not be easily solved. The paper standards are applicable due to S standards < CNS) A4 specifications (210 X 297 public love) A7 B7 Ministry of Economic Affairs wisdom Printed by the Consumers' Cooperative of the Property Bureau V. Description of the invention () Purpose and summary of the invention: Shallow trench isolation (STI) has been widely used in the manufacture of very large integrated circuits (lJLSI). However, since the planarization of STI can help the subsequent semiconductor fabrication process, traditionally there are many methods that can planarize the insulating material deposited by STI. • Chemical mechanical polishing (CMP) dominates the planarization process of STI, but There will be many problems, such as micro-to-polished surface, uneven polishing, uneven polishing rate, etc., which also complicates the process of STI. Therefore, the object of the present invention is to provide an indirect method for the fabrication of ultra-large integrated circuits. Chemical mechanical research method to form shallow trench isolation. Another object of the present invention is to provide a shallow trench isolation method for comprehensive planarization in the integrated circuit manufacturing process. In order to achieve the above-mentioned object, the method provided by the present invention is: forming a hafnium oxide layer in a semiconductor substrate, and then depositing a silicon nitride layer on the padding layer. Then a photolithography and etching process is used to form a siliconized photoresist layer on the silicon nitride layer, and then the silicon nitride layer is etched to define a shallow trench isolation area. Then the nitrided layer is used as the substrate for the military curtain to etch the shallow trench area. 'After the shallow trench is formed, it is thermally oxidized, and then a high-density dielectric chemical vapor deposition (HDPCVD) method is used to form a thicker dielectric layer. The dielectric layer is generally a silicon dioxide layer (using 0, and the thin film formed by the high-density plasma cvd method is also more stable, and due to the inconsistency of the deposition caused by its ion bombardment, the deposition of the sidewall is more than that of a flat surface. w is much harder, so it is easy to deposit in shallow trenches of different widths and less prone to defects. 5 This paper size is applicable to the Chinese Standard for Household Standards (CNS) A4 (21〇x 297 mm) (Please read the back Please fill in this page for the matters needing attention) Packing ------- Ordering ------------ Printed by the Consumers' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 415015 A7 • -------- B7_ V. Description of the invention () After the shallow trench is deposited, the dielectric layer is renamed by wet etching. At this time, the dielectric layer in the shallow trench will be etched back to a more appropriate level, and the dielectric layer on the silicon nitride layer is etched back. The electrical layer is etched at the same time to expose the corners on both sides. This silicon nitride layer area is generally called the active area. Then, a comprehensive silicon nitride masking layer is deposited, and then lithography and etching are used. A patterned photoresist layer is formed in the process to expose the main In the active region, the patterned photoresist layer is easier to form because of the larger width of the active region. Then, the masking layer above the larger active region is removed to expose the oxide dielectric layer, and then the upper layer is exposed. The photoresist layer is removed. After the photoresist layer is removed, the uppermost part of the structure is polished by non-precision controlled chemical mechanical polishing. The purpose of this chemical mechanical polishing is not to equalize the shallow trench area, but it can be located in The cover layer on the smaller active area is removed to expose the underlying oxide dielectric layer. At the same time, this step is easier to control. Then, 'the remaining oxide layer is etched with a diluted H gas acid solution or BOE solution first'. Sex money engraving solution has a very low engraving rate on the nitride nitride layer, so the nitride nitride layer above the shallow trench and the nitride layer on the active area will not be affected. After the oxide layer is wet etched, Use a hot dish acid solution (H3P04) to etch the remaining silicon nitride layer a. As described above, the traditional chemical mechanical polishing method for flat shallow channel isolation is no longer needed. In the present invention, only Non-precision The chemical mechanical polishing method indirectly polishes the wafer structure, so due to the chemical mechanical polishing ------. 1_ 「V ---- 装 .1. I · * ϋ ^ OJI n) n Is 1] II-(Please (Please read the notes on the back before filling out this page) 6

415015

V. Explanation of the invention (the disadvantages caused by the process contacting the flattened surface will no longer exist ', and the non-precise chemical mechanical grinding process of the present invention to form the shallow trench isolation process will also be more suitable for mass production using the beta ring type. Simple explanation: economic The preferred embodiment of the present invention printed by the Ministry of Intellectual Property Bureau's Consumer Cooperatives will be explained in more detail in the following explanatory texts with the following figures, of which: -th is a cross-sectional view of the crystal enclosure according to the present invention Non-shallow trenches are formed in the wafer; the second figure is a cross-sectional view of the crystal perimeter according to the present invention, showing the process of thermally oxidizing the shallow trenches; the third ® is a 81-section view of the crystal according to the present invention '' shows HDP-CVD The process of depositing the dielectric layer: The fourth figure is a cross-sectional view of the crystal according to the present invention, showing the process of etch back the HDP dielectric layer; the fifth picture is the cross-sectional view of the crystal according to the present invention, showing the formation of a silicon nitride mask Layer process: The sixth circle is a cross-sectional view of a wafer according to the present invention, showing the easier process of photoresist® formation: The seventh circle is a crystal® cross-sectional field according to the present invention, showing nitrogen Covering silicon layer peeling process: This paper scales applicable Chinese national standard < CNS) A4 size (210 X 297 mm) (Please read the precautions angry at the back of the page and then fill in) installed Ί1 !! - Order! 1 line

415015 5. Description of the invention (8) Figure 8 is a cross-sectional view of a wafer according to the present invention, showing the process of stripping the patterned photoresist layer; Figure 9 is a cross-sectional view of a wafer according to the present invention, showing chemical mechanical polishing Grinding process: The tenth line is a view circle of a wafer cross section according to the present invention, and shows a process for removing a silicon oxide layer by a wet money engraving method. The eleventh circle is a cross section view of a wafer according to the present invention, showing The remaining nitrided dream layer full-etch process; and the twelfth circle is a cross-sectional view of a wafer according to the present invention, showing the process of removing the pad oxide layer. Detailed description of the invention: Traditionally, the area oxidation method (LOCOS) is used to isolate the transistor. The isolation process is used by most semiconductors. However, when the shipbuilding circuit is more integrated, the disadvantages of LOCOS are as black. The disadvantages of bird's peak formation, insufficient planarization, and film stress are even more intolerable. The shallow trench isolation (Shai low Trench I sal at i on) process formed in the wafer is very suitable for the sub-micron semi-conductor process. Because the dielectric layer in the trench is formed by a comprehensive deposition method, a thin film is deposited. It is necessary to planarize β later. In different drawings of the present invention, the same reference numerals represent the same materials. At the same time it should be noted that the proportions of the layers in the illustration are not completely in accordance with the 8 paper sizes. The Chinese National Standard (CNS) A4 specification (210x297 mm) is applied. -----, ---.---- ------- Order --------- Line 1 ("Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 41b〇i5 A7 B7 V. Description of the invention (The thickness ratio of the layers is drawn. In addition, because the process steps described include many well-known lithographic masks and etching processes, there are many steps that will not be described in detail here. See the first section This figure shows a shallow trench isolation region formed in a semiconductor substrate 100. Before this shallow trench isolation region is formed, a pad oxide layer 120 is formed by oxidation using a hot furnace tube. In one embodiment, this pad The thickness of the oxide layer 120 is about 50 to 300 angstroms. Next, a silicon nitride layer 11 is formed on the pad oxide layer I 2 0 by a suitable chemical vapor deposition (CVD) method such as plasma enhanced CVD (PECVD). 〇, and in one embodiment, the thickness of the silicon nitride layer II 0 is about 100 to 2000 Angstroms. After the formation of the pad oxide layer 120 and the silicon nitride layer 11 G, a patterned photoresist layer is formed on the stack layer by using a conventional lithographic leather screen and etching 裎 (not shown in 圊) Then, the patterned photoresist layer is used to etch the underlying silicon nitride layer 110. After stripping the photoresist layer, the etched silicon nitride layer 110 is used as an etching mask to etch down a shallow trench isolation area. In one embodiment, the depth of the shallow trench is between about 0.4 to 0.66 m. The shallow trench isolation area can be referred to as a non-active area, and the shallow trench isolation area is located between the shallow trench isolations. The area is the active area. Due to the different designs of the integrated circuit, the active area and the non-active area will have different widths. Refer to the second figure, which shows, for example, the thermal oxidation method in the Steps to form a linear oxide layer on the side wall and bottom of the shallow trench area. Then refer to the third paper size applicable to the Chinese National Standard (CNS) A4 (210 x 297 mm) (Please read the precautions on the back before filling this page)

_ Equipment -------- Order if H ϋ ϋ n IB I Printed by iL5015 in the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs; 5. Description of the invention () 圏, the silicon dioxide layer 130 is then a high-density plasma chemical gas Phase deposition (HDPCVD) is formed in shallow trenches in the non-active region and over the silicon nitride layer 110 in the active region. The HDPCVD method can use Siih, 02, and Ar and other reaction gases «to form an inductively coupled plasma source in the reaction chamber in order to form a higher density plasma. At the same time, the uniformity of the thin film deposited by this method is not uniform, and its deposition rate on the side wall is much slower than that on the plane. "If the width of the trench is different, the HDP film can fill the narrower trench. And its deposition thickness has nothing to do with the trench width. See FIG. 4 | After the dielectric material layer 130 of the trench is deposited, the dielectric layer 130 is etched back and forth using wet etching. Although the dry etching method has excellent anisotropic etching results, sometimes it cannot provide the required etching selectivity, and sometimes it will erode to other materials or cause varying degrees of pollution, so Wet etching can also be applied to some special processes, such as etching full-refolding polycrystalline silicon, dielectric layers, and metal layers. In the figure, the silicon dioxide layer film 130 can be etched by using a dilute argon fluoride (HF) solution or a BOE solution. The etch rate of this oxide layer is related to the concentration of the etchant, the degree of agitation, and the temperature. In addition, the density, microstructure, and purity of the film will naturally affect the etching rate. In the diluted HF solution, the etching rate of the nitride film is much slower than that of the oxide film. Therefore, when the silicon dioxide film 130 is etched back, the silicon nitride layer 110 on the active area is hardly affected. As shown in the fourth circle, the oxidizing material 130 in the trench will be etched. 10 The paper size is applicable to the national standard (CNS) A4 specification (210 X 297 cm). (Please read the intentions on the back first. (Fill in this page)

n 1 «Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, and printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, and printed by the Employee Consumer Cooperative, 415015 at ____ B7 V. Description of the invention () To a certain degree, and the oxide layer on the active area was The corners of the silicon nitride underlayer 110 are exposed by etching. This exposure step is a very important step in the present invention, because in the following procedure, the exposed corners will be combined with the masking layer deposited later to protect the trench and to deposit oxide materials thereon. Referring to the fifth figure, after the oxide layer 130 is etched back, a silicon nitride masking layer 140 is deposited on the HDP oxide layer material 130 and the silicon nitride layer 10 by an appropriate chemical vapor deposition method, and the deposition is performed. The thickness is between about 2000 and 2000 Angstroms. Since the silicon nitride layer is not easily penetrated by impurities or water vapor, it is very suitable as a protective layer. Refer to the sixth figure, which shows a schematic cross-sectional view of the deposition of a non-critical photoresist pattern layer formed in the above structure. The traditional photolithographic mask and # engraving process are used to form a second encapsulation photoresist layer go on the cover layer 140. In addition, the exposed area of the photoresist layer 150 is set on an active area that has a relatively large width, and the width of this active area is approximately larger than the left and right. In order to increase the reliability of subsequent processes, it is necessary to process the active area with a larger degree of strength first. At the same time, this step can also increase the convenience of the process. Referring to the seventh figure, this figure shows a schematic cross-sectional view of the peeling of the cover layer. Because the patterned photoresist layer 150 exposes the masking layer 'on the larger active area, this masking layer is first wet-etched and stripped. Since this masking layer is a vaporized dream layer, it can be used at room temperature at a high concentration. The HF solution or HsPCh solution is removed at a temperature of about 150 to 200 ° C. In this structure, this paper size is applicable to the National Standard for Difficulties (CNS) A4 (210 X 297 meals)-------1-^ L ------ ^ --- Kill I (Please Read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 415015 A7 ------- B7 V. Description of the invention () The bottom silicon oxide layer 1 3 0 is used as an etching stop layer . Referring to the eighth figure, this step is to peel off the patterned photoresist layer 150. It can also be seen from the figure that when the photoresist layer is peeled off, the silicon nitride layer 110 above the larger active area will cover the cover layer. 140 is combined to protect the filled oxide material in the shallow trench. Referring to FIG. 9 ', after the photoresist layer 150 is removed, a chemical mechanical polishing process is performed. In this grinding process, since the masking layer 140 on the larger active area has been removed by depositing the non-precision photoresist pattern described above, the silicon oxide layer 130 is exposed, but the oxidized stone layer 130 on the smaller active area is removed. It is still covered by the cover layer 140, so the purpose of the CMP is to remove the cover layer 140 on the smaller active area. It can also be seen from this description that this chemical mechanical polishing method is less precise and easier to implement, and it does not directly polish the silicon oxide layer in shallow trenches, so it can increase the reliability of the process. Refer to Tenth®, since the covering layer 140 on the larger active area and the smaller active area has been removed, the above-mentioned diluted argon fluoride acid solution or boe solution is used to remove the exposed oxide layer 130, and the remaining nitrogen The siliconized layer 140 will not be affected. Refer to the eleventh figure, which shows a schematic cross-sectional view after the step of stripping the silicon argon layer. After the oxide layer is removed, only the cover layer 140 and the nitride layer 110 remain on the top layer of the wafer. At this time, the H 3PO4 solution is heated to 150 to 20 (the temperature of TC is used to remove the silicon nitride material.) The paper size is applicable to the National Standard (CNS) A4 (210 X 297 mm) -II. —-In Packing * I --- ^ Order ---- !! Line < Please read the Weeping Matters on the back before filling out this page) 415015 V. Description of the invention () Refer to Figure 12 and finally remove An oxide layer is formed on the substrate 100 to form the non-precision chemical mechanical polishing process of the present invention to form a shallow trench isolation process. The shallow trench isolation process of the present invention uses HDPCVD to form a high-quality deposited film. At the same time, the chemical mechanical polishing in the process method of the present invention does not directly grind to the dielectric layer of the shallow trench, so it does not produce uneven polishing surfaces. Problems such as inconsistent etching rates and the non-precision photoresist pattern formation and non-precision chemical mechanical polishing in the present invention will make the process steps easier to perform, and therefore will have more reliability for mass production processes. As will be understood by those familiar with this technology, the above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the patent application for the present invention; all others completed without departing from the spirit disclosed by the present invention, etc. Effective changes or modifications should be included in the scope of patent application described below. ^ — — — —-* —R IIIIII i — — — — — — — — i Please read the notes on the back before filling out this page} Printed on paper scales applied by Chinese Consumers ’Cooperative Standards (CNS) A4 specification (210 * 297 mm)

Claims (1)

415015 Bismuth C8 D8 7. Scope of patent application Patent scope: 1. A shallow trench isolation manufacturing method, which at least includes: depositing a first dielectric layer on a semiconductor substrate; depositing a second dielectric layer on the first dielectric Above the electrical layer; the second dielectric layer is engraved to form an active region and an inactive region, wherein the active region includes at least a wide active region and a narrow active region with different widths, and the semiconductor substrate is etched A shallow trench is formed in the non-active area, wherein the second dielectric layer is used as an etching mask: a third dielectric layer is deposited on the shallow trench and the second dielectric layer; the third dielectric layer is etched and A corner portion of the second dielectric layer is exposed; a fourth dielectric layer is deposited on the third dielectric layer and the second dielectric layer; and a portion of the fourth dielectric layer located in the wide movable region is etched Among them, a patterned photoresist layer is used as an etching mask: printed by the Central Ministry of Economic Affairs, the Mogai Consumer Cooperative Co., Ltd. 0 Please read the precautions on the back before filling this page) Grinding the fourth dielectric layer is located in the Part of narrow active area To expose the third dielectric layer; to etch the third dielectric layer located on the active area; to etch the fourth dielectric layer and the second dielectric layer: (CNS) A4 specification (210X297 mm) 415015 A8 B8 C8 D8 々 The scope of patent application engraved the first dielectric layer. (Please read the precautions on the reverse side before filling out this page) 2. If the method of the first scope of the patent application, the first dielectric layer mentioned above is the dream dioxide layer (Si〇2) »3. If the scope of the patent application The method of item 1, wherein the second dielectric layer is a silicon nitride layer (Si3fh). 4. The method according to item 1 of the patent application, wherein the third dielectric layer is a silicon dioxide layer. 5. The method according to item 1 of the patent application, wherein the fourth dielectric layer is a silicon nitride layer. 6. The method according to the first item of the patent application, wherein the step of depositing the third dielectric layer described above uses a high-density plasma chemical vapor deposition method (HDP-CVD). Printed by the Central Government Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives 7. For the method of applying for the scope of the first item of the patent scope, where the width of the above-mentioned wide active area is greater than about 1 inch D3 ° 8. For the method of the scope of the first scope of the patent application The above-mentioned etching is located on the paper scale, using the Chinese National Standard (CNS) A4 grid (2Η5 × 297 mm) 415015 A8 B8 C8 D8 The third dielectric layer step on the active area of the patent application is a liquid solution Wet etching > Solvent 9 with diluted argon fluoride (HF) as described in item 1 of the scope of the patent application, wherein the above steps of etching the fourth dielectric layer and the second dielectric layer are used IbPih solution was added. The method of wet etching of the Ministry of Economic Affairs of the Central Bureau of Standards and Labor «Printing of cooperatives 10. For example, the method of applying for patent U 9 item, in which the above-mentioned wet type engraving is at a temperature of about 150 to 2 0 r Executive. η. As mentioned in the method 1 of the project, the depth of the upper ditch canal is about 0.4 m to 0.6 # m. 12. As the method of the scope of patent application for item 1, the above grinding The step system uses a chemical mechanical polishing (CMP) method. 13. —A method for manufacturing a shallow trench isolation of an integrated circuit, the method at least comprises: depositing a pad oxide layer on a semiconductor substrate; depositing a silicon nitride layer on the pad oxide layer; etching the nitrided sand layer to form an active layer Active region and non-active region ', where the active region contains at least a wide active region and a narrow main region of different widths. This paper size is in accordance with China National Standards (CNS) A4 (210X297 mm) ^ 1-- --- Order-. (Please read the note on the back of the page before filling in this page) 415015 戠 C8 _____D8 VI. Application for patent range of moving area; Etching the non-active area of the semiconductor substrate to form a shallow trench, which uses the A silicon nitride layer is used as an etching mask; an insulating oxide layer is deposited on the shallow trench and the gasification dream layer, the insulating oxide layer is etched and a corner portion of the nitrided layer is exposed; a cover layer is deposited on the insulation An oxide layer and the silicon nitride layer; etching a portion of the masking layer located in the wide active region, wherein a patterned photoresist layer is used; grinding a portion of the masking layer located in the narrow active region to expose the insulating oxygen Layer; etching the insulating oxide layer located over the active region; etching the silicon nitride layer and the masking layer: and etching the pad oxide layer. 14. For the method of applying for the scope of patent No. 13, wherein the above-mentioned padding layer is an oxide layer of oxide (SiOO. 15. For the method of applying for the scope of patent No. 13, wherein the above-mentioned covering layer is the Central Government Bureau of the Ministry of Economic Affairs Printed by Bei Gong Consumer Cooperative (Please read the precautions on the back before filling this page) Silicon nitride layer (SiaNO. 16 ') The method of item 13 in the scope of patent application, in which the above step of depositing the insulating oxide layer The word system uses high-density plasma chemical vapor deposition method (HDp_ This paper standard uses the Chinese National Standard (CNS) 8 4 grid (21〇 ^ 97 ^) '' '------ Λ8 fig C8 D8 415015 ----- VI. Patent Application Range CVD) 17. If the method of applying for the scope of patent No. 13, the width of the above-mentioned wide active area is greater than the above. 18. If the method of applying for the scope of patent No. 13, where the above The step of etching the insulating oxide layer on the active region is performed by wet etching using a dilute argon acid (HF) solution. 19. The method according to item 13 of the patent application, wherein the covering layer and the mask are etched as described above. The step of gasifying the dream layer uses H3P〇4 Wet etching with liquid. 20. The method according to item 19 of the patent application range, wherein the above-mentioned wet etching is performed at a temperature of about 150 to 200 ° C. I ~ ill 丨 |! 装 ·-^ —! — ^ I.-Please read the notes on the back before filling in this page) Yin Yang Liang Mou Bureau, Ministry of Economic Affairs