TW305071B - The MOSFET in electro-static discharge protecting circuit - Google Patents

The MOSFET in electro-static discharge protecting circuit Download PDF

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TW305071B
TW305071B TW085109874A TW85109874A TW305071B TW 305071 B TW305071 B TW 305071B TW 085109874 A TW085109874 A TW 085109874A TW 85109874 A TW85109874 A TW 85109874A TW 305071 B TW305071 B TW 305071B
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gate
drain
diffusion region
diffusion
silicon substrate
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TW085109874A
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Shyi-Tsong Lin
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Winbond Electronics Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843Source or drain regions of field-effect devices
    • H01L29/0847Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642Isolation within the component, i.e. internal isolation
    • H01L29/0649Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692Surface layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

3 Ο 5 f. doc/002 A7 經濟部中央標準局員工消費合作社印製 B7 五、發明説明(I ) 本發明是有關於靜電放電(Electro-Static Discharge ; ESD)保護電路中的金氧半場效電晶體架構, 且特別是有關於一種靜電放電保護電路中,具有部份分割 擴散區(Partially Segmented Diffusions)之金氧半場效 電晶體的架構。 η型金氧半電晶體元件,不論是閘極接地式η型金氧半 電晶體(Gate Grounded NM0S)或是閘極藕接式η型金氧半 電晶體(Gate Coupled NMOS) ’在積體電路中已常被作爲 靜電放電保護電路中的主要元件。η型金氧半場效電晶體 的靜電放電保護能力,幾乎視高電壓跳回機制(Snap-back Mechanism)而定,此高電壓跳回機制係用以在汲極(Drain) 與源極(Source)之間傳導巨大的靜電放電電流。起初,在 汲極接面的高電場會造成撞擊離子化(Impact Ionization),而產生少數載子和多數載子(Minority and Majority Carriers)。此少數載子流向基底(Substrate) 或P井的接觸窗(Contact),而在P井區產生區域電位 (Local Potential)。當此區域基底電位比鄰接的n+源極 電位高出約0.6V時,源極接面就變成順偏(Forward BUs)。此順偏的源極接面會將少數載子注入P井中,最後 少數載子到達汲極接面又進一步增強撞擊離子化,如此連 續循環的結果,使金氧半場效電晶體進入一低阻抗(跳回) 狀態,以傳導巨大的靜電放電電流。 隨著從汲極流向源極接面的電流之增加,最後將產生 一電流壓縮(Cur ren t Cons t r i c t i on),使靜電放電電流延 3 (請先閲讀背面之注袁事項再填寫本頁) -裝· -a Μ 本紙張尺度.適用中國國家樣隼(('NS ) Λ4規格(210X2W公犛) 0509twf.doc/002 A7 B7 經濟部中央標隼局員工消f合作杜印製 五、發明説明(、) 著汲極/源極接面間的若干狹窄路徑,經由閘極下方流入 最弱點(Weakest spot)。狹窄壓縮路徑沿線的高電流密度 會引發熱和更多的載子產生,結果區域溫度昇高到矽或鋁 的熔點溫度,而對矽或接觸窗造成永久破害。我們最期望 的是靜電放電電流均勻地從汲極流向源極,並且延著整個 閘極邊緣平均分散。如果延著閘極邊緣有一弱點(Weak Spot)產生,例如氧化物間隙壁(Oxide Spacer)不均勻, 則汲極擴散區靠近弱點處將率先崩潰(Break down),結果 在靠近弱點處發生電流壓縮,因而導致元件損壞。 爲了使靜電放電電流均勻地流向源極,AlanLee等人 於專利號碼爲5,157,573之美國專利“ESD Protection Ci rcui t Wi t h Segmen t ed Buf f er Trans i s tor”中提出了 一 種佈局(Layout)方式,請同時參照第1圖與第2圖。其中, 圖1繪示的是靜電放電保護電路的佈局上視示意圖,而圖 2繪示的是對應於圖1的靜電放電保護電路之剖面示意 圖。金氧半電晶體10的源極擴散區12形成在一 p型井15 中,而汲極擴散區11則形成在p型井15與一 η型井16中。 汲極擴散區11與源極擴散區12分別包括複數個互相平行 的擴散區段lla-]ld與12a-12d,且源極側的每一擴散區 段12a-12d中至少包含有一接觸窗13a-13d。金氧半電晶 體1 0,閘極14分別與擴散區段11 a ; 11 b ; 11 c ; 11 d、 12a;12b;12c;12d 結構成一電晶體 10a;10b;10c;10d,也 就是說金氧半電晶體10類似被切割成數個並列的區塊金 氧半電晶體(MOSFET Segment)10a-10d。來自焊墊或VDD匯 4 (請先閲讀背面之注意事項再填寫本頁) .裝- 訂 」 本紙張反度適用中國國家標嗥(C’NS ) Λ4規格(210X297公釐) 0509twf.doc/002 A7 0509twf.doc/002 A7 經濟部中央標準局員工消費合作社印製 B7 五、發明説明(3 ) 流排18的靜電放電電流會經由汲極擴散區17與η型井16 流向汲極擴散區11,而由於互相平行的擴散區段lla-lld 與12a-12d之故,靜電放電電流會均勻地分別經由擴散區 段lla-lld、閘極14、擴散區段12a-12d與接觸窗13a-13d 流入VSS匯流排,使得靜電放電保護的能力增強。然而,卻 也有下列三項缺點: 1. 限制了每一區塊金氧半電晶體的寬度 由於接觸窗邊緣到擴散區邊緣(Contact-to-diffusion edge),例如圖 1 中之 di、d2、d3與 d4,均有 一定的距離限制,因此,每一區塊金氧半電晶體之寬度並 不能盡如人願的窄。於是,寬度的限制就限制了靜電放電 事件時金氧半電晶體所能承受的電位。 2. 減少了源極側的接觸窗數目 接觸窗邊緣到擴散區邊緣以及接觸窗邊緣到複晶矽層 邊緣通常均保持一固定的距離,例如圖1中之cl·、d2、d3 與d4,以避免接觸窗在高電流的靜電放電事件中受到傷 害。由於源極側的擴散區被分割成複數個擴散區段,故源 極側的接觸窗總數便較未區段分割源極擴散區者少,而接 觸窗數目愈少表示流過每一接觸窗的電流密度就愈高,這 對於抗靜電放電的能力而言,確是一項大缺失。 因此,本發明的主要目的就是在提供一種靜電放戆保 護電路中具有部份分割擴散區的金氧半場效電晶體, 使靜電放電電流均勻分流,且降低分流的電流密度。 根據本發明的一較佳實施例,一種靜電放電保護電& 5 (請先閱讀背面之注意事項再填寫本萸) 裝·
*1T 本紙張尺度適用中國國家橾準(CNS ) Λ4規格(210x 297公釐) 3 u G C ^^twf.d〇 c/002 A7 經濟部中央標準局員工消費合作杜印製 B7 五、發明説明(4 ) 中具有部份分割擴散區的金氧半場效電晶體架構包括:一 閘極,形成在一矽基底上;一井,形成在閘極一側邊的矽 基底中;一第一汲極擴散區,形成在井中;一第二汲極擴 散區,形成在矽基底與井中;一源極擴散區,形成在閘極 另一側邊的矽基底中;一場氧化物層,形成在矽基底上, 其具有複數個手指,自汲極側延伸穿過閘極下方至源極 側,使得第二汲極擴散區被分割成複數個平行排列的陣列 狀擴散區塊,而源極擴散區仍爲一完整區塊。 根據本發明的另一較佳實施例,一種靜電放電保護電 路中具有部份分割擴散區的金氧半場效電晶體架構包 括:一閘極,形成在一矽基底上;一汲極擴散區,形成在 閘極一側邊的矽基底中;一源極擴散區,形成在閘極另一 側邊的矽基底中;一陣列狀場氧化物島,形成在矽基底上, 且每一場氧化物島均自汲極側延伸穿過該閘極下方至源 極側,使得汲極擴散區中包括有複數個互相平行的擴散路 徑。 根據本發明的一特點,陣列狀場氧化物島中之每一場 氧化物島均係具有一似長方形的形狀,或是具有一似保齡 球瓶的形狀。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂,下文特舉一些較佳實施例,並配合所附圖式,作 詳細說明如下= 圖式之簡單說明: 第1圖繪示的是習知一種靜電放電保護電路的佈局上 6 -------r--^ -裝-- (請先閱讀背面之注意事項再填寫本頁) 訂 本紙張尺度適用中國國家標準(CNS ) Λ4規格(210Χ2()7公楚) 經濟部中央標準局員工消費合作社印聚 A7 B7 五、發明説明(艾) 視示意圖; 第2圖繪示的是對應於圖1的剖面示意圖; 第3圖繪示的是應用本發明之第一較佳實施例的佈局 上視示意圖; 第4圖繪示的是應用本發明之第二較佳實施例的佈局 上視示意圖;以及 第5圖繪示的是應用本發明之第三較佳實施例的佈局 上視示意圖。 第一實施例 請參照第3圖,圖3繪示的是應用本發明之第一較佳 實施例的佈局上視示意圖。第一汲極n+擴散區30形成在一 η型井31中,而第二汲極n+擴散區32則形成在矽基底(未 顯示)與η型井31中。由於場氧化物層33具有至少一根手 指(finger),例如在本較佳實施例中係爲多根手指33a-33g,每根手指均平行排列成陣列狀,且自汲極側貫穿整 個第二汲極n+擴散區32延伸穿過閘極34至源極側但不貫 穿源極n+擴散區35。故如圖所示,形成之第二汲極n+擴散 區32便被完全分割成多個擴散區塊32a-32h,而形成之源 極擴散區35則仍舊維持一完整區塊。每根手指33a-33g 均鄰接兩個相鄰的擴散區塊,例如手指33d鄰接擴散區塊 32d與32e,且擴散區塊32a-32h形成一平行的擴散路徑。 第一汲極n+擴散區30透過多個接觸窗37a-37g經由金屬導 線36a耦接到輸出入焊墊或vDD匯流排38,而源極n+擴散 區35則透過多個接觸窗39a-39h經由金屬導線36b耦接到 ___ 7 本紙張尺度適用中國國家標準(CNS ) Λ4規格(2丨0x 297公籍) 0509twf.doc/002 ----.--^--ί * 裝-- (請先閱讀背面之注意事項再填寫本頁) 訂 」 〇5〇9twf.doc/0〇2 A7 B7 五、發明説明u )
Vss匯流排。在本較佳實施例中,每一擴散區塊32a-32h均 有部份與η型井31重疊,故η型井31提供了從焊墊38經 由第一汲極η+擴散區30到每一擴散區塊32a-32h的阻抗路 徑’用以強化靜電放電事件時之靜電放電電流的均勻度。 當然’在本較佳實施例中,阻抗路徑係利用η型井31所產 生’然熟悉此藝者應知阻抗路徑中的電阻也可被其他形式 的阻抗材料所替換。 在本較佳實施例中,第二汲極ιΓ擴散區32被完全分割 成多個互相平行排列的擴散區塊32a-32h,結果是金氧半 電晶體300被分割成8個並列的小金氧半電晶體(如圖所 示),且每一小金氧半電晶體均串連一由η型井31所造成 的汲極阻抗。當靜電放電電流陷入(s wamp i n t 〇)某一小金 氧半電晶體時,串連的汲極阻抗會提昇該區域的汲極電 位,迫使靜電放電電流流往其他的小金氧半電晶體。這將 提昇電流的整體均勻性,且強化金氧半電晶體300作爲靜 電放電保護元件的穩固性(robustness)。又由於汲極阻抗 均是互相平行,故整體的有效汲極阻抗比個別汲極阻抗要 小很多,因此有效的汲極阻抗就不會影響N型金氧半電晶 體300的正常操作。 由第一較佳實施例得知,應用本發明克服了前述習知 技藝的缺點,且優點如下所述: 1.金氧半場效電晶體300被分割成多個小電晶體,每 一小電晶體之寬度均可以不受接觸窗到擴散區邊緣之間 隔極限的限制,而使寬度小到需求之尺寸’以增加分割效 8 m m i i (請先閲讀背面之注意事項再填寫本頁) 訂 」 經濟部中央標準局員工消費合作社印ii 本紙張尺度適用中國國家橾準(CNS ) Λ4規格(2丨0X297公釐〉 υ 5 G Pi 9twf.doc/002 A7 經濟部中央標準局員工消費合作杜印裝 B7 五、發明説明(1 ) 果。 2.對具有狹窄源極/汲極擴散區塊的電晶體而言,增加 了源極側的接觸窗數目。結果使得流經每一接觸窗的靜電 放電電流密度降低,進而增強了靜電放電保護的能力。 以下特舉一佈局設計的實例,讓讀者參考: 1. N型金氧半場效電晶體300之通道長度約0.5/^,而 其通道寬度約是60/zw ; 2. 每一擴散區塊32a-32h的寬度W約是; 3. 手指33a-33g的寬度G約是0.6//m ; 4. 手指33a-33g在汲極側的長度L約是3.5//m,而在源 極側的長度P約是〇 . 5 //m ; 5. 汲極側的接觸窗37a-37g到閘極34邊緣之間隔D約 是 5 ! 6. 源極側的接觸窗39a-39h到閘極34邊緣之間隔S約 是 2 //m。 第二實施例 請參照第4圖,圖4繪示的是應用本發明之第二較佳 實施例的佈局上視示意圖。圖4與圖3的差異是在圖4無η 井區,且在汲極側的汲極η+擴散區係爲一完整區塊,故在 第二較佳實施例中僅就有差異處做說明,其餘相同部份不 再贅述。首先設計複數個平行排列之陣列狀場氧化物島 40a - 40g,令其自汲極側延伸穿過閘極41下方至源極側, 使得因陣列狀場氧化物島40a-40g所形成之汲極n+擴散區 42具有如圖3般的形狀。其中,每一場氧化物島40a-40g 9 -----^--;--C 裝------訂------^ ‘ (請先閏讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS ) Λ4規格(210X297公釐) 0509twf.doc/002 A7 0509twf.doc/002 A7 經濟部中央標準局員工消費合作杜印製 B7 五、發明説明(2 ) 均具有一類長方形的形狀。在本較佳實施例中,因無η井 區,故須形成一完整的汲極擴散區塊42,以提供複數個平 行的汲極擴散路徑42a-42g。在這種擴散區結構中,每一 汲極擴散路徑42a-42g的阻値,係由每一擴散路徑42a-42g 中的n+片電阻(Sheet Resistance)決定。 以下特舉一佈局設計的實例,讓讀者參考: 1. N型金氧半場效電晶體400之通道長度約0.5///«,而 其通道寬度約是60_ ; 2. 每一擴散路徑42a-42h的寬度W約是2.4/zm ; 3. 場氧化物島40a-40g的寬度G約是0.6//m ; 4. 場氧化物島40a-40g在汲極側的長度L約是3.5///», 而在源極側的長度P約是0.5 //w ; 5. 汲極側的接觸窗43a-43g到閘極41邊緣之間隔D約 是 5 //w ; 6. 源極側的接觸窗44a-44h到閘極41邊緣之間隔S約 是 2 ° 第三實施例 接下來請參照第5圖,圖5繪示的是應用本發明之第 三較佳實施例的佈局上視示意圖。圖5是由圖4變化而得, 其特徵是汲極側的每一 n+擴散路徑均非如圖4般具有一類 長方形的形狀,而是由窄變寬。圖5中除了汲極側的n+擴 散路徑有別於圖4中者外,其餘部份均與圖4同,是故在 此僅就此差異處做說明。其餘部份只要是熟悉此藝者均可 輕易瞭解,故不再贅述。 本紙張尺度適用中國國家標準(CNS ) Α4規格(210Χ 297公釐) ----:--.--C -裝-- (請先閱讀背面之注意事項再填寫本頁)
,1T 0509twf.doc/002 A7 B7 五、發明説明(1 ) 圖5中之複數個平行排列的陣列狀場氧化物島50a-5〇g具有一似保齡球瓶的形狀,使得因之形成之汲極n+擴 散區51,提供了由窄變寬的擴散路徑51a-51h。也就是說, 當發生靜電放電事件時,靜電放電電流先自焊墊52流入汲 極n+擴散區51,接著由擴散路徑51a-5lh中的較窄路徑流 往較寬路徑,之後經由閘極53流向源極擴散區54。如圖5 般的狹窄擴散路徑結構所形成之串聯阻抗,更能提昇靜電 放電電流的均勻流向。 以下特舉一佈局設計的實例,讓讀者參考: 1. N型金氧半場效電晶體500之通道長度約0.5_,而 其通道寬度約是6 0//w ; 2. 每一擴散路徑51a-51h中較寬路徑的寬度W約是 而較窄路徑的寬度Η約是l//rn; 3. 場氧化物島50a-50g中較寬部份的寬度F約是2//m, 而較窄部份G約是0.6 _ ; 4. 場氧化物島50a-50g在汲極側的長度約是3.5//W, 而在源極側的長度約是0.5 //w ; 5. 汲極側的接觸窗53a-53g到閘極53邊緣之距離約是 5 μτη ; 6. 源極側的接觸窗54a-54h到閘極53邊緣之距離約是 Ί μτη。 較寬部份的寬度F約2/zrn,較窄部份場氧化寬度G約 0.6_,而n+擴散路徑被狹窄化部份其寬度Η約是,其 他分割擴散的寬度W約是2.4_。 本紙張尺度適用中國阀家標準(CNS ) Λ4規格(210 X 297公f ) (請先閱讀背面之注意事項再填离本頁) 裝. ,ιτ 經濟部中央標準局員工消f合作社印製 〇5〇9twf,doc/002 A7 B7 _ 五、發明説明(户) 雖然本發明已以一些較佳實施例揭露如上,然其並非 用以限定本發明,任何熟習此技藝者,在不脫離本發明之 精神和範圍內,當可作些許之更動與潤飾,因此本發明之 保護範圍當視後附之申請專利範圍所界定者爲準。 ^^1. ^^1 —^1 — -1 - - - - J H . n I (請先閲讀背面之注意事項再填寫本頁)
、tT
L 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標率(CNS ) Λ4規格(210X 297公釐)

Claims (1)

  1. 0509twf.doc/002 A8 B8 C8 D8 六、申請專利範圍 1. 一種靜電放電保護電路中具有部份分割擴散區的 金氧半場效電晶體架構,包括: 一閘極,形成在一矽基底上; 一井,形成在該閘極一側邊的該矽基底中; 一第一汲極擴散區,形成在該井中; 一第二汲極擴散區,形成在該矽基底與該井中; 一源極擴散區,形成在該閘極另一側邊的該矽基底 中; 一場氧化物層,形成在該矽基底上,其具有複數個手 指,自汲極側延伸穿過該閘極至源極側,使得該第二汲輯 擴散區被分割成複數個平行排列的陣列狀擴散區塊,而該 源極擴散區仍爲一完整區塊。 2. 如申請專利範圍第1項所述之架構,其中該金氧半 場效電晶體是N型金氧半場效電晶體。 3. 如申請專利範圍第2項所述之架構,其中該井係η 型井。 4. 如申請專利範圍第3項所述之架構,其中該第一、 第二汲極擴散區與源極擴散區均係η型擴散區。 5. —種靜電放電保護電路中具有部份分割擴散區的金 氧半場效電晶體架構,包括: 一閘極,形成在一矽基底上; 一汲極擴散區,形成在該閘極一側邊的該矽基底中; 一源極擴散區,形成在該閘極另一側邊的該矽基底 中; ---------^ ·裝------訂------^ (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家橾準(CNS〉Λ4规格(210Χ297公釐) 3050^ f.doc/002 六、申請專利範圍 一陣列狀場氧化物島,形成在該矽基底上,且每一場 氧化物島均自汲極側延伸穿過該閘極下方至源極側,使得 該汲極擴散區中包括有複數個互相平行的擴散路徑。 6. 如申請專利範圍第5項所述之架構,其中該金氧半 場效電晶體是N型金氧半場效電晶體。 7. 如申請專利範圍第6項所述之架構,其中該汲極擴 散區與源極擴散區均係η型擴散區。 8. 如申請專利範圍第7項所述之架構,其中每一場氧 化物島均具有一似長方形的形狀。 9. 如申請專利範圍第7項所述之架構,其中每一場氧 化物島均具有一似保齡球瓶的形狀,使得該些擴散路徑的 寬度在靠近該閘極側係較寬,而在遠離該閘極側係較窄。 (請先閱讀背面之注意事項再填寫本頁) -裝. 訂 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS ) Λ4規格(210Χ297公釐)
TW085109874A 1996-08-14 1996-08-14 The MOSFET in electro-static discharge protecting circuit TW305071B (en)

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