3〇4283 i、發明説明（1) 經濟部中央標準局員工消費合作杜印製 發明領域 本案係關於一種半導體元件之製造方法，尤指一種在 半導體元件中形成無損害（damage-free)埋層接觸之方 法。 發明背景 埋層接觸（buried contact)係一種電子接觸，用以連 接複晶矽層至半導體基體中的摻雜逦域（dopped region) »埋層接觸已廣泛地使用於CMOS SRAM電路 中。一個CMOS SRAM單元（cell)包括二負載電阻，二拉 低（pull down)電晶體，及二旁路（pass)電晶體。其中一 拉低電晶體利用埋層接觸來連接其閘極與其它拉低電晶體 的汲極。在典型的SRAM單元佈局中，該等拉低電晶體的 汲極也被做爲該等旁路電晶體的閘極使用，而該等旁路電 晶體提供位元線（bit-line)至記憶單元的存取。 習知用以形成埋餍接觸之製程表示於圖la至le。在圖 la中表示了一 P型半導體基體12，於基體12中已完成一些 半導體元件製程之處理步驟。一薄氧化層14形成於基體12 之上，以做爲一閘極介電質層使用。在薄氧化層14形成後 立即沉積一薄複晶矽層16。薄複晶矽層16及薄氧化層14利 用光阻罩幕18(圖lb)及蝕刻被形成圖案，以便形成一埋曆 2 本紙張尺度適用中國國家標準（CNS ) Α4規格（2Ι0Χ297公釐） (請先閲讀背面之注意事項再填寫本頁) 裝-3〇4283 i. Description of the invention (1) Employee's consumption cooperation of the Central Bureau of Standards of the Ministry of Economic Affairs Du Printed Invention Field of the Invention This case relates to a method of manufacturing a semiconductor element, especially a damage-free buried layer formed in a semiconductor element Method of contact. BACKGROUND OF THE INVENTION A buried contact is an electronic contact used to connect a polycrystalline silicon layer to a doped region in a semiconductor substrate. »Buried contact has been widely used in CMOS SRAM circuits. A CMOS SRAM cell includes two load resistors, two pull down transistors, and two pass transistors. One of the pull-down transistors uses buried layer contacts to connect its gate to the drains of other pull-down transistors. In a typical SRAM cell layout, the drains of the pull-down transistors are also used as the gates of the bypass transistors, and the bypass transistors provide bit-lines to the memory Unit access. The conventional process for forming buried contacts is shown in Figures la to le. In FIG. 1a, a P-type semiconductor substrate 12 is shown, in which some processing steps of the semiconductor device manufacturing process have been completed. A thin oxide layer 14 is formed on the substrate 12 for use as a gate dielectric layer. A thin polycrystalline silicon layer 16 is deposited immediately after the thin oxide layer 14 is formed. The thin polycrystalline silicon layer 16 and the thin oxide layer 14 are patterned using a photoresist mask 18 (FIG. 1b) and etching, so as to form a buried calendar. The paper size is applicable to the Chinese National Standard (CNS) Α4 specification (2Ι0Χ297 mm) (please Read the precautions on the back before filling out this page)
<1T 3〇4283 五、發明説明（2 ) 經濟部中央標準局員工消費合作杜印製 接觸20(圖1〇。光阻罩幕隨後被移開，並沉稹一複晶矽層 24於薄複晶矽層16及埋層接觸區域20之上·接著，複晶砍 層16及24被摻雜P〇Cl3以降低複晶矽層16及24之電阻， 並於基體12中形成一N +區域，如圖Id所示。複晶矽層16 及24藉由一光阻罩幕形成圖案，並被施予非等向 (anisotropic)蝕刻處理，以便形成閘極27及中間連接層 26，這表示在圖le »既然複晶矽及矽基體都包含矽，非等 向蝕刻步驟也以大約相同的蝕刻速率蝕刻矽基體12。溝槽 (trenCh)30在形成閘極27及中間連接層26所使用之蝕刻 步驟中被形成。溝槽30的形成是我們所不想要的，因爲它 提供了 N +區域22與基體12之間的漏電流路徑。 因此，本發明之主要目的在提供一種在半導體基體中 形成埋層接觸之方法，該方法不具有習知方法之缺失及短 處。 本發明之次一目的在提供一種於半體基體中形成無損 害埋餍接觸之方法。 本發明之另一目的在提供一種在半導體基體中形成埋 靥接觸之方法，該方法不會產生如溝槽或凹窪區域（pitted areas)等缺陷。 本發明之又一目的在提供一種在半導髏基體中形成埋 層接觸之方法，該方法不會產生溝槽及N +區域與P-型矽基 體間之次漏電流路徑。 3 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) -3 經濟部中央標準局員工消費合作社印製 A7 __ B7 五、發明説明（3 ) 本發明之再一目的在提供一種在半導體基體中形成埋 靥接觸之方法，其使用在基體之不同材料間具有髙蝕刻選 擇性之蝕刻氣體。 本發明仍有一目的，在於提供一種在半導體基體中形 成埋靥接觸之方法，其使用在不同材料的複晶矽，氧化砂 與單晶矽材料間具有髙蝕刻選擇性之蝕刻氣體。 發明綜合說明 本發明提供一種不會產生如溝槽或凹窪區域（pitted areas)等缺陷之形成半導體基體內之埋層的方法。 在本發明之較佳實施例中，形成第一導電型態之半導 體基體內之埋層的方法可以經由下列步驟實施：形成一做 爲閘極介電質層之氧化矽層於基體之上，形成第一複晶矽 層於該氧化矽層之上，藉由使用第一軍幕及第一蝕刻氣體 而非等向蝕刻掉該第一複晶矽層，其中該蝕刻氣體在複晶 矽與氧化矽之間具有髙蝕刻選擇性，以便該複晶矽層之第 一部份被存留於該基體上除了一埋層接觸區域以外之處， 藉由佈植雜質離子|在基體內之埋厝接觸區域形成一第二 導電型態區域，移去定義爲埋層接觸區域上之氧化矽層並 移去該複晶矽層之第一部份上之罩幕層，依序沉積一導電 層及一第二複晶矽層，藉由一第二罩幕及第二蝕刻氣體非 等向蝕刻定義一電晶雔閘極及中間連接層區域之外上方之 第二複晶層，該第二蝕刻氣體具有複晶矽與導電層間的髙 4 本紙張尺度適用中國國家標準（CNS ) A4規格（21〇X297公釐） (請先閲讀背面之注意事項再填寫本頁) -裝- 、·!! 經濟部中央樣準局員工消费合作社印製 A7 B7 五、發明説明（4 ) 度蝕刻選擇性，藉由一第三蝕刻氣體非等向蝕刻形成電晶 體閘極及中間連接層區域，該第三蝕刻氣體具有複晶矽， 導電層與矽之間的髙度蝕刻選擇性，以及，藉由在氧或水 的環境中加熱，將殘留於閘極及中間連接區域外之第一複 晶矽層以氧化方式消耗掉。 在另一實施例中，在定義爲埋層接觸之區域上之矽氧 化層可以在佈植雜質離子至其基體之埋層接觸區域內以形 成一第二導電型態區域之步驟前被移走。 本發明更注意到以本發明方法所製造之埋層接觸，其 中，具有髙蝕刻選擇性的蝕刻氣體被使用，因此只有複晶 矽層及導電層被蝕刻掉，而不會對矽基體造成損害。 圖式簡要說明 本發明得藉下列圖式及詳細說明，俾得一深入了解： 第la-le圖：係習知形成埋層接觸之方法之截面放大 圖。 第2-9圖：係本發明形成埋層接觸之方法之截面放大 圖。 特別說明的是，爲了舉例說明，圖式中的元件並不必 —定成比例表示。爲了淸楚表示的目的，有時元件的尺寸 會相對其它部份被誇大。 較佳實施例詳細說明 5 本紙張尺度適用中國國家橾準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝·< 1T 3〇4283 V. Description of the invention (2) Employee ’s consumer cooperation of the Central Bureau of Standards of the Ministry of Economic Affairs du printed contact 20 (Figure 10. On the thin polycrystalline silicon layer 16 and the buried layer contact area 20. Next, the polycrystalline silicon cut layers 16 and 24 are doped with PCl3 to reduce the resistance of the polycrystalline silicon layers 16 and 24, and an N + region is formed in the substrate 12 , As shown in Id. The polycrystalline silicon layers 16 and 24 are patterned by a photoresist mask and subjected to anisotropic etching to form the gate electrode 27 and the intermediate connection layer 26, which means In FIG. »Since both polycrystalline silicon and the silicon substrate contain silicon, the non-isotropic etching step also etches the silicon substrate 12 at about the same etch rate. The trench (trenCh) 30 is used to form the gate 27 and the intermediate connection layer 26 Is formed during the etching step. The formation of the trench 30 is undesirable because it provides a leakage current path between the N + region 22 and the substrate 12. Therefore, the main object of the present invention is to provide a semiconductor substrate The method of forming the buried layer contact in the method, this method does not have the lack of the conventional method and The second object of the present invention is to provide a method for forming a non-damaging buried contact in a half-body substrate. Another object of the present invention is to provide a method for forming a buried contact in a semiconductor substrate, which method does not produce Defects such as trenches or pitted areas. Another object of the present invention is to provide a method for forming a buried layer contact in a semi-conductor skull base, which does not produce trenches and N + regions and P- The secondary leakage current path between the silicon substrates. 3 This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) (please read the precautions on the back before filling this page) -3 Employee consumption of the Central Standards Bureau of the Ministry of Economic Affairs Printed by the cooperative A7 __ B7 V. Description of the invention (3) Another object of the present invention is to provide a method for forming a buried contact in a semiconductor substrate, which uses an etching gas with high etching selectivity between different materials of the substrate. The present invention still has an object to provide a method for forming a buried contact in a semiconductor substrate, which uses polycrystalline silicon, oxidized sand and single crystal silicon materials of different materials Etching gas with high etching selectivity. Summary of the invention The present invention provides a method for forming a buried layer in a semiconductor substrate without generating defects such as trenches or pitted areas. It is preferred in the present invention In an embodiment, the method of forming the buried layer in the semiconductor substrate of the first conductivity type can be implemented through the following steps: forming a silicon oxide layer as a gate dielectric layer on the substrate to form the first polycrystalline silicon Layer on the silicon oxide layer, the first polycrystalline silicon layer is etched away instead of isotropically by using the first military curtain and the first etching gas, wherein the etching gas has a high temperature between the polycrystalline silicon and the silicon oxide Etching selectivity, so that the first part of the polycrystalline silicon layer is retained on the substrate except for a buried layer contact area, by implanting impurity ions | buried contact area in the substrate to form a second Conductive type region, defined as the silicon oxide layer on the contact area of the buried layer and the mask layer on the first part of the polycrystalline silicon layer are removed, and a conductive layer and a second polycrystalline silicon are deposited in sequence Layer, with a second mask Anisotropic etching with the second etching gas defines an electric crystal gate and a second polycrystalline layer above the intermediate connection layer area. The second etching gas has a high temperature between the polycrystalline silicon and the conductive layer. China National Standard (CNS) A4 Specification (21〇X297mm) (Please read the precautions on the back before filling in this page) -installed-, · !! A7 B7 printed by the Employee Consumer Cooperative of the Central Bureau of Standards, Ministry of Economic Affairs Description of the invention (4) Degree of etching selectivity, the transistor gate and the intermediate connection layer region are formed by anisotropic etching of a third etching gas, the third etching gas has polycrystalline silicon, a high layer between the conductive layer and the silicon The degree of etching selectivity, and, by heating in an oxygen or water environment, the first polycrystalline silicon layer remaining outside the gate and the intermediate connection area is consumed by oxidation. In another embodiment, the silicon oxide layer on the region defined as the buried layer contact can be removed before the step of implanting impurity ions into the buried layer contact region of its substrate to form a second conductivity type region . The present invention pays more attention to the buried layer contact manufactured by the method of the present invention, in which an etching gas with high etching selectivity is used, so only the polycrystalline silicon layer and the conductive layer are etched away, without damaging the silicon substrate . Brief Description of the Drawings The present invention can be understood in depth by the following drawings and detailed descriptions: Figure la-le: It is an enlarged cross-sectional view of a conventional method for forming a buried layer contact. Figures 2-9 are enlarged cross-sectional views of the method for forming a buried layer contact of the present invention. In particular, for illustrative purposes, the elements in the drawings do not have to be expressed to scale. For the purpose of Chu Chu, sometimes the size of the component will be exaggerated relative to other parts. Detailed description of the preferred embodiment 5 This paper size is applicable to China National Standard (CNS) A4 (210X297mm) (Please read the precautions on the back before filling this page)
、1T A7 B7 一·_ .. -- 五、發明説明（5 ) 經濟部中央標準局員工消費合作社印製 本發明揭示一種形成半導體基體中之埋層接觸之方 法。本案方法可以產生不具有如基體上之溝槽或凹窪區域 等缺陷之埋層接觸。 請參閲圖2，其表示具有一矽基體42之半導體元件40 之截面放大圖。所表示之矽基體爲P-型基體。例如，以形 成一N·通道元件而言，基體42最好是被摻雜硼的單晶矽· 如果是使用小型基體，則以形成一 N-通道元件而言，此N-通道元件應被製造在P型井區中。 氧化矽材料的閘極介電質層44首先被形成於矽基體42 之上。此氧化層可以藉由熱氧化過程或化學氣相沉積（CVD) 過程而被形成，厚度大約在5-20nm之間。一薄複晶矽層 46隨後藉由化學氣相沉積技術被沉積在氧化矽層之上，厚 度大約在S-lOOnm之間。複晶矽層46的作用在於保護閘極 介電質層免於外部的污染。其沉積溫度通常介於600-700 °C之間· 如圖3所示，塗佈厚度介於大約5 0 0 -2 0 0 0 nm之間的光 阻層48，以便定義出埋層接觸之圖案。在下一處理步驟 中，埋層接觸區域上方之複晶矽層藉由電漿蝕刻處理而被 非等向蝕刻去除。此步驟表示在圖4。必需注意的是，只有 複晶矽46係藉著使用在複晶矽與氧化矽之間具有髙蝕刻選 擇性之蝕刻氣體而被蝕刻去除，也就是說，蝕刻氣體對複 晶矽具有髙蝕刻速率而對氧化矽則具有低蝕刻速率。蝕刻 氣體可以是下列任何一種混合氣體，SiCb/Cli、BCb/Ch、 6 本紙張尺度適用中國國家標準（CNS ) A4規格（210>< 297公釐） (請先閱讀背面之注意事項再填寫本頁) -裝- 訂 304283 五、發明説明（6) HBr/Cb/〇2、Br/SF6、及SF6/〇2。也可以使用其它等效的蝕刻氣 體。 在下一製程步驟中，N·型態離子被植入基體內之埋層 接觸區域以便形成一N +區域。所植入之雜質離子可以是碟 或砷。當被植入之離子爲磷時，所使用之佈植能量大約介 於10-80kev之間，而濃度大約在lE15-8E15/cm2之間。 當被植入之離子爲砷時，所使用之佈植能量大約介於10-lOOkev之間，而濃度大約在1E15-7E15/Cm2之間。在離 子佈植步驟後，基體通常在髙於8 00 °C的溫度下被退火。然 而，此退火步驟也可以在稍後的階段中完成。在製程的下 一階段中，如圖5所示，埋層上的氧化矽藉由濕蝕刻或乾蝕 刻方法而被移走。乾蝕刻時所使用的蝕刻氣體可以是 CCI2F2、CHF3/CF4、CHF3/〇2、及 CH3CHF2。濕蝕刻 的蝕刻方法，如以HF爲基礎之溶液，或以HF爲基礎之溶 液加上如NH4F2緩衝劑，也可以在此蝕刻步驟中使用。 經濟部中央標準局員工消費合作杜印製 I---„--.Ί. I----裝-- (請先閲讀背面之注意事項再填寫本頁) 應該注意的是，上述之離子植入步驟也可以在埋層接 觸上之氧化矽層首先被移走後實施。當離子植入步驟在氧 化層移開步驟之後被實施時，磷離子可以在5-70kv的佈植 能量及1E15-8E15/Cm2的離子濃度下被植入，而砷離子 可以在5-80kv的佈植能量及lE15-7E15/cm2的離子濃度 下被植入》 在移開氧化層後，光阻層隨後被移開。在本發明之實 施中，可以使用不同的方法移開光阻層。例如，由IndUS-R-Chem生產之以酚爲基礎之J-100有機去除劑 7 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） A7 _____B7 五、發明説明（7 ) (stripper)，或 Allied Chemical 生產之 A20 ’ 以及 EKC Chemical生產之例如BURMAR 712之無酚有機去 除劑（phenol-free organic stripper)，Allied Chemical生產之Ecostrip，或 Shipely生產之Demover 1112A。如H2SO4/H2O2等氧化型態的 去除劑可以在100-150 °C的溫度下使用。如氧電漿之乾去 除技術也可以被用來移開光阻層。、 1T A7 B7 1. _ ..-V. Description of the invention (5) Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs This invention discloses a method of forming a buried layer contact in a semiconductor substrate. The method in this case can produce buried layer contacts that do not have defects such as trenches or depressions in the substrate. Please refer to FIG. 2, which shows an enlarged cross-sectional view of a semiconductor device 40 having a silicon substrate 42. The silicon substrate shown is a P-type substrate. For example, in terms of forming an N-channel element, the substrate 42 is preferably boron-doped single crystal silicon. If a small substrate is used, in terms of forming an N-channel element, the N-channel element should be Manufactured in the P-well area. The gate dielectric layer 44 of silicon oxide material is first formed on the silicon substrate 42. The oxide layer can be formed by a thermal oxidation process or a chemical vapor deposition (CVD) process, and the thickness is about 5-20 nm. A thin polycrystalline silicon layer 46 is then deposited on the silicon oxide layer by chemical vapor deposition techniques, with a thickness of approximately S-100 nm. The function of the polycrystalline silicon layer 46 is to protect the gate dielectric layer from external pollution. The deposition temperature is usually between 600-700 ° C. As shown in FIG. 3, the photoresist layer 48 with a thickness between about 500-2000 nm is coated to define the contact of the buried layer pattern. In the next processing step, the polycrystalline silicon layer above the buried layer contact area is removed by anisotropic etching by plasma etching. This step is shown in Figure 4. It must be noted that only polycrystalline silicon 46 is etched and removed by using an etching gas with a high etching selectivity between polycrystalline silicon and silicon oxide, that is, the etching gas has a high etching rate for polycrystalline silicon The silicon oxide has a low etching rate. Etching gas can be any of the following mixed gases, SiCb / Cli, BCb / Ch, 6 This paper standard is applicable to China National Standard (CNS) A4 specification (210 > < 297mm) (Please read the notes on the back before filling in (This page)-Binding-Order 304283 V. Description of the invention (6) HBr / Cb / 〇2, Br / SF6, and SF6 / 〇2. Other equivalent etching gases can also be used. In the next process step, N-type ions are implanted into the contact area of the buried layer in the substrate to form an N + region. The impurity ions implanted can be dish or arsenic. When the implanted ion is phosphorus, the implantation energy used is approximately 10-80kev, and the concentration is approximately 1E15-8E15 / cm2. When the implanted ion is arsenic, the implantation energy used is about 10-100kev, and the concentration is about 1E15-7E15 / Cm2. After the ion implantation step, the substrate is usually annealed at a temperature of 800 ° C. However, this annealing step can also be completed at a later stage. In the next stage of the process, as shown in Figure 5, the silicon oxide on the buried layer is removed by wet etching or dry etching. The etching gas used in dry etching may be CCI2F2, CHF3 / CF4, CHF3 / 〇2, and CH3CHF2. Wet etching etching methods, such as HF-based solutions, or HF-based solutions plus buffers such as NH4F2, can also be used in this etching step. Du Printed I --- „-. Ί. I ---- Dressed by Employee Consumer Cooperation of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page) It should be noted that the above The implantation step can also be performed after the silicon oxide layer on the buried layer contact is first removed. When the ion implantation step is performed after the oxide layer removal step, the phosphorus ion can be implanted at 5-70 kV and 1E15 -8E15 / Cm2 ion implantation, and arsenic ions can be implanted at an implantation energy of 5-80kv and an ion concentration of lE15-7E15 / cm2. After removing the oxide layer, the photoresist layer is then Removal. In the implementation of the present invention, different methods can be used to remove the photoresist layer. For example, the phenol-based J-100 organic remover produced by IndUS-R-Chem (CNS) A4 specification (210X297mm) A7 _____B7 5. Description of invention (7) (stripper), or A20 'produced by Allied Chemical and EKC Chemical produced phenol-free organic stripper such as BURMAR 712 (phenol-free organic stripper ), Ecostrip produced by Allied Chemical, or Shipel Demover 1112A produced by Y. Oxidative removal agents such as H2SO4 / H2O2 can be used at a temperature of 100-150 ° C. Dry removal techniques such as oxygen plasma can also be used to remove the photoresist layer.
TiN或TiW材料的導電層隨後藉由化學氣相沉積技術 被沉積，厚度大約在l〇-200nm之間。嫌鍍（sputtering) 沉積技術也可被用來沉積導電層50。如圖6所示，在導電層 50上方，一厚度大約介於1 00-500nm之間的複晶矽屠56 被沉積。該複晶矽層56可藉由化學氣相沉稹技術在600-700 °C的溫度下被沉積。然後複晶矽層56在具有做爲P來源 之POC13的爐管（furance)中，於大約800-1000 °C的溫 度下藉由擴散步驟而被摻雜，以便降低其電阻。複晶矽層 56下方之導電層50係爲一擴散障礙層，如此則P離子不會 擴散入矽基體42內。複晶矽的電阻從擴散步驟前的500-2 0 0 0 Ω/平方被降低至擴散步騍後的2 0 - 1 0 0 Ω/平方。 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 在下一步驟中，如圖7所示，光阻層58被塗佈以便在矽 基體上定義電晶髓閘極及中間連接層圖案。然後使用非等 向蝕刻將電晶體閘極及中間連接層區域以外之複晶矽層S6 蝕刻掉，並以導電層50做爲蝕刻停止層以防止對矽基體所 造成的損害。所使用的蝕刻氣體與前述複晶矽層所使用者 相同•非等向蝕刻通常在使用組合的蝕刻氣體及反應器環 境之活性離子蝕刻（RIE)反應器中進行，如此可使垂直向 8 本紙張尺度適用中國國家揉準（CNS ) A4規格（210X297公釐） 五、發明説明（8 ) A7 B7 經濟部中央標準局員工消費合作杜印製 材料之蝕刻速率大於水平向材料之蝕刻速率·這產生了想 要的實質垂直邊壁結構》此外，所選擇的蝕刻氣體應該對 複晶矽層具有髙蝕刻速率而對其下方之層，即導電層，具 有低蝕刻速率。換句話說，在複晶矽層與導電層間具有一 髙的蝕刻選擇性，以便該導電層可做爲蝕刻複晶矽用之合 適的蝕刻停止層。 然後使用電漿蝕刻步驟以非等向蝕刻去除電晶體閘極 及中間連接62中之導電層50。這表示於圖8。當導電層爲 TiN材料時，所使用的蝕刻氣體爲ClWAr。當導電層爲 TiW材料時，所使用的蝕刻氣體爲SF6/Ar或SF6/N2。所 使用的蝕刻氣體必需具有髙的導電層、矽層與複晶矽層之 間的蝕刻選擇性。利用髙的蝕刻選擇性，矽基體42在位於 電晶體閘極及中間連接62之導電層50被蝕刻的期間將不會 被損害。然而，不可避免地在電晶體閘極及中間連接62中 會有第一複晶矽層留置。 爲了除去電晶體閘極及中間連接62中之第一複晶矽層 且不損害矽基體42，最好使用氧化方法。在藉由前述某一 方法除去光阻層後，一髙溫氧化步驟於〇2或H2〇氣體之爐 管中進行，溫度介於700- 1 1 50 °C，可有效氧化殘留的第一 複晶矽層並形成矽基體42內之氧化矽64 ·此氧化過程所需 的時間大於10分鐘。這表示在圖九。藉由使用本發明新穎 的方法，不會對矽基體42產生任何損害❶ 9 本紙張尺度適用中國國家榡準（CMS > A4規格（210X297公釐） I . I 1.—.--.ί 裝-- (請先閲讀背面之注意事項再填寫本頁) 訂 r A7 B7 五、發明説明（9 ) 應該注意的是，本案較佳實施例中之晶圓所使用的是 P —型態基體，但本案方法同樣適用於N·型基體。在N·型基 體中，埋層接觸應該是在P·型井（well)中製造。 雖本發明以一實施例方式描述，然應了解的是，所使 用的術語係爲自然的文字描述，而非用以限制本發明。 雖本發明係以一較佳實施例而爲描述，但熟悉本技藝 之人士顯然可以輕易地使用本發明的技術啓示至本發明其 它可能的變化》例如，複晶矽被表示爲所欲之形成基體中 埋層接觸用的材料。然而，任何其它具有相似共形 (conform)，電子及摻雜遷移特性的材料也適合在本發明 方法中使用》 m> m n-. n nn In ^^^1 i - > 0¾ 、ve (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製The conductive layer of TiN or TiW material is subsequently deposited by chemical vapor deposition techniques with a thickness of approximately 10-200 nm. Sputtering deposition techniques can also be used to deposit the conductive layer 50. As shown in FIG. 6, above the conductive layer 50, a polycrystalline silicon wafer 56 with a thickness between about 100-500 nm is deposited. The polycrystalline silicon layer 56 can be deposited at a temperature of 600-700 ° C by chemical vapor deposition technology. The polycrystalline silicon layer 56 is then doped in a furnace with POC13 as a P source at a temperature of about 800-1000 ° C through a diffusion step in order to reduce its resistance. The conductive layer 50 under the polycrystalline silicon layer 56 is a diffusion barrier layer, so that P ions will not diffuse into the silicon matrix 42. The resistance of polycrystalline silicon is reduced from 500-2 0 0 0 Ω / square before the diffusion step to 2 0-1 0 0 Ω / square after the diffusion step. Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page) In the next step, as shown in Figure 7, the photoresist layer 58 is coated to define the electrical crystal on the silicon substrate Gate and intermediate connection layer patterns. Then, anisotropic etching is used to etch away the polycrystalline silicon layer S6 outside the transistor gate and the intermediate connection layer area, and the conductive layer 50 is used as an etch stop layer to prevent damage to the silicon substrate. The etching gas used is the same as the user of the aforementioned polycrystalline silicon layer. • Anisotropic etching is usually carried out in a reactive ion etching (RIE) reactor using a combination of etching gas and the reactor environment. The paper scale is applicable to China National Standard (CNS) A4 specification (210X297mm). V. Description of invention (8) A7 B7 The etching rate of the printed materials for consumer cooperation of the Central Standards Bureau of the Ministry of Economic Affairs is greater than that of the horizontal materials. This The desired substantially vertical side wall structure is generated. In addition, the selected etching gas should have a high etching rate for the polycrystalline silicon layer and a low etching rate for the layer below it, that is, the conductive layer. In other words, there is a high etch selectivity between the polycrystalline silicon layer and the conductive layer, so that the conductive layer can be used as an appropriate etch stop layer for etching polycrystalline silicon. A plasma etching step is then used to remove the transistor gate and the conductive layer 50 in the intermediate connection 62 by anisotropic etching. This is shown in Figure 8. When the conductive layer is TiN material, the etching gas used is ClWAr. When the conductive layer is TiW material, the etching gas used is SF6 / Ar or SF6 / N2. The etching gas used must have high etching selectivity between the conductive layer, the silicon layer and the polycrystalline silicon layer. With high etching selectivity, the silicon substrate 42 will not be damaged while the conductive layer 50 located at the transistor gate and intermediate connection 62 is etched. However, it is inevitable that a first polysilicon layer will remain in the transistor gate and intermediate connection 62. In order to remove the first polycrystalline silicon layer in the transistor gate and the intermediate connection 62 without damaging the silicon substrate 42, it is preferable to use an oxidation method. After removing the photoresist layer by one of the aforementioned methods, a high-temperature oxidation step is carried out in a furnace tube of 〇2 or H2〇 gas at a temperature between 700-1 150 ° C, which can effectively oxidize the remaining first complex The crystalline silicon layer forms silicon oxide 64 within the silicon matrix 42. The time required for this oxidation process is greater than 10 minutes. This is shown in Figure IX. By using the novel method of the present invention, it will not cause any damage to the silicon substrate 42 ❶ 9 This paper standard is applicable to the Chinese National Standard (CMS > A4 specification (210X297mm) I. I 1 .—.--. Ί Loading-(Please read the precautions on the back before filling in this page) Order r A7 B7 V. Description of the invention (9) It should be noted that the wafer in the preferred embodiment of this case uses a P-type substrate However, the method in this case is also applicable to N · type substrates. In N · type substrates, the buried layer contact should be manufactured in P · type wells. Although the invention is described in an embodiment, it should be understood that The terminology used is a natural text description, not to limit the present invention. Although the present invention is described in terms of a preferred embodiment, those skilled in the art obviously can easily use the technical inspiration of the present invention To Other Possible Changes of the Invention "For example, polycrystalline silicon is represented as a desired material for forming a buried layer contact in a substrate. However, any other material with similar conformal, electron and doping migration characteristics is also Suitable for use in the method of the invention Use》 m > m n-. N nn In ^^^ 1 i-> 0¾, ve (please read the precautions on the back before filling this page) Printed by Employee Consumer Cooperative of Central Bureau of Standards, Ministry of Economic Affairs
ο --H 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐）ο --H This paper scale is applicable to China National Standard (CNS) A4 specification (210 X 297 mm)