經濟部智慧財產局員工消費合作社印製 L ^ 4 1 0 1 p • A7 ____B7____ 五、發明說明（/ ) 技麵域： 本發明係關於一種半導體元件之自行對準接觸窗cSAC) 的製作方法，特別是關於一種位於閘極結構側壁上之絕緣間 隙壁（spacer)的製作方法。 發明背景： ,隨著半導體元件進入次微米製程後，改善了元件的性能 並降低了元件之生產成本，而半導體工業的發展也一直持續 不斷的朝提高性能及降低成本的方向努力。次微米技術製作 之半導體元件可降低電容及電阻的不良率，此外，因爲次微 米製程提供較小的半導體晶片（chip)，所以單一晶圓基板 上則可得到較多的晶片，如此便降低了每一晶片的生產成 本。半導體製程中之微影與乾式蝕刻技術是尺寸極小化發展 中之主要貢獻者，例如更複雜的曝光機臺，更敏感的感光材 料的使用，讓次微米線路圖案會gm複的顯影於光阻層上，而 更佳之乾式蝕刻方法則可成功的將光阻圖案轉換到下層結構 上。 另外利用半導體製程的特殊設計，例如：自行對準接觸 窗（SAC)的應用，亦可發展更小及更快的半導體元件。自 行對準接觸窗係指開啓一接觸窗孔洞，並露出閘極結構間之 摻雜源極/汲極，爲了要使閘極結構保持一最小之間距，且 能使自行對準接觸窗結構完全置於摻雜源極/汲極區域上 方，則必須提供比現今微影技術所能提供的更小的接觸窗孔 洞（contact hole)。所以自行對準接觸窗的槪念才被應用， 先開啓一大於閘極結構間距的孔洞’並露出摻雜源極/汲極 _____2------ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） — IHIIKI — ^ I · I E I I 1· 1 I 一SJ ^ I I I— n I I I (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 A7 __B7_ 五、發明說明（）） 區域與部份的閘極結構頂端，如同閘極結構側壁上之氮化矽 間隙壁，閘極結構亦具有一氮化矽頂層。隨後，沉積導電層 形成一大於開啓之自行對準接觸窗半徑的導電層接觸窗插 塞，使導電層能與自行對準接觸窗下方之摻雜源極/汲極相 接觸。 ,一般而言，自行對準接觸窗乃開啓於絕緣層之中，所述 絕緣層通常爲一硼磷砂玻璃，所述硼磷政玻璃往往在形成間 隙壁之後才沉積，並直接覆蓋在摻雜源極/汲極區域之上， 利用此種製程步驟會使得硼磷砍玻璃中摻雜之硼或磷離子因 爲向外擴散而進入摻雜源極/汲極區域，導致不必要的離子 互補償作用；另外，開啓自行對準接觸窗時所利用之非均向 RIE蝕刻法，亦在可蝕刻終點處或過渡蝕刻時移除氧化砂隔 離區域。本發明係揭露一種可開啓自行對準接觸窗但不會造 成摻雜源極/汲極被再植入雜質的缺點，也不會傷害到氧化 矽隔離區域之製作方法。本發明製作了一部份氮化矽間隙壁 與一位於閘極結構間摻雜源極/汲極上之氮化矽薄層，所述 氮化矽薄層可保護摻雜源極/汲極，免於被覆蓋上的硼磷矽 玻璃擴散出之硼或磷植入。本發明亦利用一兩段式蝕刻法開 啓自行對準接觸窗，第一步先利用蝕刻硼磷矽玻璃之速率大 於蝕刻氮化矽的蝕刻劑，並令RIE蝕刻反應終止於氮化矽薄 層上；接著，第二步利用蝕刻氮化矽之速率大於蝕刻氧化矽 的蝕刻劑，將氮化砂薄層移除。由美國專利第5643824號中 揭露了利用氮化矽的延長來避免場氧化（FieldOxide; FOX) 區域之鳥嘴（birds beak)現象產生，但先前的發明並未利 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公爱） I ϊ ----r--— II 裝-----訂---------吹 <請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 4 41 u 1 2 A7 _________B7 _ 五、發明說明（^ ) 用氮化矽薄層來覆蓋摻雜源極/汲極區域，也沒有利用兩段 式之非均向RIE飩刻法來選擇性移除氮化砂薄層以開啓自行 對準接觸窗。 發明之槪述： 本發明之主要目的爲製作金氧半場效電晶體（Metal Oxide Semiconductor Field Effect Transistor; MOSFET) 之自行對準接觸窗。 本發明之另一目的爲閘極結構側壁上之部份氮化矽間隙 •壁的製作，並在閘極結構間之摻雜源極/汲極上留下一氮化 砂薄層。 本發明之又一目的是於硼麟砂玻璃（BPSG)中開啓一自 行對準接觸窗，利用非均向RIE法，選擇蝕刻硼磷砂玻璃 (BPSG)之速率大於飽刻氮化矽的蝕刻劑，令飽刻反應終止 於氮化矽薄層上。 本發明之再一目的爲一完整自行對準接觸窗的製作，利 用非均向RIE法蝕刻氮化矽薄層，選擇蝕刻氮化矽之速率大 於蝕刻硼磷矽玻璃或氧化矽的蝕刻劑，露出閘極結構間之摻 雜源極/汲極。 本發明製作自行對準接觸窗結構的方法，利用兩段式非 均向RIE蝕刻法進行部份氮化矽間隙壁的製作，此設計可保 護摻雜源極/汲極及隔離區域，避免其受上覆結構之材質影 響和避免過度蝕刻造成的傷害。爲了達到上述之各項目的， 本發明使用了以下的方法：首先，提供一半導體基板，其中 摻雜源極/汲極位於兩閘極結構間之基板中，而閘極結構則 ______4--— 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---i-------IHI!^-------i 訂------t!線 (請先閱讀背面之注意事項再填窵本頁) 經濟部智慧財產局員工消費合作社印製 :.4 4 1 CM 2 A7 —______B7____—- 五、發明說明（if) 位於閘極絕緣層或隔離區域上；接著，沉積一氮化砂層’並 利用非均向RIE飽刻法進行部份回蝕，在閘極結構間之摻雜 源極/汲極上留有一氮化矽薄層，而在閘極結構的側壁形成 —氮化矽層間隙壁；再接著，沉積一硼鱗政玻璃，並利用微 影技術及非均向RIE蝕刻，開啓第一階段之自行對準接觸 窗，此步驟係選擇蝕刻硼磷政玻璃之速率大於蝕刻氮化矽的 蝕刻劑，而蝕刻反應會終止於氮化矽薄層上；然後，將光阻 移除，並開啓第二階段之自行對準接觸窗，此步驟係選擇蝕 刻氮化矽之速率大於蝕刻硼磷砂玻璃或氧化矽的蝕刻劑，將 閘極結構間氮化矽薄層移除，而露出摻雜源極/汲極區域； 最後，沉積一金屬或複晶矽材質，並形成與自行對準接觸窗 中之摻雜源極/汲極接觸的導電層圖案，即完成了自行對準 接觸窗的製作。 圖式簡要說明： 圖一爲本發明實施例中形成淺渠溝隔離及閘極結構的剖 面示意圖。 圖二爲本發明實施例中形成摻雜源極/汲極及一氮化矽 層的#酒示意圖。 圖二爲本發明實施例中回飽刻氮化砂層的剖面示意圖。 圓四爲本發明實施例中沉積硼磷砂玻璃及定義預備開啓 之接觸窗光阻圖案的窗胞示意圖。 圖五爲本發明實施例中第一階段開啓自行對準接觸窗的 剖面示意圖。 圖六爲本發明實施例中第一階段開啓自行對準接觸窗的 本紙狀度適用中國國家標準（CNS>A4規格（21。X 2士公笼) -------1--I--I * 裝·！--- -- 訂------1-^ (請先閱讀背面之沒意事項再填寫本頁) A7 2-淺渠溝隔離 4-複晶矽層 6-氮化矽層 8-摻雜汲極/源極 9b-氮化矽間隙壁 10-硼磷矽玻璃 12a-接觸窗光阻圖案 12c-自行對準接觸窗 4 410 12 B7__ 五、發明說明（t ) 剖面示意圖。 圖七爲本發明實施例中完成自行對準接觸窗插塞製作的 剖面示意圖。 圖號說明： I- 基板 • 3-閘氧化層 5-矽化金屬層 7-複晶矽化金屬閘極結構 9a-氮化矽層 9c-氮化矽薄層 II- 光阻層 12b-自行對準接觸窗 13-接觸窗插塞 發明詳細說明： 以下實施例係一利用兩段式蝕刻方法製作氮化矽間隙 壁，以選擇1 生開啓自行對準接觸窗的製程方法。 首先，請參閱圖一，提供一 P型<100〉基板卜於所述 基板1上製作淺渠溝隔離（Sha 11 ow Trench I so Ut i on; STI) 2，係先利用微影技術定義出淺渠溝（shallow trench)之 光阻圖案，並利用非均向性反應性離子蝕刻法(Reactive Ion Etching; RIE)蝕刻基板1以形成淺渠溝，上述蝕刻係以Cl2 爲蝕刻劑；接著，利用氧電漿灰化法（ashing)及濕式淸洗 將光阻去除，並利用低壓化學氣相沉積法（Low Pressure Chemical Vapor Deposition; LJPCVD)或電發增強式化學氣 ---- I 1 Γ I I--I ------I I ^0 I ------- I (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 4 4.1 ϋ 1 d Α7 _Β7___ — 五、發明說明（&) 相沉積法（Plasma Enhance Chemical Vapor Deposition· PECVD)形成一氧化矽層將所述淺渠溝塡滿；然後，對所述 氧化矽層進行回飽刻處理，係利用化學機械硏磨法(Chem i c a i Mechanical Polishing; CMP)或利用 CHF3 爲触亥_的選擇 性RIE法來去除主動元件區域的氧化矽層，以形成淺渠溝隔 離2。所述淺渠溝隔離2係用來隔絕各主動元件區域，亦可 以熱氧化方式形成的場氧化層（Field Oxide; FOX)來取代 淺渠溝隔離2的製作。 在一含氫氟酸緩衝劑（buffered hydrofluoric acid) 的濕式淸洗之後，於完成淺渠溝隔離2製程之基板1表面上 依序形成一蘭極絕緣層3、一複晶砂層4 —'砍化金屬層 Csilicide) 5及一氮化矽層6，並利用習知的微影及非均 向RIE蝕刻技術，以CF4/CHF3/Ar/02混和氣體爲蝕刻劑蝕刻 氮化矽層6，而以Cl2爲触刻劑蝕刻矽化金屬層（Silicide) 5及複晶砂層4，於所述複層結構上定義出氮化砂層6頂蓋 及複晶砂化金屬（P〇丨ycide)鬧極結構7。所述閘極絕緣層 3係利用熱氧化法形成之二氧化矽層，其厚度介於50A至 200A之間。所述複晶矽層4係利用低壓化學氣相沉積法彤 成，其厚度介於500A至1000A之間。所述砂化金屬層5係 爲砂化鎢或矽化鈦材質，可利用低壓化學氣相沉積法或濺鍍 法（R.F. sputtering)形成，其厚度介於500A至1000A 之間。所述複晶矽層4及矽化金屬層5形成阻値較低的複晶 矽化金屬複層結構可提升閘極結構之導電性。所述氮化矽層 6係利用低壓化學氣相沉積法或電發增強式化學氣相沉積法 ί請先閱讀背面之注意事項再填寫本頁) 裝----——訂------—ί- 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 χ 297公釐） 經濟部智慧財產局員工消費合作社印製 4 41 0 12 A7 ___B7 _ 五、發明說明（/ ) 形成，其厚度介於1000A至2500A之間。 接著，請參閱圖二，利用離子佈植（ion implantation) 方法’以介於20至40 KeV的佈植能量，摻雜砷離子或磷離 子於基板1以形成N型摻雜源極/汲極（source/drain) 8， 得到雜質離子濃度介於1〇12至1〇ΐ4原子/平方公分;再接著， 利用低壓化學氣相沉積法或電紫增強式化學氣相沉積法沉積 一氮化ϊ夕層9a，其厚度介於400A至1000A之間；接下來 是進行本發明的一項關鏈性步驟，請參閱圖三，即利用非均 向RIE蝕刻法，以CHF3/Ar爲蝕刻劑對氮化砂層9a進行部 份回蝕刻，在複晶矽化金屬閘極結構7的側壁可得到氮化砂 層間隙壁％，而在摻雜源極/汲極8、氮化砂層6頂蓋及淺 渠溝隔離2上可得厚度介於ιοοΑ至200λ的剩餘氮化矽薄 層9c。所述氮化矽薄層9c可保護摻雜源極/汲極8，免於被 隨後覆蓋上的硼憐砂玻璃向傾散出之硼或磷植入，造成雜 質離子互補丨賞作用。 再接著’請參閱圖四’利用沉積組成爲3 % ~ 8 % BA 與3 %〜1〇 % P2〇5 (%爲重量百分比）的低壓化學氣相沉 積法或電漿增強式化學氣相沉積法沉積一硼磷砂玻璃1〇 ’ 其厚度介於5k A至l〇k A之間，所述硼磷砂玻璃丨〇亦珂 以一未摻雜矽玻璃（USG)取代；接著，利用化學機械硏磨 法（CMP)對所述硼磷砂玻璃進行平坦化製程；然後，於 所述砸隣砂玻璃10上沉積一光阻層11，利用微影蝕亥[j技術， 定義預備開啓之接觸窗光阻圖案12a，並開啓一自行對準接 觸窗（Self-Aligned Contact; SAC) 12b，再將利用氧電獎 ------- I-----^----- 訂--------_4t (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用t國國家標準（CNS)A4規格（210 441012 A7 ___ B7_____ 五、發明說明（$ ) 灰化法（ash!ng)及濕式淸洗將光阻移除11，所述結構係 如圖五所示。本發明的另一項關鍵性步驟在於本發明利用兩 段式蝕刻開啓自行對準接觸窗，第一步餓刻步驟是利用非均 向RIE蝕刻法，以C4F8/C〇/Ar/02混和氣體爲蝕刻齊晴虫刻硼 磷矽玻璃10，來開啓自行對準接觸窗12b 〇所述鈾刻劑對硼 磷政玻璃10的蝕刻速率約是蝕刻氮化矽層的10 ~ 20倍， 因此可將接觸窗位置之硼磷矽玻璃10完全移除，而且利用 選擇性RIE蝕刻法即使爲了確定完全移除硼磷矽玻璃10， 過度蝕刻也不危及氮化矽薄層9c，而氮化砂薄層9c則可保 護淺渠溝隔離2。 再接著，請參閱圖六，本發明利用兩段式蝕刻開啓自行 對準接觸窗之第二步飽刻步驟是利用非均向RIE触刻法，以 CH2F2/CH3F/Ar/02混和氣體爲鈾刻劑選擇性移除氮化矽薄層 9c，露出接觸窗位置之淺渠溝隔離2及撥雜源極麵8， 形成自行對準接觸窗12c 〇所述餓刻劑對氮化矽層的蝕刻速 率約是蝕刻硼磷砂玻璃10的5 ~ 20倍。自行對準接觸窗12c 係利用兩段式RIE蝕刻，形成氮化矽層間隙壁9b，且不傷 害淺渠溝隔離2及摻雜源極/汲極8，並使讎源極/汲極8 可避免被隨後覆蓋上的硼磷矽玻璃10擴散出之硼或磷植 入，造成雜質離子互補償作用。其中在所述第二步餓刻之前， 先利用離子佈植技術形成重摻雜源極/汲極（Heavily Doped Source/Drain)，以介於40至50 KeV的佈植能量’穿過氮 化矽薄層進行摻雜，摻雜砷離子約1〇14至1〇16原子/平方公 分形成N+區域，摻雜氟化硼（BF2)約1014至1016原子/平方 ^紙張尺度適用中國國家標準（CNS)A4規格（210 2¾公S ) (請先閱讀背面之注意事項再填寫本頁) 裝！ 訂---------垮 經濟部智慧財產局員工消費合作社印製 A7 __B7_ 五、發明說明（I ) 公分:Γ區域。最後，請參閱圖七，沉積一導電材料再利用 Cl2/SF6/BCl3/Ar混合氣體進行RIE回蝕，而形成導電層圖 案，得到大於開啓之自行對準接觸窗12c的接觸窗插塞13， 其厚度介於3k A至6k A之間。所述接觸窗插塞13沉積之 導電材料可爲一金屬、複晶矽或複晶矽化金屬材質，若爲金 屬材質可利用低壓化學氣相沉積法或濺鍍法形成，例如:鎢； 若爲複晶矽或複晶矽化金屬材質可利用低壓化學氣相沉積法 形成，例如：矽化鎢或矽化鈦。 上述說明係以較佳實施例來闡述本發明，而非限制本發 明，並且熟知半導體技藝之人士皆能明瞭，適當而作些微的 改變及調整，仍將不失本發明之要義所在，亦不脫離本發明 之精神和範圍。 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員Η消費合作社印製 本紙張尺度適用中國國家標準（CNS)^4規格（210 X 2$公釐）Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs L ^ 4 1 0 1 p • A7 ____B7____ V. Description of the Invention (/) Technical Field: The present invention relates to a method for manufacturing a self-aligned contact window cSAC of a semiconductor device. In particular, it relates to a method for manufacturing an insulating spacer on a sidewall of a gate structure. Background of the Invention: As semiconductor devices enter the sub-micron process, the performance of the devices is improved and the production costs of the devices are reduced. The development of the semiconductor industry has also continued to work towards improving performance and reducing costs. Semiconductor devices made with sub-micron technology can reduce the defect rate of capacitance and resistance. In addition, since sub-micron processes provide smaller semiconductor chips, more wafers can be obtained on a single wafer substrate, which reduces the number of wafers. Production cost per wafer. The lithography and dry etching technology in the semiconductor process are the main contributors in the development of miniaturization. For example, more complex exposure equipment and the use of more sensitive photosensitive materials will allow sub-micron circuit patterns to be developed in gm. Layer, and the better dry etching method can successfully transfer the photoresist pattern to the underlying structure. In addition, the special design of semiconductor processes, such as the application of self-aligned contact windows (SAC), can also develop smaller and faster semiconductor components. Self-aligning contact window refers to opening a contact window hole and exposing the doped source / drain between the gate structures. In order to maintain a minimum gap between the gate structures and enable self-alignment of the contact window structure, Above the doped source / drain regions, it is necessary to provide smaller contact window holes than can be provided by today's lithography technology. So the idea of self-aligning the contact window is applied. First, open a hole larger than the gate structure spacing 'and expose the doped source / drain _____ 2 ------ This paper size applies to Chinese national standards (CNS ) A4 size (210 X 297 mm) — IHIIKI — ^ I · IEII 1 · 1 I-SJ ^ III— n III (Please read the notes on the back before filling this page) System A7 __B7_ V. Description of the Invention ()) The top of the gate structure in the region and part is like a silicon nitride spacer on the side wall of the gate structure, and the gate structure also has a silicon nitride top layer. Subsequently, the conductive layer is deposited to form a conductive layer contact window plug that is larger than the opened self-aligned contact window radius, so that the conductive layer can contact the doped source / drain electrode under the self-aligned contact window. In general, the self-aligned contact window is opened in an insulating layer, which is usually a borophospho sand glass, and the borophospho glass is often deposited after forming a barrier wall and directly covered in the doped Above the hetero-source / drain region, using this process step will cause doped boron or phosphorus ions in the boron-phosphorus-chopped glass to enter the doped source / drain region due to outward diffusion, resulting in unnecessary ion interactions. Compensation effect; In addition, the non-uniform RIE etching method used when opening the self-aligning contact window also removes the oxidized sand isolation area at the end of the etchable or transitional etching. The invention discloses a manufacturing method capable of opening a self-aligned contact window without causing impurities of the doped source / drain to be re-implanted with impurities, and without harming the silicon oxide isolation region. According to the present invention, a part of the silicon nitride spacer wall and a thin silicon nitride layer on the doped source / drain between the gate structures are manufactured. The silicon nitride thin layer can protect the doped source / drain. Free from the implantation of boron or phosphorus diffused by the covered borophosphosilicate glass. The invention also uses a two-stage etching method to open the self-aligned contact window. In the first step, the etching rate of borophosphosilicate glass is greater than that of the silicon nitride etchant, and the RIE etching reaction is terminated at the silicon nitride thin layer. Next, in the second step, a thin layer of nitrided sand is removed by using an etchant that etches silicon nitride faster than silicon oxide. U.S. Patent No. 5643824 discloses the use of silicon nitride extension to avoid field beak (FieldOxide; FOX) region bird beak phenomenon, but the previous invention does not apply this paper standard to Chinese national standards ( CNS) A4 specification (21〇X 297 public love) I ϊ ---- r --- II Packing ----- Order --------- Blow & Please read the precautions on the back first (Fill in this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 41 u 1 2 A7 _________B7 _ V. Description of the Invention (^) The doped source / drain region is covered with a thin layer of silicon nitride, and neither is used. A segmented non-uniform RIE etch method selectively removes a thin layer of nitrided sand to open a self-aligning contact window. Description of the invention: The main purpose of the present invention is to make a self-aligned contact window of a metal oxide semiconductor field effect transistor (MOSFET). Another object of the present invention is to fabricate a part of the silicon nitride gap on the sidewall of the gate structure, and to leave a thin layer of nitrided sand on the doped source / drain between the gate structures. Another object of the present invention is to open a self-aligning contact window in borosilicate glass (BPSG), and use anisotropic RIE to select the etching rate of borophosphosilicate glass (BPSG) than the etching of saturated silicon nitride. Agent to stop the full-saturated reaction on a thin layer of silicon nitride. Yet another object of the present invention is to produce a complete self-aligned contact window. The non-uniform RIE method is used to etch a thin layer of silicon nitride, and the selective etching rate of silicon nitride is greater than that of etched borophosphosilicate glass or silicon oxide. The doped source / drain between the gate structures is exposed. The method for manufacturing a self-aligned contact window structure of the present invention uses a two-stage non-unidirectional RIE etching method to fabricate a part of the silicon nitride spacer wall. This design can protect the doped source / drain and the isolation region and prevent it. Affected by the material of the superstructure and avoiding damage caused by over-etching. In order to achieve the above-mentioned objects, the present invention uses the following methods: First, a semiconductor substrate is provided, in which a doped source / drain is located in a substrate between two gate structures, and the gate structure is ______ 4-- — This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) --- i ------- IHI! ^ ------- i Order ------ t ! Line (please read the precautions on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs: .4 4 1 CM 2 A7 —______ B7 ____—- 5. Description of the invention (if) is located on the gate insulation layer Or on the isolation area; then, a nitrided sand layer is deposited and partially etched back using the heterogeneous RIE saturation etching method, leaving a thin layer of silicon nitride on the doped source / drain between the gate structures, and A silicon nitride layer spacer is formed on the side wall of the gate structure. Next, a boron scale glass is deposited, and the photolithography technique and anisotropic RIE are used to etch the self-aligned contact window in the first stage. This step It is selected to etch boron-phosphorus political glass at a rate faster than that of silicon nitride, and the etching reaction will stop at the thickness of silicon nitride. Layer; then, remove the photoresist and open the self-aligned contact window in the second stage. This step is to select an etchant that etches silicon nitride faster than etched borophosphate sand glass or silicon oxide, and gate structure The thin inter-silicon nitride layer is removed to expose the doped source / drain region. Finally, a metal or polycrystalline silicon material is deposited and formed in contact with the doped source / drain in the self-aligned contact window. The conductive layer pattern is completed to make the self-aligned contact window. Brief description of the drawings: FIG. 1 is a schematic cross-sectional view of forming a shallow trench isolation and gate structure in an embodiment of the present invention. FIG. 2 is a schematic diagram of a doped source / drain and a silicon nitride layer formed in an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view of a back-saturated nitrided sand layer in an embodiment of the present invention. Circle 4 is a schematic diagram of window cells for depositing borophosphate sand glass and defining a photoresist pattern of a contact window to be opened in the embodiment of the present invention. FIG. 5 is a schematic cross-sectional view of opening a self-aligning contact window in a first stage in an embodiment of the present invention. Figure 6 shows the paper-like degree of opening the self-aligning contact window in the first stage of the embodiment of the present invention, which is applicable to the Chinese national standard (CNS > A4 specification (21. X 2 taxi cage)) -------- 1--I --I * Installation ·! ----Order ------ 1- ^ (Please read the unintentional matter on the back before filling this page) A7 2-Shallow trench isolation 4-Multicrystalline silicon layer 6 -Silicon nitride layer 8-doped drain / source 9b-silicon nitride spacer 10-borophosphosilicate glass 12a-contact window photoresist pattern 12c-self-aligned contact window 4 410 12 B7__ 5. Description of the invention ( t) Schematic cross-section. Figure 7 is a schematic cross-sectional view of the self-aligned contact window plug in the embodiment of the present invention. Drawing number description: I- substrate • 3-gate oxide layer 5-silicide metal layer 7-polycrystalline silicide metal Gate structure 9a-silicon nitride layer 9c-silicon nitride thin layer II-photoresist layer 12b-self-aligned contact window 13-contact window plug Detailed description of the invention: The following embodiments are fabricated using a two-stage etching method The silicon nitride spacer wall is used to select a manufacturing method for opening the self-aligned contact window. First, referring to FIG. 1, a P-type < 100> substrate is provided on the substrate 1. Trench Isolation (Sha 11 ow Trench I so Ut i on; STI) 2 is to first define the photoresist pattern of shallow trenches by lithography technology, and use the anisotropic reactive ion etching method (Reactive (Ion Etching; RIE) etching the substrate 1 to form a shallow trench. The above etching uses Cl2 as an etchant; then, the photoresist is removed by an oxygen plasma ashing method and wet cleaning, and a low-pressure chemical gas is used. Phase deposition (Low Pressure Chemical Vapor Deposition; LJPCVD) or electro-enhanced chemical gas ---- I 1 Γ I I--I ------ II ^ 0 I ------- I ( Please read the notes on the back before filling out this page) Printed on the paper by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, the paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 4 4.1 ϋ 1 d Α7 _Β7 ___ — 5 2. Description of the invention (&) Plasma Enhance Chemical Vapor Deposition · PECVD forms a silicon oxide layer to fill the shallow trenches; then, the silicon oxide layer is subjected to back-saturation and etch treatment, which uses chemical Mechanical Honing (Chem icai Mechanical Polishing; CMP) or CHF3 Hai _ touch selection of a silicon oxide layer is removed by RIE active device region to form a shallow trench isolation 2. The shallow trench isolation 2 is used to isolate each active device region, and a field oxide layer (Field Oxide; FOX) formed by thermal oxidation may be used instead of the production of the shallow trench isolation 2. After the wet cleaning with a buffered hydrofluoric acid, a blue electrode insulation layer 3 and a polycrystalline sand layer 4 are sequentially formed on the surface of the substrate 1 after the shallow trench isolation 2 process is completed. Csilicide) 5 and a silicon nitride layer 6 are etched, and the silicon nitride layer 6 is etched with a CF4 / CHF3 / Ar / 02 mixed gas as an etchant using a conventional lithography and anisotropic RIE etching technology. Cl2 is used as the etchant to etch the silicide metal layer 5 and the polycrystalline sand layer 4. The nitrided sand layer 6 cap and the polycrystalline sanded metal (Polycide) anode are defined on the multilayer structure. Structure 7. The gate insulating layer 3 is a silicon dioxide layer formed by a thermal oxidation method, and has a thickness between 50A and 200A. The polycrystalline silicon layer 4 is formed by a low pressure chemical vapor deposition method and has a thickness between 500A and 1000A. The sanded metal layer 5 is made of sanded tungsten or titanium silicide, and can be formed by a low pressure chemical vapor deposition method or a sputtering method (R.F. sputtering), and has a thickness between 500A and 1000A. The polycrystalline silicon layer 4 and the silicided metal layer 5 form a polycrystalline silicon silicided multi-layer structure with low resistance, which can improve the conductivity of the gate structure. The silicon nitride layer 6 is a low pressure chemical vapor deposition method or an electro-enhanced chemical vapor deposition method. (Please read the precautions on the back before filling this page.) --- ί- Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economy Printed on a paper size applicable to the Chinese National Standard (CNS) A4 (210 x 297 mm) Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 4 41 0 12 A7 ___B7 _ V. Description of the invention (/) is formed, and its thickness is between 1000A and 2500A. Next, please refer to FIG. 2, using an ion implantation method to dope an arsenic ion or a phosphorus ion onto the substrate 1 with an implantation energy between 20 and 40 KeV to form an N-type doped source / drain. (Source / drain) 8 to obtain a concentration of impurity ions between 1012 and 10 4 atom / cm 2; and then, a low pressure chemical vapor deposition method or an electro-violet enhanced chemical vapor deposition method is used to deposit thorium nitride. The evening layer 9a has a thickness between 400A and 1000A. The next step is to perform a chain-linking step of the present invention. Please refer to FIG. 3, which uses anisotropic RIE etching method and uses CHF3 / Ar as an etchant pair. The nitrided sand layer 9a is partially etched back, and the nitrided sand layer gap wall% can be obtained on the side wall of the polycrystalline silicon silicide gate structure 7, while the doped source / drain 8, the nitrided sand layer 6 top cover and the shallow channel can be obtained. On the trench isolation 2, a residual silicon nitride thin layer 9c having a thickness ranging from ιοο to 200λ can be obtained. The silicon nitride thin layer 9c can protect the doped source / drain electrode 8 from implantation of boron or phosphorus poured out by the borax glass which is subsequently covered, resulting in complementary ion ions. Then, please refer to FIG. 4 using a low pressure chemical vapor deposition method or a plasma enhanced chemical vapor deposition method using a deposition composition of 3% to 8% BA and 3% to 10% P205 (% is a weight percentage). A borophosphosilicate glass 10 ′ is deposited by a method with a thickness between 5k A and 10k A. The borophosphosilicate glass is replaced by an undoped silica glass (USG); A mechanical honing method (CMP) performs a planarization process on the borophosphate sand glass; then, a photoresist layer 11 is deposited on the adjacent sand glass 10, and a lithography etching method is used to define a ready-to-open The contact window photoresist pattern 12a, and a self-aligned contact (SAC) 12b is opened, and then the oxygen electricity award will be used --------- I ----- ^ ----- Order --------_ 4t (Please read the precautions on the back before filling this page) This paper size is applicable to the national standard (CNS) A4 specification (210 441012 A7 ___ B7_____ 5.) Description of the invention ($) Gray Ash! Ng and wet scrubbing remove the photoresist 11 and the structure is shown in Figure 5. Another key step of the present invention is that the present invention utilizes two-stage etching The self-aligning contact window is opened. The first step is to use a non-unidirectional RIE etching method to etch a borophosphosilicate glass 10 with a mixed gas of C4F8 / C〇 / Ar / 02. The etch rate of the boron-phosphorus political glass 10 by the uranium etching agent in the quasi-contact window 12b is about 10 to 20 times that of the silicon nitride layer. Therefore, the borophosphosilicate glass 10 at the contact window position can be completely removed, and the The selective RIE etch method does not jeopardize the thin silicon nitride layer 9c, even to confirm the complete removal of the borophosphosilicate glass 10, and the thin nitrided sand layer 9c protects the shallow trench isolation 2. Then, please refer to Fig. 6. In the present invention, the second step of the self-aligning contact window is opened by using two-stage etching. The non-uniform RIE touch-etching method is used to selectively move the CH2F2 / CH3F / Ar / 02 mixed gas as a uranium etching agent. In addition to the silicon nitride thin layer 9c, the shallow trench isolation 2 and the impurity source surface 8 where the contact window is exposed form a self-aligned contact window 12c. The etching rate of the silicon nitride layer by the above-mentioned etching agent is about an etch 5-20 times of borophosphate glass 10. Self-aligned contact window 12c is etched by two-stage RIE. Forming a silicon nitride layer spacer 9b without harming the shallow trench isolation 2 and the doped source / drain electrode 8 and preventing the erbium source / drain electrode 8 from being diffused by the borophosphosilicate glass 10 subsequently covered The implantation of boron or phosphorus causes mutual compensation of impurity ions. Before the second step, a heavily doped source / drain is formed using ion implantation technology to introduce Doped through a thin layer of silicon nitride at a implantation energy of 40 to 50 KeV, doped with arsenic ions at about 1014 to 1016 atoms / cm2 to form N + regions, and doped with boron fluoride (BF2) for about 1014 to 1016 atoms / square ^ Paper size is applicable to Chinese National Standard (CNS) A4 specifications (210 2¾mm S) (Please read the precautions on the back before filling this page) Install! Order --------- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 __B7_ V. Invention Description (I) cm: Γ area. Finally, referring to FIG. 7, a conductive material is deposited and then RIE etched back using a Cl2 / SF6 / BCl3 / Ar mixed gas to form a conductive layer pattern to obtain a contact window plug 13 larger than the opened self-aligned contact window 12c. Its thickness is between 3k A and 6k A. The conductive material deposited by the contact window plug 13 may be a metal, polycrystalline silicon, or polycrystalline silicided metal. If it is a metal material, it may be formed by a low-pressure chemical vapor deposition method or a sputtering method, such as tungsten; if it is Polycrystalline silicon or polysilicon silicide metal materials can be formed using low pressure chemical vapor deposition methods, such as tungsten silicide or titanium silicide. The above description is to illustrate the present invention with a preferred embodiment, but not to limit the present invention. Those skilled in the art of semiconductors can understand that making appropriate changes and adjustments will still not lose the essence of the present invention. Depart from the spirit and scope of the present invention. (Please read the precautions on the back before filling out this page) Printed by a member of the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives This paper is sized for the Chinese National Standard (CNS) ^ 4 (210 X 2 $ mm)