399502 A7 B7 五、發明説明（1 ) 第84 1 1 1450號專利申請案 說明書修正頁 修正日期：85年12月 經濟部中央標準局貝工消費合作社印製 趟昍铕域 本發明是關於一層薄膜電晶體的活性層•及其製造方 法，特別是一種非晶賭式的矽晶層。逭種矽晶曆分為一種 具有較佳電氣特性的细密型非晶體式矽晶層，以及一種具 有較佳物理和機械特性的粗槠型非晶體式矽晶層。如此配 製好的矽晶層會在提高工作速度，附著性，和沈稹速率時 •減少黏著時間。 習知持術描沭 在當今這種圖像資訊的時代裡，那些在顯示器，特別 是用於取代陰極射線管之平面型顯示器的領域中所採用的 技術·已被發展出來，而且大量地使用。 在諸平面顯示器中•當被一積體電路所驅動時•液晶 顯示器便顯現出其特色在於具有因為緊密的設計，便宜的 價格•以及低的功率消耗所造成良好的應用性*並且因此 而被廣泛應用於膝上型電腦，口袋型電腦•汽車，和彩色 電視。 參考第1圖•所顯示的是一涸在傅統式液晶顯示器中 的反向交錯型薄膜電晶體（TFT)基座，包括閘極金颺層1 * 一層閘極絕緣非晶體式氮晶層2 · —層非晶體式矽晶層 3 ·-層作為源一汲電極之歐姆性接觸層型非晶體式 砂晶層4，一廇源一汲金属電極5，一餍保護層6，陽極 絕緣層7，Μ及一層基座8。 在第2圖中所說明的是由2到4之三層連鑲層的結構 °該閘極絕緣非晶賭式氮薄膜2的厚度大約為3000埃，而 本紙張尺度適用中國國家標準（CNS ) Α4規格（2ΐ〇χ297公釐） (請先聞讀背面之注意事項再填寫本頁) ’秦· Γ Ί 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（2 ) 該非晶體式矽晶層3的厚度大約爲2000埃，以及該η型非 晶體式矽晶層4的厚度為500埃。在一般藉由等離子強化 化學汽相沈積法（CVD)，在該薄膜霣晶鱺（TFT)基座8上所 連續沈積而成的2到4晶層中，該非晶《式矽晶層3是會 在形成一條薄膜《晶體（TFT>通道時彩街該元件待性的晶 層，並且會具有較佳的光m和物理特性。一般而言，為一 棰薄膜霣晶體（TFT〉成分的非晶龌式矽晶層3，應具有較 佳的霣氣特性，來被用作在一值液晶顯示器（LCD〉中的閭 Μ要素。至於逭些決定置氫特法的要，有光和暗傅導靈 、敏度，一，以及光能量頻帶間隙，其中：該光和 --------··------ - - 1 \ * 暗傳導茧敏度，就是眾所周知的一種有效評估方式h該@ 和暗傳導靈敏度表示為一棰在非晶龌式矽薄膜上之暗處所 測量的傅導率，Μ及在該菲晶鞲式矽薄膜上，亮度為1200399502 A7 B7 V. Description of Invention (1) No. 84 1 1 1450 Patent Application Specification Amendment Page Amendment Date: December 1985 Printed by the Central Bureau of Standards of the Ministry of Economic Affairs of Beigong Consumer Cooperatives. This invention is about a thin film. Active layer of transistors and its manufacturing method, especially an amorphous silicon crystal layer. The silicon crystals are divided into a fine amorphous silicon layer with better electrical characteristics and a coarse amorphous silicon layer with better physical and mechanical properties. The silicon crystal layer prepared in this way will improve the working speed, adhesion, and Shen Zhen rate. • Reduce the adhesion time. In the current era of image information, those technologies used in the field of displays, especially flat panel displays used to replace cathode ray tubes, have been developed and used in large quantities . Among flat panel displays • When driven by an integrated circuit • The liquid crystal display is characterized by its compact design, cheap price • Low power consumption and good applicability * and therefore Widely used in laptops, pocket computers, automobiles, and color TVs. Refer to Figure 1 • Shown is a reverse staggered thin film transistor (TFT) base in a conventional liquid crystal display, including a gate gold layer 1 * a gate insulating amorphous nitrogen crystal layer 2 ·-Amorphous silicon crystal layer 3 ·-An ohmic contact layer type amorphous sand crystal layer 4 as a source-drain electrode, a source-drain metal electrode 5, a protective layer 6, anode insulation Layer 7, Μ and a layer of base 8. The structure shown in Figure 2 is composed of three layers of 2 to 4 °. The thickness of the gate insulating amorphous nitrogen film 2 is about 3000 angstroms, and this paper scale is applicable to the Chinese National Standard (CNS ) Α4 specification (2 ΙΟχ297 mm) (please read the precautions on the back and then fill in this page) 'Qin · Γ Ί Printed A7 B7 by Employee Consumer Cooperative of Central Bureau of Standards, Ministry of Economic Affairs V. Invention description (2) The amorphous The thickness of the silicon layer 3 is about 2000 angstroms, and the thickness of the n-type amorphous silicon layer 4 is 500 angstroms. In the 2 to 4 crystal layers that are generally deposited on the thin-film TFT base 8 by plasma enhanced chemical vapor deposition (CVD), the amorphous silicon crystal layer 3 is Will form a thin film "crystal (TFT> channel) when the crystal layer of the device is ready, and will have better optical properties and physical properties. In general, it is a non-crystalline thin film (TFT) component The crystalline silicon layer 3 should have better gas characteristics and be used as a luminous element in a one-value liquid crystal display (LCD). As for some of the factors that determine the hydrogen placement method, there are light and dark Fu Daoling, sensitivity, one, and light energy band gap, where: the light and -------- ·· --------1 \ * dark conduction cocoon sensitivity is well known An effective evaluation method h The @ and dark conduction sensitivity are expressed as a measured conductivity in the dark on the amorphous silicon thin film, Μ and on the phenanthrene silicon thin film, the brightness is 1200
Cd/Β»處所測量的傅導率之間的比值。 .......... \ 該傅導率可藉由下列的公式來測量。 W ai 傳導率==-X t X - L σν 在逭項公式中，σ是一個非阻抗性的比值，w是通道 寬度，L是通道長度，σν是一値量測昀霣壓值，以及σ i 是一傾量測的《流值。 至於該薄膜«晶體（TFT)成分會有一棰檯定之霣氣特 性在其中的該光和暗傳導靈敏度值，應在106以上，而傳 特非晶«式矽晶層則是藉由化學汽相沈積法*以一棰70-500埃/每分鏟之低沈積速率的單一速率而形成。 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） ---------^-Iγ 衮------訂一-----^ (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局負工消費合作社印製 A7 _B7_ 五、發明説明（3 ) 因此，對習知技術结構和製造方法而言，在該非晶黼 式矽晶層的形成過程中，有些缺點，其中，該非晶鱧式矽 晶層的物理和機械特性之所以惡化，是由於在#離子環 境中遷移的离度矽烷 形成，以及與籍由化學汽相沈積法而形成之非晶鱷式矽晶 層相比，所得到大約150-1000埃/每分鳙的高沈稹速率。 而且因為習知技術的非晶駸式矽晶層的沈積時間，會比用 該«薄膜或一種η型非晶《式矽晶層爲長*而形成該矽晶 層，在一種嫌機式结構的密室中，是一値瓶頸，並且會導 致一段長的作用時間。 因此*假如該非晶醱式矽晶層利用化學汽相沈積法， 而以一種150-1000埃/每分鐘的高沈積速率成形的話，該 矽晶層就能夠藉由減少作用時間，而解決習知技術的問題 ，然而*並無法如同一傾薄膜電晶體（TFT)成分般地完全 地工作*因爲該光和暗傳導靈敏度潙1〇4-1〇»，而且因此 如薄膜電晶醴矽晶層般的電氣特性會不夠好。 發明描要 本發明的一項目的》就是要解決上述已確認的問題》 Μ及提供一棰具有一活性層的薄膜11晶醱。 實際上，由於該非晶醱式矽晶層的一條載子所通過的 通道是該絕緒層和該非晶體式矽晶層的一條介面，在分為 一棰藉由以低沈積速率之化學汽相沈積法（CVD〉所形成而 具有較佳®氣特性的非晶鱧式矽晶層，Μ及一棰藉由以高 沈積速率之化學汽相沈積法（CVD)所形成而具有較佳物理 本紙張尺度適用中國國家標準（CNS > Α4規格（210X297公釐） 6 (請先閲讀背面之注意事項再填寫本頁) '衣· 訂ί 經濟部中央揉準局員工消费合作社印製 A7 _ _B7_ 五、發明説明（4 ) 和機械特性的非晶體式矽晶層之後，可採用沈積的製造方 法，所以提供了能夠滅少作用時間，及具有不會劣化之« 氣或物理和機械特性，以及具有一棰與習知技術相比，只 在於以低沈積速率或高沈積速率形成之附著性的薄膜霣晶 黼（TFT)基座。 爲了要達成該目的。本發明包含一種具有較佳的霄氣 特性，而在該閘«極和該閘極絕鐮層上，以低沈積速率形 成的細密型非晶醱式矽副層，以及一棰具有較佳的物理和 機械特性，而在該閘電極和該閘極絕緣層上，以高沈積速 率形成的粗楢型非晶醱式矽副層。 為了要達成該目的》本發明所用方法的較佳實施例， 包含在該Μ棰氮薄膜的介面上沈積一層細密型霣氣副層的 一些步篇；採取在該閘霣極和閘極絕嫌層上*用低沈積速 率的化學汽相沈稹法（CVD)，並且沈積一層薄的粗糙型物 理層*而為一棰非晶«式矽晶層的第一副層；採取在該細 密型非晶龌式矽晶層上*用高沈積速率的化學汽相沈積法 (CVD)，而也是一種非晶釀式矽晶層的第二副層。 本發明的另一個實施例，包含一種在該基座上所形成 的輕度截止型薄腰；一1在那上面所形成的絕緣層；Μ— 段間距配置在該絕緣層上的一層源霣棰和一層汲霄極；以 一段間距配置在該源霣極和汲霣極上的二層歃姆性接觸層 ;範画從覆蓋該源霣極之歐姆性接觸層的一部分到覆蓋該 汲霣極之另一備歐姆性接觸層的一部分，而Μ高沈積速率 形成的一層粗糙型非晶鼸式矽晶層；Μ低沈積速率形成的 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X 297公釐） I-------「装-------訂------^ (請先閲讀背面之注意事項再填寫本頁) 經濟部中央樣準局員工消费合作社印裝 A7 _B7_ 五、發明説明（5 ) 一層細密型非晶體式矽晶層；一層在該細密型非晶驩式矽 晶靥上所形成的閛極絕鐮層；Μ及一層在該薄謨霣晶驩（ TFT)頂端上所形成的閛極。 附BI ：> AM术 第1鼸是一傾習知技術之薄膜霣晶髏基座的横截面圔 » 第2_是一個習知技術之薄膜霣晶鼸基座三晶層的大 刻度圖形； 第3圖是一傾類似第2圔的函形，但是其構造卻是把 該非晶黼式矽晶層分成二層連繙的沈積副層，根據本發明 的較佳實施例*採用不同的技術而被沈積而成：以及 第4画是一館說明等離子化學長晶法之資施例的方塊 ，該方法是根據本發明的一傾較佳實施例，利用一種為 了薄膜霣晶齷基座而作為雙層非晶體式矽晶《的化學汽相 沈稹法；Μ及 第5圖是一儸根據本發明較佳實施例的頂纗閘極型薄 膜霣晶體（TFT)成分實施例的播截面圈。 酧佯奮渝俐：> 註沭 除了逭裡所描述的之外，一種加入根據本發明之活性 非晶醱式矽晶«的薄膜霣晶釀可Μ被製造出來*而且會附 上相閫的描述。 如同在第3圖中所說明的一般，一層根據本發明的較 佳實施例，而在該薄膜霣晶驩（TFT)基底上的活性非晶髓 式矽晶層》，可Μ如下述般的方式被製造出來，示邸把本身 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ 297公釐） 8 --------:---^ ^-- (請先閲讀背面之注意事項再填寫本頁) 訂The ratio between the measured Fourier Conductivity at Cd / B ». .......... The Fourier conductivity can be measured by the following formula. W ai conductivity ==-X t X-L σν In the formula for the term, σ is a non-impedance ratio, w is the channel width, L is the channel length, and σν is a value for measuring the initial pressure, and σ i is the "flow value" measured by one tilt. As for the thin film «crystalline (TFT) component, the light and dark conduction sensitivity values in which the gas characteristics of a thin film will be set should be above 106, while the crystalline silicon layer of the special amorphous« type is formed by the chemical vapor phase The deposition method * is formed at a single rate with a low deposition rate of 70-500 Angstroms per minute. The paper size is applicable to China National Standard (CNS) Α4 specification (210X297mm) --------- ^-Iγ 衮 ------ set one ----- ^ (please read the back (Notes to fill out this page) A7 _B7_ printed by the Consumer Labor Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs V. Description of the invention (3) Therefore, for the conventional technical structure and manufacturing method, the formation of the amorphous silicon type silicon crystal layer During the process, there are some shortcomings. Among them, the physical and mechanical properties of the amorphous silicon crystal layer are deteriorated due to the formation of ionized silane migrated in the # ion environment and the chemical vapor deposition method. Compared with the amorphous crocodile type silicon crystal layer, the high sinking rate of about 150-1000 Angstroms / min. And because the deposition time of the amorphous thorium-type silicon crystal layer of the conventional technology is longer than that of using the «thin film or an n-type amorphous silicon crystal layer *, the silicon crystal layer is formed in a quasi-organic structure Is a bottleneck in the back room, and will cause a long period of action. Therefore, if the amorphous silicon layer is formed by chemical vapor deposition and is formed at a high deposition rate of 150-1000 Angstroms per minute, the silicon layer can solve the conventional problem by reducing the action time Technical issues, however * does not work as fully as the same tilted thin film transistor (TFT) component * because the light and dark conduction sensitivities are 10-14.0 », and therefore as thin film transistors General electrical characteristics will not be good enough. SUMMARY OF THE INVENTION An object of the present invention is to solve the above-identified problems and to provide a thin film 11 with an active layer. In fact, since the channel through which a carrier of the amorphous crystalline silicon layer passes is an interface between the steric layer and the amorphous crystalline silicon layer, it is divided into one by a chemical vapor phase with a low deposition rate Amorphous silicon crystal layer with better gas characteristics formed by deposition method (CVD), M and Yi are formed by chemical vapor deposition method (CVD) with high deposition rate and have better physical cost The paper standard is applicable to the Chinese National Standard (CNS> Α4 specification (210X297mm) 6 (Please read the precautions on the back before filling in this page) 'Clothing and Ordering A7 _ _B7_ Printed by the Employee Consumer Cooperative of the Central Bureau of Economic Development of the Ministry of Economic Affairs Fifth, the invention description (4) and the mechanical properties of the amorphous silicon crystal layer can be deposited using manufacturing methods, so it can provide less extinction time, and has no deterioration «gas or physical and mechanical properties, and Compared with the conventional technology, it only has the adhesion of a thin film 難 晶 黼 (TFT) base formed at a low deposition rate or a high deposition rate. In order to achieve this goal, the present invention includes a device Gas , And on the gate electrode and the gate insulation layer, a fine amorphous silicon sub-layer formed at a low deposition rate, and a small one has better physical and mechanical properties, and the gate electrode and On the gate insulating layer, a coarse crystalline amorphous silicon sub-layer formed at a high deposition rate. In order to achieve the objective, a preferred embodiment of the method used in the present invention is included on the interface of the M-nitrogen thin film Some steps of depositing a fine-layered sub-layer of gas; take it on the gate electrode and the gate insulation layer * Use a low deposition rate chemical vapor deposition method (CVD), and deposit a thin layer of rough physical layer * It is the first sub-layer of a non-crystalline «type silicon crystal layer; it is taken on the dense amorphous silicon layer * using a high deposition rate chemical vapor deposition method (CVD), which is also an amorphous The second sub-layer of the brewing silicon crystal layer. Another embodiment of the present invention includes a light cut-off thin waist formed on the base; an insulating layer formed thereon; M- segment A layer of source chirp and a layer of dip pole arranged on the insulating layer at intervals; From the two layers of ohmic contact layers arranged on the source electrode and the drain electrode; the range from the part of the ohmic contact layer covering the source electrode to the other ohmic contact layer covering the drain electrode One part, and a layer of rough amorphous silicon crystal layer formed by M high deposition rate; the paper scale formed by M low deposition rate is applicable to China National Standard (CNS) Α4 specification (210X 297 mm) I ----- -"Packing ------- order ------ ^ (please read the precautions on the back before filling in this page) A7 _B7_ printed by the Central Sample Bureau of the Ministry of Economic Affairs Employee Consumer Cooperative V. Description of invention ( 5) A layer of fine amorphous silicon crystal layer; a layer of extreme sickle formed on the fine amorphous silicon crystal; Μ and a layer on the top of the thin TFT The formed poles. Attached to BI: > AM technique 1st mule is a cross-section of a thin-film epimedium base with a known technique »No. 2_ is a large-scale graph of a three-crystal layer of a thin-film epimedium base with a known technique Figure 3 is a function similar to the second one, but its structure is to divide the amorphous silicon layer into two successive deposition sub-layers, according to the preferred embodiment of the present invention * using different The technology is deposited: and the fourth picture is a block showing an example of the plasma chemical growth method, the method is according to a preferred embodiment of the present invention, using a kind of thin film 銣 晶 龌 susceptor And as a double-layer amorphous silicon crystal, the chemical vapor deposition method; M and FIG. 5 are a cross section of a top gate type thin-film thin-film crystal (TFT) component embodiment according to a preferred embodiment of the present invention . Yu Feifen Yuli: > In addition to what is described in Yuri, a thin-film 魣 晶 酒 added with the active amorphous silicon crystal according to the present invention can be manufactured * and will be attached description of. As illustrated in FIG. 3, a layer according to the preferred embodiment of the present invention, and the active amorphous silicon layer on the thin film TFT substrate (TFT) substrate can be as follows The method was manufactured, and Shidi applied its own paper standards to the Chinese National Standard (CNS) Α4 specifications (210Χ 297 mm) 8 --------: --- ^ ^-(please read the back page first Matters needing attention before filling this page)
A BA B
經濟部中央梯準局員工消費合作社印装 五、發明説明（6 ) 為具有優異物理和機械特性的非晶體式矽晶層，而以高沈 積速率被沈積而成的粗槠型非晶體式矽晶層31，配置在本 身為具有良好電氣特性的非晶體式矽晶層，而Μ低沈積速 率被沈積而成的佃密型非晶體式矽晶層3 2之上。 上述的细密型非晶體式矽晶層表示，該晶層的光和暗 傳導《敏度為106 *並且該晶層Μ大約70-500埃/每分鐘 的沈積速率而被沈積。同時該粗槠型非晶體式矽晶層表示 ，該晶層的光和暗傅導S敏度為104-10β*並且該晶層Μ 大約1 50- 1 500埃/每分鐘的沈積速率而被沈積，超過使用 化學汽相沈積法（CVD)之细密型非晶髖式矽晶層的沈稹速 率。 在Μ上的描述中，之所Μ重覆該粗槠型和該细密型非 晶體式矽晶層沈積速率範圍的理由，是為了考慮構造上的 差異· Μ及為了得到上述光和暗傳導灌敏度的一般值，並 且因此在某些方面•限制了本發明的想法。 一個根據本發明的較佳實施例，而具有一活性層之薄 膜電晶體（TFT)的製造方法，將被描述如下。 根據一個液晶顯示器（LVD)的薄膜電晶體（TFT)之製 造過程，本身為一層閘電極之活性曆的非晶體式矽晶層， 可Μ用下列的方式被製造出來，亦即把以大約7(1-5(30埃/ 每分鐘的低沈積速率沈積到厚度為50-500埃來成形，而具 有較佳電氣特性的细密型非晶體式矽晶層32，Μ及Μ大約 1 50-1 OQQ埃/每分鐘的高沈積速率沈積到厚度為1000-1500 埃來成肜，而具有較佳物理和機械特性的粗槠型非晶體式 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） I I I I I I I I 裝— I I 1 I I 訂— —線 (請先閲讀背面之注意事項再填寫本f ) 經濟部中央橾準局貝工消費合作社印製 399502_B7_ 五、發明説明（7 ) 矽晶層31，沈積到在作爲蘭極絕緣層的非晶Η式《晶層2 之上。該非晶醱式矽晶層的沈積遇程是在H»+SiH*的氫化 非晶鼸式矽晶的環塊中進行。 如同在第4 _中所說明的一般，用於薄膜«晶釀（TFT) 基座的雙重副層非晶黼式矽晶層是Μ下列的方式所製成， 亦邸把本身爲Μ离沈稹速率成形之非晶鼸式矽晶層，而具 有良好物理和機械特性的粗糖型非晶覼式矽晶層31*配置 在本身爲以低沈積速率成形之非晶饈式矽晶層，而f有良 好«氣特性的細密型非晶釀式矽晶層32之上。由於該非晶 體式矽晶層被分成一種雙重副層的構逭，並且因此而減少 作用時間，以及提高作用速度，附着性，和沈積速率。 而且作為該源極和汲搔之歐姆性接觸層的粗糙型矽晶 層，被用來蝕刻，逭是由於當η型非晶饑式矽晶層，在如 第1圃中所說明之源極和汲型定型過程中被定型之後，再 被蝕刻時，並無法如一條寅際通道般地蓮作。而且按照造 樣的情況，在該細密型非晶髏式矽晶層中，所產生霣氣特 性的劣化現象是撤小的。 如同在第5國中所說明之本發明另一値較佳實施例， 在該交錯型或頂绱W極薄膜霣晶體（TFT)的構造中，該活 性層56和57被配置在該源霣棰55和該汲霄極54之上，而且 該閭«極被配置在該活性層56和57之上。在如此形成的結 構中* 一層在該源霣極55和該汲霄棰54上被用作歃姆性接 觸層的N型非晶腥式矽晶層53, Μ —段間距在該輕度截止 層58和該絕緣層59上而形成；一層利用化學汽相沈積法（ 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） 10 (請先閲讀背面之注意事項再填寫本頁) 装. 訂 A7 B7 五、發明説明（8 ) CVD)，而Μ具有較佳物理特性之离沈積速率形成的粗糙型 非晶驩式矽晶層57在那<53>上面被沈積而成；一層利用化 學汽相沈稹法（CVD)，而以具有較佳霣氣特性之低沈稹速 率形成的细密型非晶鼸式矽晶層56則在那（57)上面被沈積 而成；一層閘極络艨曆52則在那（56)上面被沈積而成；並 且該閘電棰51最後在諸晶層的頂端被沈積而成。 如同上述的實施例*當實際的通道層在該蘭電極之間 棰絕緣1中的介面上形成時，本發明的較佳實施例就能夠 藉由在該閜霣極的一邊上*形成具有較佳霣氣特性的非晶 龌式矽晶層*來減少該作用時間。 表格2是爲了在表格1的情況下所製造之薄膜«晶饈 基座，而採用雙重副層非晶龌式矽晶層的一但拥試结果。 表格1 晶層形成狀況 (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部中央樣準局負工消費合作社印製 表格2 結果 射頻功率（瓦） 壓力<Pa> 100 100 150 110 狀況 特 性 沈稹速率（埃/每分鏽> 電氣層 良好霣氣特性 70.97 物理層 良好物理特性 195.06 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） 五、 發明説明（ A7 B7Printed by the Employee Consumer Cooperative of the Central Bureau of Economic Affairs of the Ministry of Economic Affairs 5. Description of the invention (6) It is an amorphous silicon crystal layer with excellent physical and mechanical properties, and a coarse cast amorphous silicon that is deposited at a high deposition rate The crystalline layer 31 is disposed on the dense-type amorphous silicon crystalline layer 32 which is an amorphous silicon crystalline layer having good electrical characteristics and is deposited at a low deposition rate. The above-mentioned fine amorphous silicon crystal layer means that the light and dark conduction of the crystal layer is 106 * and the crystal layer M is deposited at a deposition rate of about 70-500 Angstroms per minute. At the same time, the coarse-type amorphous silicon crystal layer indicates that the light and dark S-sensitivity of the crystal layer is 104-10β * and the crystal layer M is deposited at a deposition rate of approximately 1 50-1 500 A / min. The deposition rate exceeds the sinking rate of the fine amorphous silicon silicon layer using chemical vapor deposition (CVD). In the description of M, the reason why M repeats the deposition rate range of the coarse and dense amorphous silicon crystal layer is to consider the structural difference. M and to obtain the above-mentioned light and dark conduction irrigation The general value of sensitivity, and therefore in some respects, limits the idea of the invention. A method of manufacturing a thin film transistor (TFT) having an active layer according to a preferred embodiment of the present invention will be described as follows. According to the manufacturing process of a thin-film transistor (TFT) of a liquid crystal display (LVD), an amorphous silicon layer which is an active layer of gate electrode itself can be manufactured in the following manner, that is (1-5 (30 angstroms / min. Low deposition rate deposited to a thickness of 50-500 angstroms to form, and the fine amorphous silicon layer 32 with better electrical characteristics, M and M about 1 50-1 OQQ Angstroms / per minute high deposition rate is deposited to a thickness of 1000-1500 Angstroms to form a thick, but the rough type of amorphous type with better physical and mechanical properties This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 Mm) IIIIIIII outfit — II 1 II order — line (please read the precautions on the back before filling in this f) Printed 399502_B7_ by the Ponggong Consumer Cooperative of the Central Bureau of Economic Affairs of the Ministry of Economic Affairs Ⅴ. Invention description (7) Silicon crystal layer 31 , Deposited onto the amorphous H-type crystalline layer 2 as the blue pole insulating layer. The deposition process of this amorphous crystalline silicon layer is the ring block of hydrogenated amorphous silicon-based silicon crystal at H »+ SiH * Carry out. As explained in section 4_, for thin «The double sub-layer amorphous silicon crystal layer of the TFT base is made of M in the following manner, and it also has an amorphous silicon-based silicon crystal layer which is formed by M at the rate of Shen Shen, and has The coarse sugar type amorphous silicon crystal layer 31 * with good physical and mechanical properties is arranged in the amorphous silicon crystal layer which is formed at a low deposition rate, and the fine amorphous silicon type silicon with good «gas characteristics Above the crystalline layer 32. Since the amorphous silicon crystalline layer is divided into a double sub-layer structure, and thus reduces the action time, and increases the action speed, adhesion, and deposition rate. And as the source and sink The rough silicon layer of the ohmic contact layer is used for etching. It is due to the fact that when the n-type amorphous silicon layer is shaped in the source and drain type setting process as explained in the first garden Afterwards, when it is etched again, it ca n’t be made like an inter-channel. And according to the situation of sample preparation, the degradation of the enlightenment characteristics in the fine amorphous silicon crystal layer is small. As described in the fifth country, another preferred value of the present invention In an embodiment, in the structure of the staggered or top W thin film thin-film crystal (TFT), the active layers 56 and 57 are disposed on the source 55 and the drain 54 and the It is arranged above the active layers 56 and 57. In the structure thus formed * a layer of N-type amorphous silicon crystals which are used as a nudity contact layer on the source electrode 55 and the Jixiaohe 54 Layer 53, Μ — segment spacing is formed on the light cut-off layer 58 and the insulating layer 59; a layer using chemical vapor deposition method (this paper scale is applicable to China National Standard (CNS) Α4 specifications (210X297 mm) 10 ( Please read the precautions on the back before filling in this page). Packing. Order A7 B7. 5. Description of the invention (8) CVD), and M has a rough type amorphous silicon layer with good physical properties and a deposition rate of 57 It is deposited on the < 53 >; a layer of fine amorphous silicon-based silicon crystal layer 56 formed by a chemical vapor phase sedimentation method (CVD), which is formed at a low sedimentation rate with better gas characteristics, is there ( 57) is deposited on it; a layer of gate electrode 52 is deposited on that (56); and the 51 electrical problem, finally formed on top of all deposited crystal layer. As in the above-mentioned embodiment * When the actual channel layer is formed on the interface in the insulating 1 between the blue electrodes, the preferred embodiment of the present invention can be formed by forming * on the side of the electrode Amorphous silicon layer with good gas characteristics * to reduce the action time. Table 2 is a test result of using the double sub-layer amorphous silicon silicon layer for the thin film «crystal base '' manufactured in the case of Table 1. Form 1 Crystal layer formation status (please read the precautions on the back before filling in this page). Form 2 printed by the Ministry of Economic Affairs Central Prototyping Bureau Negative Work Consumer Cooperative 2 Results RF Power (Watts) Pressure < Pa > 100 100 150 110 Status Characteristic sinking rate (Angstroms per minute rust) Good electrical characteristics of electrical layer 70.97 Good physical characteristics of physical layer 195.06 This paper scale is applicable to China National Standard (CNS) Α4 specifications (210Χ297mm) V. Description of invention (A7 B7
狀況 目前狀況 第一狀況 第二狀況 第三狀況 第四狀況 透縝 #1.6 #2.7 #3.8 #4.9 #5.0 细密型非晶» 2000 300 500 700 500 式矽晶層（t) (28分 11秒） (4分 14# ) (7分 03秒 ) (9分 52秒 ） (7分 03秒} 粗掐型非晶餵 0 1700 1500 1300 1000 式矽晶ii(t) (〇 ) (8分 43鉍) (7分 42秒> (S分 40秒 ） (5分 08秒 ） 厚度结和 2000 2000 2000 2000 1500 (請先閱讀背面之注意事項再填寫本頁) -裝- 經濟部中央梯準局貝工消費合作社印裝 在表格2中針對時間的部分’在目前狀況中28 ’ 11 ”的 時間值，在第1狀況中會減少為12’57”*而且在其他狀況 中也會減少。 本發明並不只是侷限在上述的較佳實施例，而是能夠 根據一個元件的特性，而Μ不同的方式來實現。Μ及根據 本發明所沈積的非晶體式矽晶層•並不會在電氣或物理特 性上劣化，而且會II由Κ不同的沈積速率而被沈積之雙重 副層所形成的方式，來減少該沈積時間。 如同以上所描述的一般，在本發明的一個較佳實陁例 中•提供一個具有一活性層的薄膜電晶體（TFT) •其中該 非晶體式矽晶層根據諸晶層的特性，而被分為一種雙重副 層。將提供一種能夠減少該作用時間，以及提高作用速度 *附著性，和沈積速率的製造方法。 本紙张尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 12 、11 線 五、發明説明（10 ) A7 B7 經濟部中央標準局貝工消費合作社印製 元件檷»對照 1.. ..間極金展層 2.. ..閘極絕绪非晶鼸式 氮晶層 3.. ..非晶體式矽晶層 4.. ..η型非晶《式矽晶層 5.. ..源-汲金屬«極 6.. ..保護層 7.. ..陽棰絕緣層 8----基座 31.. ..粗糙型非晶《式 矽晶層 32.. ..細密型非晶腥式 矽晶層 51——閘霣極 52.. ..閘棰絕緣層 53. ... η型非晶匾式矽晶層 (歃姆性接觭層） 54— —汲霣極 55— —源霣棰 56.. ..細密型非晶鼉式 矽晶層 57.. ..粗糙型非晶讎式 矽晶層 58.. ..輕度截止Λ 59.. ..絕鐮層 (請先閱讀背面之注意事項再填寫本頁) 装. 訂 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨0X297公釐） 13Status Current status First status Second status Third status Fourth status Thorough # 1.6 # 2.7 # 3.8 # 4.9 # 5.0 Fine amorphous »2000 300 500 700 500 type silicon crystal layer (t) (28 minutes 11 seconds) (4 min 14 #) (7 min 03 sec) (9 min 52 sec) (7 min 03 sec) Coarse pinch type amorphous feed 0 1700 1500 1300 1000 type silicon crystal ii (t) (〇) (8 min 43 bismuth ) (7 minutes 42 seconds> (S minutes 40 seconds) (5 minutes 08 seconds) Thickness and 2000 2000 2000 2000 1500 (please read the precautions on the back before filling this page) The time value of the time part of 28 printed in Form 2 by the Beigong Consumer Cooperative Society will be reduced to 12’57 ”* in the first situation and will be reduced in other situations. The invention is not limited to the above preferred embodiment, but can be implemented in different ways according to the characteristics of a device. M and the amorphous silicon layer deposited according to the invention Or the physical properties are degraded, and it will be reduced by the way that the double sub-layers are deposited by different deposition rates of K, to reduce Less deposition time. As described above, in a preferred embodiment of the present invention • Provide a thin film transistor (TFT) with an active layer • wherein the amorphous silicon crystal layer is based on the crystal layers The characteristics are divided into a double sub-layer. It will provide a manufacturing method that can reduce the action time, as well as increase the action speed * adhesion, and sedimentation rate. This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 Mm) 12、11 Line V. Description of the invention (10) A7 B7 Printed components of the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs »Comparative 1 ... inter-gold layer 2 ... Amorphous silicon-based nitrogen crystal layer 3: Amorphous silicon crystal layer 4 ... η-type amorphous "type silicon crystal layer 5 ... source-drain metal" pole 6 ... protective layer 7. .. Insulation layer 8-pedestal 31.... Rough amorphous "silicon layer 32.... Fine amorphous silicon layer 51-gate electrode" 52. .. gate insulation layer 53 .. η-type amorphous plaque type silicon crystal layer (symmetrical connection layer) 54--Ji Ji pole 55--source Ji 56. .. fine type Amorphous Silicon layer 57 ... rough rough amorphous silicon layer 58 ... light cut-off Λ 59 ... sable layer (please read the precautions on the back before filling this page) The paper size is applicable to China National Standard (CNS) A4 specification (2 丨 0X297mm) 13