JPH04180237A - Thin film transistor and production method - Google Patents
Thin film transistor and production methodInfo
- Publication number
- JPH04180237A JPH04180237A JP2309320A JP30932090A JPH04180237A JP H04180237 A JPH04180237 A JP H04180237A JP 2309320 A JP2309320 A JP 2309320A JP 30932090 A JP30932090 A JP 30932090A JP H04180237 A JPH04180237 A JP H04180237A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- film transistor
- electrode
- source
- polycrystalline silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims description 31
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 7
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 abstract description 4
- 239000011521 glass Substances 0.000 abstract description 4
- 229910052782 aluminium Inorganic materials 0.000 abstract description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 abstract description 2
- 229910003437 indium oxide Inorganic materials 0.000 abstract description 2
- 239000000203 mixture Substances 0.000 abstract description 2
- QHGNHLZPVBIIPX-UHFFFAOYSA-N tin(ii) oxide Chemical class [Sn]=O QHGNHLZPVBIIPX-UHFFFAOYSA-N 0.000 abstract description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 239000011159 matrix material Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 229910052804 chromium Inorganic materials 0.000 description 3
- 239000011651 chromium Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野１
本発明は、フラットデイスプレィ等に用いられる薄膜ト
ランジスターの構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] The present invention relates to the structure of a thin film transistor used in flat displays and the like.
［従来の技術］
近年、液晶デイスプレィ等のフラットデイスプレィは、
モの機動性の高さから、様々な分野での応用が期待され
、盛んに研究が行われている。そしてその応用の際には
、表示領域の拡大、画質の向上が重要な課題である。[Prior art] In recent years, flat displays such as liquid crystal displays have
Due to its high mobility, it is expected to be applied in a variety of fields, and research is actively being conducted on it. In its application, expanding the display area and improving image quality are important issues.
液晶デイスプレィは大きく分けて、単純マトリクス型と
アクティブマトリクス型に分けられるが、単純マトリク
ス型の場合、時分割で処理して画素の数をふやしている
ため、画質を高くすることに限界がある。そこで、アク
ティブマトリクス型の液晶デイスプレィに大きな期待が
寄せられている。Liquid crystal displays can be broadly divided into simple matrix types and active matrix types, but in the case of a simple matrix type, the number of pixels is increased through time-division processing, so there is a limit to how high the image quality can be improved. Therefore, there are great expectations for active matrix type liquid crystal displays.
しかし、アクティブマトリクス型の場合、表示領域の拡
大、画素の増大に伴い、アクティブデバイス等の容量に
よる影響での信号遅延が顕著になるため、薄膜トランジ
スターの特性による制限から、画素数に上限がある。こ
れを解決するには、薄膜トランジスターの特性の向上が
重要な課題である。However, in the case of an active matrix type, as the display area expands and the number of pixels increases, the signal delay due to the effect of the capacitance of the active device becomes noticeable, so there is an upper limit to the number of pixels due to limitations due to the characteristics of thin film transistors. . To solve this problem, improving the characteristics of thin film transistors is an important issue.
従来の一般的な薄膜トランジスターの一例を上面から眺
めた図を用いて第４図に示す。FIG. 4 shows an example of a conventional general thin film transistor viewed from above.
［発明が解決しようとする課題］
本発明による薄膜トランジスターは、従来の技術の項目
で述べた薄膜トランジスターの高性能化を実現するもの
で、その目的とするところは、従来の薄膜トランジスタ
ーより高性能な薄膜トランジスターの構造及びその製造
方法を提供するところにある。[Problems to be Solved by the Invention] The thin film transistor according to the present invention achieves higher performance than the thin film transistor described in the prior art section, and its purpose is to achieve higher performance than conventional thin film transistors. An object of the present invention is to provide a thin film transistor structure and a manufacturing method thereof.
［課題を解決するための手段］
本発明による薄膜トランジスターは、基板上に無ドープ
半導体を全面に付着させた構造を有することを特徴とす
る。またその製造方法では、基板上に無ドープ半導体を
形成した後、該無ドープ半導体をパターニングしないこ
とを特徴とする。[Means for Solving the Problems] A thin film transistor according to the present invention is characterized in that it has a structure in which an undoped semiconductor is deposited over the entire surface of a substrate. Further, the manufacturing method is characterized in that after forming the undoped semiconductor on the substrate, the undoped semiconductor is not patterned.
［作用］
電界効果トランジスターにおいて、ゲート酸化膜とチャ
ンネル部の界面は、その電気的特性を決定する重大な因
子であり、その特性の向上のためには界面の清浄化が非
常に求められる。[Operation] In a field effect transistor, the interface between the gate oxide film and the channel portion is an important factor that determines its electrical characteristics, and in order to improve the characteristics, cleaning of the interface is extremely required.
−射的な電界効果トランジスターは、その界面の形成方
法として熱酸化法を用いているため、界面がシリコン中
に入り込んで形成されるので、特に特殊な製造方法を用
いなくても清浄な界面を形成することができる。- Radical field effect transistors use a thermal oxidation method to form the interface, so the interface is formed by penetrating the silicon, so it is possible to create a clean interface without using any special manufacturing method. can be formed.
しかし、薄膜トランジスターの場合、チャンネル部の無
ドープシリコンを形成した後、該無ドープシリコンをパ
ターニングする工程で界面が著しく汚染され、そのため
薄膜トランジスターの電気的特性に非常な悪影響を及ぼ
す。However, in the case of a thin film transistor, the interface is significantly contaminated during the step of patterning the undoped silicon after forming the undoped silicon of the channel portion, which has a very negative effect on the electrical characteristics of the thin film transistor.
本発明による製造方法は、基板上に無ドープ半導体を全
面に付着させた後バターニングしないことを特徴として
おり、そのため先の界面は非常に清浄なものに保たれる
特徴を有する。The manufacturing method according to the present invention is characterized in that no buttering is performed after the undoped semiconductor is deposited on the entire surface of the substrate, so that the previous interface is kept extremely clean.
［実施例］
本発明による薄膜トランジスタの構造の一例を上面より
眺めた図を第１図に示す。[Example] FIG. 1 shows an example of the structure of a thin film transistor according to the present invention viewed from above.
ガラス基板１上に、ソース電極、 ドレイン電極として
機能する、リンドープ多結晶シリコンによる電極領域２
．３が形成されている。さらに、無ドープ多結晶シリコ
ンによるチャンネル領域４、ゲート酸化膜５が基板上全
面に形成されており、さらにインジウムと錫の酸化物の
混合物よりなるクロムによるゲート電極６が形成されて
いる。そして、酸化シリコン薄膜によるソース−ゲート
電極間絶縁膜７、アルミニウムによるソース電極８、Ｉ
ＴＯによるドレイン電極９が形成されている。An electrode region 2 made of phosphorus-doped polycrystalline silicon that functions as a source electrode and a drain electrode is formed on a glass substrate 1.
．． 3 is formed. Further, a channel region 4 made of undoped polycrystalline silicon and a gate oxide film 5 are formed over the entire surface of the substrate, and a gate electrode 6 made of chromium made of a mixture of indium and tin oxides is further formed. Then, a source-gate electrode insulating film 7 made of a silicon oxide thin film, a source electrode 8 made of aluminum, and an I
A drain electrode 9 made of TO is formed.
第１図に示した本発明による薄膜トランジスタの構造の
一例のＡ−Ｂでの断面構造を示した図を第２図に示す。FIG. 2 shows a cross-sectional structure taken along line AB of an example of the structure of the thin film transistor according to the present invention shown in FIG.
本発明による製造方法の一例を構造の断面図を用いて第
３図に示す。An example of the manufacturing method according to the present invention is shown in FIG. 3 using a cross-sectional view of the structure.
第３図ａの工程
ガラス基板上１に、リンをドーピングした多結晶シリコ
ン薄膜を減圧ＣＶＤ法を用いて１２００人の厚さになる
よう形成し、フォトリソグラフィー法を用いて、ソース
電極、 ドレイン電極として機能するリンドープ多結晶
シリコンによる電極領域２．３をパターニングし形成す
る。Step of Figure 3a: A polycrystalline silicon thin film doped with phosphorus is formed on a glass substrate 1 using low pressure CVD to a thickness of 1200 nm, and source and drain electrodes are formed using photolithography. An electrode region 2.3 made of phosphorus-doped polycrystalline silicon, which functions as an electrode, is patterned and formed.
第３図すの工程
無ドープ多結晶シリコン薄膜を減圧ＣＶＤ法を用いて２
５０Ａの厚さになるよう形成し、該薄膜のパターニング
は行なわず、チャネル領域４を形成する。Figure 3 shows the step of forming an undoped polycrystalline silicon thin film using the low pressure CVD method.
The thin film is formed to have a thickness of 50 Å, and the channel region 4 is formed without patterning the thin film.
第３図Ｃの工程
酸化シリコン薄膜を常圧ＣＶＤ法を用いて１５００Ａの
厚さになるよう形成し、ゲート酸化膜５を形成する。Step of FIG. 3C: A silicon oxide thin film is formed to a thickness of 1500 Å using the atmospheric pressure CVD method, and a gate oxide film 5 is formed.
第３図ｄの工程
クロムをスパッタリング法を用いて２０００人の厚さに
なるよう形成し、ゲート電極６をパターニングし形成す
る。Step of FIG. 3d: Chromium is formed to a thickness of 2000 mm using a sputtering method, and the gate electrode 6 is patterned and formed.
第３図ｅの工程
酸化シリコン薄膜を常圧ＣＶＤ法を用いて５０００Ａの
厚さになるよう形成し、ソース−ゲート電極間絶縁膜７
を形成する。In the process shown in FIG. 3e, a silicon oxide thin film is formed to a thickness of 5000 Å using the normal pressure CVD method, and the insulating film 7 between the source and gate electrodes is formed.
form.
第３図ｆの工程
酸化シリコン薄膜５．７を、ソース電極、ドレイン電極
として機能するリンドープ多結晶シリコンによる電極領
域２．３が露出するようパターニングし、更にアルミニ
ウムをスパッタリング法を用いて８０００人の厚さにな
るよう形成し、ソース電極８を形成する。またＩＴＯを
スパッタリング法を用いて２００ＯＡの厚さになるよう
形成し、ドレイン電極９を形成する。The silicon oxide thin film 5.7 of FIG. The source electrode 8 is formed by forming the source electrode 8 to a certain thickness. Further, ITO is formed using a sputtering method to a thickness of 200 OA to form a drain electrode 9.
なお、本発明による実施例では、チャンネル部の材料と
して多結晶シリコンを用いたが、非晶質シリコン、シリ
コン以外の材料を用いても同様な効果が期待できること
は明かであり、それらも本発明の範中に属する。In the embodiment according to the present invention, polycrystalline silicon was used as the material for the channel portion, but it is clear that the same effect can be expected by using amorphous silicon or a material other than silicon, and these are also applicable to the present invention. belongs to the category of
同様に、他の材料についてもここに示した物に限定する
ものではない。Similarly, other materials are not limited to those shown here.
［発明の効果］
本発明による構造の薄膜トランジスターは、従来の構造
の薄膜トランジスターよりも電気的特性の立ち上がりの
急峻性がアップし、高いオン電流を流すことができた。[Effects of the Invention] A thin film transistor having a structure according to the present invention had a steeper rise in electrical characteristics than a thin film transistor having a conventional structure, and was able to flow a high on-current.
また、それを応用して作製した液晶デイスプレィパネル
はコントラストが従来のものよりも大幅にアップした。In addition, the contrast of the liquid crystal display panel manufactured using this technology is significantly higher than that of conventional panels.
さらに工程的には、無ドープの半導体のパターニングを
行なう工程の削減、及び該パターニング用のフォトマス
クが不必要になるという効果が得られた。Furthermore, in terms of process, the effect of reducing the step of patterning an undoped semiconductor and eliminating the need for a photomask for patterning was achieved.
本発明が、フラットデイスプレィ等へもたらす効果は大
きなものであることを確信する。We are confident that the present invention will have a great effect on flat displays and the like.
第１図は、本発明による薄膜トランジスタの構造の一例
を上面より眺めた図。
１・・・・・・ガラス基板
２・・・・・・ソース電極として機能するリンドープ多
結晶シリコンによる電極領域
３・・・・・・ドレイン電極として機能するリンドープ
多結晶シリコンによる電極領域
４・・・・・・無ドープ多結晶シリコンによるチャンネ
ル領域
５・・・・・・酸化シリコン薄膜によるゲート酸化膜６
・・・・・・クロムによるゲート電極７・・・・・・酸
化シリコン薄膜によるソース−ゲート電極間絶縁膜
８・・・・・・アルミニウムによるソース電極９・・・
・・・ＩＴＯによるドレイン電極第２図は、第１図に示
した本発明による薄膜トランジスタの構造の一例のＡ−
Ｂでの断面構造を示した図。
第３図（ａ）〜（ｆ）は、本発明による製造方法の一例
を構造の断面図を用いて示した図。
第４図は、従来の一般的な薄膜トランジスターの一例を
上面から眺めた図を用いて示した図。
以上
出願人 セイコーエプソン株式会社
代理人 弁理士 給水 喜三部 他１名第３図
第４図FIG. 1 is a top view of an example of the structure of a thin film transistor according to the present invention. 1... Glass substrate 2... Electrode region made of phosphorus-doped polycrystalline silicon that functions as a source electrode 3... Electrode region 4 made of phosphorus-doped polycrystalline silicon that serves as a drain electrode... ... Channel region 5 made of undoped polycrystalline silicon ... Gate oxide film 6 made of silicon oxide thin film
...Gate electrode 7 made of chromium...Source-gate electrode insulating film 8 made of silicon oxide thin film...Source electrode 9 made of aluminum...
. . . The drain electrode made of ITO in FIG. 2 is an example of the structure of the thin film transistor according to the present invention shown in FIG.
The figure which showed the cross-sectional structure at B. FIGS. 3(a) to 3(f) are diagrams showing an example of the manufacturing method according to the present invention using cross-sectional views of the structure. FIG. 4 is a diagram showing an example of a conventional general thin film transistor viewed from above. Applicant Seiko Epson Co., Ltd. Agent Patent attorney Water supply Kisanbe and 1 other person Figure 3 Figure 4
Claims (2)
を有することを特徴とする薄膜トランジスター。(1) A thin film transistor characterized by having a structure in which an undoped semiconductor is entirely adhered to a substrate.
プ半導体をパターニングしないことを特徴とする薄膜ト
ランジスターの製造方法。(2) A method for manufacturing a thin film transistor, characterized in that after forming an undoped semiconductor on a substrate, the undoped semiconductor is not patterned.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2309320A JPH04180237A (en) | 1990-11-15 | 1990-11-15 | Thin film transistor and production method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2309320A JPH04180237A (en) | 1990-11-15 | 1990-11-15 | Thin film transistor and production method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04180237A true JPH04180237A (en) | 1992-06-26 |
Family
ID=17991599
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2309320A Pending JPH04180237A (en) | 1990-11-15 | 1990-11-15 | Thin film transistor and production method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04180237A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100244513B1 (en) * | 1996-12-27 | 2000-02-01 | 전주범 | Thin film actuated mirror array and its fabrication method |
| JP2002543625A (en) * | 1999-05-05 | 2002-12-17 | イー−インク コーポレイション | Minimal patterned semiconductor devices for display applications |
| JP2004212992A (en) * | 2002-12-26 | 2004-07-29 | Lg Phillips Lcd Co Ltd | Dual-panel type organic electroluminescent device and its manufacturing method |
| JP2012078823A (en) * | 2010-09-10 | 2012-04-19 | Semiconductor Energy Lab Co Ltd | Transistor, liquid crystal display device, and manufacturing method therefor |
-
1990
- 1990-11-15 JP JP2309320A patent/JPH04180237A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100244513B1 (en) * | 1996-12-27 | 2000-02-01 | 전주범 | Thin film actuated mirror array and its fabrication method |
| JP2002543625A (en) * | 1999-05-05 | 2002-12-17 | イー−インク コーポレイション | Minimal patterned semiconductor devices for display applications |
| JP2004212992A (en) * | 2002-12-26 | 2004-07-29 | Lg Phillips Lcd Co Ltd | Dual-panel type organic electroluminescent device and its manufacturing method |
| JP2007329138A (en) * | 2002-12-26 | 2007-12-20 | Lg Phillips Lcd Co Ltd | Dual panel type organic electroluminescent element and its manufacturing method |
| JP2012078823A (en) * | 2010-09-10 | 2012-04-19 | Semiconductor Energy Lab Co Ltd | Transistor, liquid crystal display device, and manufacturing method therefor |
| US9490350B2 (en) | 2010-09-10 | 2016-11-08 | Semiconductor Energy Laboratory Co., Ltd. | Transistor, liquid crystal display device, and manufacturing method thereof |
| US10170500B2 (en) | 2010-09-10 | 2019-01-01 | Semiconductor Energy Laboratory Co., Ltd. | Transistor, liquid crystal display device, and manufacturing method thereof |
| US11043509B2 (en) | 2010-09-10 | 2021-06-22 | Semiconductor Energy Laboratory Co., Ltd. | Transistor, liquid crystal display device, and manufacturing method thereof |
| US12040331B2 (en) | 2010-09-10 | 2024-07-16 | Semiconductor Energy Laboratory Co., Ltd. | Transistor, liquid crystal display device, and manufacturing method thereof |
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