JPH02137374A - Field-effect transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To make a parasitic capacity small and to realize a high-speed operation by a method wherein a gate electrode, a source electrode and a drain electrode are constituted at intervals of a slight gap. CONSTITUTION:Electrode regions 2, 3, 4, by polycrystalline silicon doped with phosphorus, which function as gate electrode, a source electrode and a drain electrode are formed on a glass substrate 1. In this case, the gate electrode 2, the source electrode 3 and the drain electrode 4 for a transistor are constituted on an identical plane at intervals of a slight gap. That is to say, a semiconductor thin film is etched by making use of a thin film of a bad step coverage as a mask; thereby, the gate electrode, the source electrode and the drain electrode are formed in a separated manner. Thereby, an alignment operation is not required; a parasitic capacity can be reduced and operating speed can be speeded up.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to the structure of a field effect transistor used in integrated circuits, flat displays, etc.

[Prior art] In recent years, flat displays such as liquid crystal displays have
Due to its high mobility, it is expected to be applied in a variety of fields, and research is being actively conducted. In its application, expanding the display area and improving image quality are important issues.

Liquid crystal displays can be broadly divided into simple matrix types and active matrix types, but in the case of a simple matrix type, the number of pixels is increased through time-division processing, so there is a limit to how high the image quality can be improved. Therefore, there are great expectations for active matrix type liquid crystal displays.

However, in the case of an active matrix type, as the display area expands and the number of pixels increases, the signal delay due to the effect of the capacitance of the active device becomes noticeable, so there is an upper limit to the number of pixels due to limitations due to the characteristics of field effect transistors. be. To solve this problem, improving the characteristics of field-effect transistors is an important issue.

An example of a conventional general field effect transistor is shown in FIG. 3 using a cross-sectional view of the structure.

[Problems to be Solved by the Invention] The field-effect transistor according to the present invention realizes higher performance of the field-effect transistor described in the section of the prior art, and its purpose is to improve the performance of the field-effect transistor described in the prior art section. An object of the present invention is to provide a structure of a field effect transistor that has smaller parasitic capacitance and can operate at high speed, and a method for manufacturing the same.

[Means for Solving the Problems] A field effect transistor according to the present invention has a gate electrode,
It is characterized in that the source electrode and the drain electrode are arranged on the same plane with a slight gap between them. Further, the manufacturing method is characterized in that it includes a step of separately forming a gate electrode, a source electrode, and a drain electrode by etching the semiconductor thin film using a thin film with poor step coverage as a mask.

[Operation] In a field effect transistor, the parasitic capacitance formed between the gate electrode and the drain electrode via the gate insulating film is an important factor that determines the dynamic characteristics of the device. For example, when a driving element is configured, the upper limit of its operating speed is
It is determined by the current that can flow through the element and the parasitic capacitance, and the larger the current that can flow and the smaller the parasitic capacitance, the faster the operating speed will be.

Furthermore, when used in a driving element of a liquid crystal display panel, the larger the parasitic capacitance, the greater the effect that a change in the potential of the gate electrode has on the drain electrode, that is, the shift down.
If the parasitic capacitance is too large, the potential applied to the liquid crystal will not be constant, which will cause problems in gradation display, etc.

However, in conventional field effect transistors, a slight overlap must be provided between the gate electrode and the drain electrode in order to ensure margin for alignment of the photomask.
There is also a limit to the reduction of the parasitic capacitance.

The manufacturing method according to the present invention is characterized in that it includes a step of separately forming a gate electrode, a source electrode, and a drain electrode by etching a semiconductor thin film using a thin film with poor step coverage as a mask. There is no need for alignment as with field effect transistors, and it is possible to drastically reduce parasitic capacitance. Further, when this manufacturing method is used, the structure is as shown in claim 1.

[Example] FIG. 1 shows a cross-sectional view of an example of the structure of a field effect transistor according to the present invention.

6 is formed. Source and drain electrodes 7 are made of ITO made of a mixture of indium and tin oxides.
．． 8. An element protection film 9 made of a silicon oxide thin film is formed.

An example of the manufacturing method according to the present invention is shown in FIGS. 2(a) to 2(g) using cross-sectional views of the structure.

Step of FIG. 2 ta) A phosphorus-doped polycrystalline silicon thin film is formed on the glass substrate 1 to a thickness of 120 OA using low pressure CVD method, and an island-shaped phosphorus-doped polycrystalline silicon thin film is formed using photolithography method. Pattern and form IO.

On the glass substrate 1, electrode regions 2.3.4 made of phosphorus-doped polycrystalline silicon are formed which function as gate electrodes, source electrodes, and drain electrodes. Furthermore, a gate oxide film 5 made of silicon oxide and a channel region made of non-doped polycrystalline silicon (FIG. 2, 1b) are formed by forming a silicon oxide thin film using the ECR plasma method.
The gate oxide film 5 is formed to have a thickness of A, and is patterned using photolithography.

Step of FIG. 2(c) A silicon oxide thin film is formed on the entire surface to an appropriate thickness using the ECR plasma method to form a silicon oxide thin film 11 with poor step coverage.

Formed using a pressure CVD method to a thickness of 250 mm,
A channel region 6 made of non-doped polycrystalline silicon is patterned and formed using a photolithography method.

Step of FIG. 2(d) Etching is performed using the silicon oxide thin film 11 with poor step coverage formed using the ECR plasma method as a mask, and the island-shaped phosphorus-doped polycrystalline silicon thin film is formed in the step of FIG. 2(a). A phosphorus-doped polycrystalline silicon thin film 2 functions as a gate electrode, a phosphorus-doped polycrystalline silicon thin film 3 functions as a source electrode, and a phosphorus-doped polycrystalline silicon thin film 4 functions as a drain electrode.
, and then a silicon oxide thin film 11 with poor step coverage! tJIIli.

The process shown in Figure 2(e) reduces the polycrystalline silicon thin film without any doping in Figure 2(e).
Step f) ITO is formed to a thickness of 200 OA using a sputtering method, and source and drain electrodes 7.8 are patterned and formed.

FIG. 2 (Main Process) A silicon oxide thin film is formed to a thickness of 5000 Å using the atmospheric pressure CVD method, and an element protection film 9 of the silicon oxide thin film is formed.

In the embodiment according to the present invention, polycrystalline silicon is used as the material for the channel portion, but similar effects can be expected even if single crystal silicon, amorphous silicon, or a material other than silicon is used.

Furthermore, in the embodiment according to the present invention, silicon oxide produced by the ECR method was used as a mask during etching.
It is clear that the same effect can be expected even if a manufacturing method other than the CR plasma method or a thin film other than silicon oxide is used as a mask, and these are within the scope of the present invention.

[Effects of the Invention] The field effect transistor with the structure according to the present invention has a much smaller parasitic capacitance than the field effect transistor with the conventional structure, and when used as a driving element, it has a much higher parasitic capacitance than the field effect transistor with the conventional structure. It is now possible to use frequencies up to Furthermore, when used in a liquid crystal display element, downshifting was almost eliminated and display reproducibility was dramatically improved.

We are confident that the present invention will have a great effect on flat displays and the like.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a cross-sectional view of an example of the structure of a field effect transistor according to the present invention. 1... Glass substrate 2... Electrode region made of phosphorus-doped polycrystalline silicon that functions as a gate electrode 3... Electrode region 4 made of phosphorus-doped polycrystalline silicon that serves as a source electrode ... Electrode region 5 made of phosphorus-doped polycrystalline silicon that functions as a drain electrode ... Gate oxide film 6 made of silicon oxide...
...Channel region 7 made of non-doped polycrystalline silicon...Source electrode 8 made of ITO...
Drain electrode 9 made of ITO...Element protection film made of silicon oxide thin film FIGS. 2(a) to 2(g) are diagrams showing an example of the manufacturing method according to the present invention using cross-sectional views of the structure. 10... Island-shaped phosphorus-doped polycrystalline silicon thin film 11... Process of silicon oxide thin film with poor step coverage (Figure 2 ra) A phosphorous-doped polycrystalline silicon thin film is deposited on a glass substrate l by low pressure CVD. A step of forming a phosphorus-doped polycrystalline silicon thin film 10 in an island shape using a photolithography method and patterning it to a thickness of 120 OA using a photolithography method. Figure 2 (bl process) A silicon oxide thin film was prepared using the ECR plasma method.
A step of forming gate oxide film 5 to have a thickness of A and patterning using photolithography. Step of FIG. 2 tc+ A step of forming a silicon oxide thin film over the entire surface to an appropriate thickness using the ECR plasma method to form a silicon oxide thin film 11 with poor step coverage. FIG. 2 (d+ step) Etching is performed using the silicon oxide thin film 11 with poor step coverage formed using the ECR plasma method as a mask, and the island-shaped phosphorus-doped polycrystalline silicon thin film 10 formed in the step of FIG. A phosphorus-doped polycrystalline silicon thin film 2 that functions as a gate electrode, a phosphorus-doped polycrystalline silicon thin film !II that functions as a source electrode, and a phosphorus-doped polycrystalline silicon thin film 4 that functions as a drain electrode are formed. Step of peeling off the silicon oxide thin film 11. Step of Fig. 2 Le) A polycrystalline silicon thin film without any doping is subjected to low pressure CVD.
A step of forming a channel region 6 made of non-doped polycrystalline silicon using a photolithography method and patterning the channel region 6 using a photolithography method. Step of FIG. 2 Bo) A step of forming ITO to a thickness of 2000 Å using a sputtering method, and patterning and forming source and drain electrodes 7.8. Step of FIG. 2 tg+ A step of forming a silicon oxide thin film to a thickness of 5000A using the atmospheric pressure CVD method, and forming an element protection film 9 of the silicon oxide thin film. FIG. 3 is a diagram showing an example of a conventional general field effect transistor using a cross-sectional view of the structure. 12...Insulating film between source, drain, and gate electrodes using silicon oxide thin film Applicant: Seiko Epson Corporation Representative Patent attorney: Masayoshi Kamikushi and 1 other person Figure 2 Figure 3

Claims (2)

[Claims] (1) A field effect transistor characterized in that a gate electrode, a source electrode, and a drain electrode are arranged on the same plane with a slight gap between them. (2) By etching the semiconductor thin film using a thin film with poor step coverage as a mask, the gate electrode
A method for manufacturing a field effect transistor, comprising a step of separately forming a source electrode and a drain electrode.