KR100328848B1 - Manufacturing Method of Thin Film Transistor - Google Patents
Manufacturing Method of Thin Film Transistor Download PDFInfo
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- KR100328848B1 KR100328848B1 KR1019980024341A KR19980024341A KR100328848B1 KR 100328848 B1 KR100328848 B1 KR 100328848B1 KR 1019980024341 A KR1019980024341 A KR 1019980024341A KR 19980024341 A KR19980024341 A KR 19980024341A KR 100328848 B1 KR100328848 B1 KR 100328848B1
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- thin film
- gate electrode
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- 238000004519 manufacturing process Methods 0.000 title abstract description 16
- 239000010409 thin film Substances 0.000 title abstract description 10
- 239000004065 semiconductor Substances 0.000 claims abstract description 31
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 27
- 229910021419 crystalline silicon Inorganic materials 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 10
- 239000012535 impurity Substances 0.000 claims description 5
- 239000010408 film Substances 0.000 abstract description 6
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 6
- 229910021424 microcrystalline silicon Inorganic materials 0.000 description 19
- 239000013078 crystal Substances 0.000 description 5
- 239000011521 glass Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000001939 inductive effect Effects 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000007847 structural defect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78663—Amorphous silicon transistors
- H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
Abstract
본 발명은 박막 트랜지스터 액정표시소자의 제조방법에 관한 것으로, 특히, 고이동도를 얻을 수 있는 박막 트랜지스터의 제조방법에 관한 것이다. 본 발명의 박막 트랜지스터의 제조방법은, 상부면에 게이트 전극이 형성되고, 상기 게이트 전극이 덮혀지도록 전면 상에 게이트 절연막이 도포된 기판을 제공하는 단계; 상기 게이트 전극 상부의 게이트 절연막 상에 비정질실리콘층과 미세 결정질실리콘층이 각각 10 내지 100두께와 10 내지 200두께로 적어도 2 내지 20층씩이 번갈아 적층된 다층구조의 반도체층을 형성하는 단계; 상기 반도체층의 중심부 상에 에치 스톱퍼를 형성하는 단계; 상기 에치 스톱퍼의 양측 가장자리 및 반도체층 상에 오믹층은 형성 하는 단계; 상기 오막층 상에 소오스/드레인 전극을 형성하는 단계를 포함하는 것을 특징으로 한다.The present invention relates to a method for manufacturing a thin film transistor liquid crystal display device, and more particularly, to a method for manufacturing a thin film transistor capable of obtaining high mobility. According to an aspect of the present invention, there is provided a method of fabricating a thin film transistor, the method comprising: providing a substrate having a gate electrode formed on an upper surface thereof and a gate insulating film coated on a front surface thereof so as to cover the gate electrode; An amorphous silicon layer and a fine crystalline silicon layer are each 10 to 100 on the gate insulating layer on the gate electrode. Thickness and 10 to 200 Forming a semiconductor layer having a multilayer structure in which at least 2 to 20 layers are alternately stacked in thickness; Forming an etch stopper on a central portion of the semiconductor layer; Forming an ohmic layer on both edges of the etch stopper and the semiconductor layer; And forming a source / drain electrode on the ohmic layer.
Description
본 발명은 박막 트랜지스터 액정표시소자의 제조방법에 관한 것으로, 특히, 고이동도를 얻을 수 있는 박막 트랜지스터의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a thin film transistor liquid crystal display device, and more particularly, to a method for manufacturing a thin film transistor capable of obtaining high mobility.
텔레비젼 및 그래픽 디스플레이 등의 표시 장치에 이용되는액정표시소자(Liquid Crystal Display : 이하, LCD)는 CRT(Cathod-ray tube)를 대신하여 개발되어져 왔다. 특히, 매트릭스 형태로 배열된 각 화소마다 박막 트랜지스터(Thin Film Transistor : 이하, TFT)가 구비되는 TFT LCD는 고속 응답 특성을 갖는 잇점과 고화소수에 적합하다는 잇점 때문에 CRT에 필적할만한 화면의 고화질화 및 대형화, 컬러화 등을 실현하고 있다.Liquid crystal displays (LCDs) used in display devices such as televisions and graphic displays have been developed in place of the CRT (Cathod-ray tube). In particular, TFT LCDs equipped with thin film transistors (TFTs) for each pixel arranged in a matrix form have high speed response characteristics and are suitable for high pixel numbers, so that the screen quality comparable to the CRT is increased and large. Colorization is realized.
여기서, TFT LCD는 통상 매트릭스 형태로 배열된 각 화소들마다 그들의 구동을 독립적으로 제어하기 위한 스위칭 소자로서 TFT가 형성되어 있는 하부기판과, 컬러화를 실현하기 위한 레드(Red), 블루(Blue), 및 그린(Green)의 삼색으로 이루어진 컬러필터들이 반복적으로 배열되어 있는 상부기판이 액정층의 개재하에 합착 되어 이루어진 구조이다.Here, a TFT LCD is usually a lower substrate on which TFTs are formed as switching elements for independently controlling their driving for each pixel arranged in a matrix form, and red, blue, And an upper substrate on which color filters composed of three colors of green are repeatedly arranged under the interposition of the liquid crystal layer.
도 1은 상기한 종래 TFT LCD의 하부기판을 도시한 단면도로서, 도시된 바와 같이, 유리 기판(1) 상에는 게이트 전극(2)이 형성되어 있고, 이러한 게이트 전극(2)이 덮혀지도록 유리기판(1) 전면에는 게이트 절연막(3)이 도포되어 있다. 그리고, 게이트 전극(2) 상부의 게이트 절연막(3) 상에는 패턴의 형태로 도핑되지 않은 비정질실리콘층으로 이루어진 반도체층(4)이 형성되어 있으며, 이 반도체층(4)의 중심부 상에는 통상 SiNX와 같은 금속층으로된 에치 스톱퍼(5)가 형성되어 있고, 상기 에치 스톱퍼(5) 및 반도체층(4) 상에는 불순물이 도핑된 비정질실리콘층으로 이루어진 오믹층(6)이 형성되어 있다.1 is a cross-sectional view illustrating a lower substrate of the conventional TFT LCD. As shown in the drawing, a gate electrode 2 is formed on a glass substrate 1, and a glass substrate (2) is covered so that the gate electrode 2 is covered. 1) The gate insulating film 3 is coated on the entire surface. On the gate insulating film 3 above the gate electrode 2, a semiconductor layer 4 made of an undoped amorphous silicon layer in the form of a pattern is formed, and on the center of the semiconductor layer 4, usually SiN X and An etch stopper 5 made of the same metal layer is formed, and an ohmic layer 6 made of an amorphous silicon layer doped with impurities is formed on the etch stopper 5 and the semiconductor layer 4.
또한, 화소영역에 해당하는 게이트 절연막 부분 상에는 투명 금속인 ITO(Indium Tin Oxide) 금속으로된 화소전극(8)이 형성되어 있고, 오믹층(6) 상에는 소오스/드레인 전극(7A, 7B)이 형성되어 있으며, 도시된 바와 같이, 소오스 전극(7A)은 화소전극(8)과 콘택되어 있다.In addition, a pixel electrode 8 made of indium tin oxide (ITO) metal, which is a transparent metal, is formed on a portion of the gate insulating layer corresponding to the pixel region, and source / drain electrodes 7A and 7B are formed on the ohmic layer 6. As shown, the source electrode 7A is in contact with the pixel electrode 8.
그러나, 상기와 같은 종래 TFT LCD는 비정질실리콘층으로 이루어진 반도체층의 낮은 이동도와 높은 광누설로 인하여 대화면의 고품위 LCD를 제작하는데 어려운 문제점이 있었다. 즉, 액정을 구동하기 위해 요구되는 최소한의 시간내에 차징을 시키기 위해서는 높은 이동도를 요구하게 되며, 또한, 14인치급 이상의 동영상 TFT LCD를 구현하기 위해서는 1.5cm2/Vs 이상의 이동도를 확보해야 하지만, 종래 비정질실리콘층으로 이루어진 반도체층의 경우에는 이동도가 1.2cm2/Vs 이하이기 때문에 대화면 TFT LCD의 제조에 적용시킬 수 없다.However, the conventional TFT LCD as described above has a problem that it is difficult to manufacture a high-quality LCD of a large screen due to the low mobility and high light leakage of the semiconductor layer consisting of an amorphous silicon layer. That is, in order to charge within the minimum time required to drive the liquid crystal, high mobility is required, and in order to realize a 14-inch or larger moving picture TFT LCD, it is necessary to secure mobility of 1.5 cm 2 / Vs or more. In the case of a semiconductor layer made of a conventional amorphous silicon layer, the mobility is 1.2 cm 2 / Vs or less, and thus it cannot be applied to the manufacture of a large screen TFT LCD.
한편, 종래에는 반도체층의 이동도를 향상시키기 위하여 비정질실리콘층 대신에 다결정실리콘층을 이용하는 연구가 진행되고 있으나, 이 경우, 이동도는 향상시킬 수 있지만, 제조비용이 증가되어 대화면 TFT LCD의 제조에 용이하게 적용할 수 없는 문제점이 있다.On the other hand, in the past, researches using a polysilicon layer instead of an amorphous silicon layer to improve the mobility of the semiconductor layer, but in this case, the mobility can be improved, but the manufacturing cost is increased to manufacture a large screen TFT LCD There is a problem that can not be easily applied to.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위하여 안출된 것으로서, 고이동도를 구현할 수 있는 TFT의 제조방법을 제공하는데, 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems, to provide a method for manufacturing a TFT that can implement high mobility, an object thereof.
도 1은 종래 기술에 따른 박막 트랜지스터 액정표시소자의 하부기판을 도시한 단면도.1 is a cross-sectional view showing a lower substrate of a thin film transistor liquid crystal display device according to the prior art.
도 2a 및 도 2b는 본 발명의 실시예에 따른 박막 트랜지스터의 제조방법을 설명하기 위한 공정 단면도.2A and 2B are cross-sectional views illustrating a method of manufacturing a thin film transistor according to an exemplary embodiment of the present invention.
(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
11 : 유리기판 12 : 게이트 전극11 glass substrate 12 gate electrode
13 : 게이트 절연막 14 : 비정실리콘층13 gate insulating film 14 amorphous silicon layer
15 : 미세 결정질실리콘층 16 : 반도체층15 fine crystalline silicon layer 16 semiconductor layer
17 : 에치 스톱퍼 18 : 오믹층17: etch stopper 18: ohmic layer
19A : 소오스 전극 19B : 드레인 전극19A: source electrode 19B: drain electrode
상기와 같은 목적을 달성하기 위한 본 발명의 TFT의 제조방법은, 상부면에게이트 전극이 형성되고, 상기 게이트 전극이 덮혀지도록 게이트 절연막이 도포된 기판을 제공하는 단계; 상기 게이트 전극 상부의 게이트 절연막 상에 비정질실리콘층과 미세 결정질실리콘층이 각각 10 내지 100두께와 10 내지 200두께로 적어도 2 내지 20층씩이 번갈아 적층된 다층 구조의 반도체층을 형성하는 단계; 상기 반도체층의 중심부 상에 에치 스톱퍼를 형성하는 단계; 상기 에치 스톱퍼의 양측 가장자리 및 반도체층 상에 오믹층을 형성하는 단계; 상기 오믹층 상에 소오스/드레인 전극을 형성하는 단계를 포함하는 것을 특징으로 한다.In accordance with another aspect of the present invention, there is provided a method of manufacturing a TFT, including: providing a substrate having a gate electrode formed on an upper surface thereof, and having a gate insulating film coated thereon to cover the gate electrode; An amorphous silicon layer and a fine crystalline silicon layer are each 10 to 100 on the gate insulating layer on the gate electrode. Thickness and 10 to 200 Forming a semiconductor layer having a multilayer structure in which at least 2 to 20 layers are alternately stacked in thickness; Forming an etch stopper on a central portion of the semiconductor layer; Forming an ohmic layer on both edges of the etch stopper and the semiconductor layer; And forming a source / drain electrode on the ohmic layer.
본 발명에 따르면, 반도체층을 수 개의 비정질실리콘층과 미세 결정질실리콘층의 적층 구조로 형성하고, 아울러, 미세 결정질실리콘층의 두께를 비정질실리콘층의 두께 보다 더 두껍게 형성하여 실질적인 전자의 흐름을 미세 결정질실리콘층이 주도하게 함으로써, 반도체층의 고이동도를 구현할 수 있다.According to the present invention, the semiconductor layer is formed of a laminated structure of several amorphous silicon layers and fine crystalline silicon layers, and the thickness of the fine crystalline silicon layer is formed thicker than the thickness of the amorphous silicon layer to substantially reduce the flow of electrons. By driving the crystalline silicon layer, high mobility of the semiconductor layer can be realized.
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 및 도 2b는 본 발명의 실시예에 따른 TFT의 제조방법을 설명하기 위한 공정 단면도로서, 우선, 도 2a에 도시된 바와 같이, 유리기판(11) 상에 게이트 전극(12)을 형성하고, 이러한 게이트 전극(12)이 덮혀지도록 유리기판(11) 전면 상에 게이트 절연막(13)을 형성한다. 그런 다음, 게이트 절연막(13) 상에 비정질실리콘층(14 : 이하, a-Si층이라 칭함)과 미세 결정질실리콘층(15 : 이하, μc-Si층이라 칭함)을 적층시킨다.2A and 2B are cross-sectional views illustrating a method of manufacturing a TFT according to an embodiment of the present invention. First, as shown in FIG. 2A, a gate electrode 12 is formed on a glass substrate 11. The gate insulating layer 13 is formed on the entire surface of the glass substrate 11 so that the gate electrode 12 is covered. Then, an amorphous silicon layer (14: hereinafter referred to as an a-Si layer) and a fine crystalline silicon layer (15: hereinafter referred to as a μc-Si layer) are laminated on the gate insulating film 13.
여기서, a-Si층(14)은 10 내지 100Å 두께로 형성하고, μc-Si층(15)은 10내지 200Å 두께로 형성함으로써, 상기 μc-Si층(15)의 두께가 a-Si층(14)의 두께와 같거나 크게 되도록 하며, 아울러, 상기 층들(14, 15)은 적어도 2층 이상씩, 바람직하게는, 통상적인 반도체층의 두께를 고려하여 2층 내지 20층씩을 번갈아 적층시킨다.Herein, the a-Si layer 14 is formed to have a thickness of 10 to 100 GPa, and the μc-Si layer 15 is formed to have a thickness of 10 to 200 GPa, so that the thickness of the μc-Si layer 15 is a-Si layer ( 14 and 15, and the layers 14 and 15 are alternately stacked by at least two layers, preferably two to twenty layers in consideration of the thickness of a conventional semiconductor layer.
이어서, 도 2b에 도시된 바와 같이, 적어도 2층 이상씩이 번갈아 적층되어 있는 μc-Si층과 a-Si층을 식각하여 게이트 전극(12) 상부의 게이트 절연막(13) 부분 상에 상기 a-Si층과 μc-Si층으로 이루어진 반도체층(15)을 형성한다.Subsequently, as shown in FIG. 2B, at least two or more layers of the c-Si layer and the a-Si layer are alternately etched to etch the a- on the portion of the gate insulating layer 13 above the gate electrode 12. A semiconductor layer 15 composed of an Si layer and a μc-Si layer is formed.
그리고 나서, a-Si층과 μc-Si층들의 적층 구조로된 반도체층(16)의 중심부 상에 공지된 방법으로 에치 스톱퍼(17)를 형성하고, 상기 에치 스톱퍼(17)의 양측 가장자리 및 노출된 반도체층(16) 상에 불순물이 도핑된 미세 결정질실리콘층(이하, n+μc-Si층으로 칭함)으로 이루어진 오믹층(18)을 형성한 후, 상기 오믹층(18) 상에 소오스/드레인 전극(19A, 19B)를 형성하여 TFT를 완성한다.Then, an etch stopper 17 is formed on the central portion of the semiconductor layer 16 in a stacked structure of a-Si layer and μc-Si layers, and both edges and exposures of the etch stopper 17 are formed. The ohmic layer 18 formed of a fine crystalline silicon layer doped with impurities (hereinafter, referred to as an n + μc-Si layer) on the semiconductor layer 16, and then a source / The drain electrodes 19A and 19B are formed to complete the TFT.
상기와 같은 구조를 갖는 본 발명의 TFT에서는 반도체층을 수 개의 a-Si층과 μc-Si층의 적층 구조로 형성하기 때문에 상기 두 층들간의 슈퍼 래티스 효과(Super Lattice), 즉, 서로 다른 물질층들이 박막으로 적층되는 경우에 결정학적 측면에서 적층된 각 층들이 하나의 격자 구조로되어 전체적으로는 하나의 결정구조를 갖게 되는 효과로 인하여 이러한 반도체층에서의 전자의 흐름은 원할하게 이루어지게 된다.In the TFT of the present invention having the structure as described above, since the semiconductor layer is formed of a stacked structure of several a-Si layers and μc-Si layers, a super lattice effect between the two layers, that is, different materials In the case where the layers are stacked in a thin film, the flow of electrons in the semiconductor layer is smoothly performed due to the effect that each layer stacked in a crystallographic aspect has a single crystal structure as a whole.
자세하게, 결정구조 측면에서 μc-Si층은 미세 결정구조들이 서로 연결되어있는 그물구조를 가지고 있는 반면에 a-Si층은 결정구조가 없기 때문에, 본 발명의 실시예에서와 같이 상기 층들을 적층시키게 되면 a-Si층과 μc-Si층이 그들 각각의 구조적인 결함을 상호 보완함으로써 전체적으로는 다결정실리콘층과 유사한 결정구조를 갖게 되고, 이에 따라, 이동도는 다결정실리콘층에 필적할만한 값을 갖게 된다.Specifically, in terms of crystal structure, the μc-Si layer has a mesh structure in which fine crystal structures are connected to each other, whereas the a-Si layer has no crystal structure, so that the layers are stacked as in the embodiment of the present invention. In this case, the a-Si layer and the μc-Si layer complement each other of their structural defects, and thus have a crystal structure that is similar to that of the polycrystalline silicon layer as a whole, and thus the mobility has a value comparable to that of the polycrystalline silicon layer. .
따라서, 본 발명의 실시예에서와 같이 a-Si층과 μc-Si층을 적어도 2층 이상씩 번갈아 적층시키되, 상기 μc-Si층의 두께를 a-Si층의 두께와 같거나 더 두껍게 형성하게 되면, 실질적인 전자의 흐름이 결정성이 우수한 μc-Si층들에 의해 주도되기 때문에 수 개의 a-Si층과 μc-Si층의 적층 구조로 이루어진 반도체층의 이동도는 1.5cm2/Vs 이상의 고이동도를 갖게 된다.Accordingly, as in the embodiment of the present invention, the a-Si layer and the μc-Si layer are alternately stacked at least two layers, so that the thickness of the μc-Si layer is equal to or thicker than the thickness of the a-Si layer. In this case, since a substantial flow of electrons is driven by the excellent crystallinity of the μc-Si layers, the mobility of the semiconductor layer composed of a stack of several a-Si and μc-Si layers is high at 1.5 cm 2 / Vs or higher. You have a degree.
또한, μc-Si층은 빛에 대한 민감도가 거의 없기 때문에 a-Si층만으로 반도체층을 구성하는 종래의 TFT 보다는 광누설전류를 효과적으로 감소시킬 수 있는 잇점도 있다.In addition, since the μc-Si layer has little sensitivity to light, there is an advantage that the light leakage current can be effectively reduced than the conventional TFT constituting the semiconductor layer with only the a-Si layer.
게다가, 본 발명의 실시예에서는 오믹층을 n+μc-Si층으로 형성하기 때문에 소오스/드레인 전극과 반도체층간의 접촉 저항을 감소시킬 수 있다. 즉, μc-Si층이 결정성이 있는 것에 기인하여 결정성이 없는 a-Si층에 불순물을 도핑하는 종래의 방법보다는 본 발명의 실시예가 불순물의 도핑 효율을 최소한 10배 이상 향상시킬 수 있으며, 이에 따라, 오믹층의 접촉 저항을 종래의 경우 보다 효과적으로 감소시킬 수 있게 되어 고이동도의 전자 흐름을 유도할 수 있게 되고, 결과적으로는TFT의 구동시에 온(On) 전류는 향상시키게 되고, 반면에, 오프(Off) 전류는 감소시킬 수 있게 된다.In addition, in the embodiment of the present invention, since the ohmic layer is formed of an n + μc-Si layer, the contact resistance between the source / drain electrodes and the semiconductor layer can be reduced. That is, the embodiment of the present invention can improve the doping efficiency of the impurity at least 10 times, rather than the conventional method of doping the impurity to the non-crystalline a-Si layer due to the crystallinity of the μc-Si layer, Accordingly, the contact resistance of the ohmic layer can be more effectively reduced than in the conventional case, thereby inducing high mobility electron flow, and consequently, the on current is improved when the TFT is driven. In turn, the off current can be reduced.
이상에서와 같이, 본 발명은 TFT의 반도체층을 수 개의 a-Si층과 μc-Si층의 적층 구조로 형성하여 반도체층의 이동도를 1.5cm2/Vs 이상의 고이동도가 되도록 할 수 있기 때문에 대화면 TFT LCD의 제조에 용이하게 적용시킬 수 있다.As described above, the present invention can form the semiconductor layer of the TFT in a stacked structure of several a-Si layer and μc-Si layer so that the mobility of the semiconductor layer can be high mobility of 1.5 cm 2 / Vs or more. Therefore, the present invention can be easily applied to the manufacture of large-screen TFT LCDs.
또한, μc-Si층은 빛에 대한 민감도가 낮기 때문에 광누설전류를 효과적으로 감소시킬 수 있으며, 이에 따라, 통상의 TFT LCD의 제조공정에서 광차단층을 형성하기 위한 공정을 삭제시킬 수 있게 되어 제조 공정을 단순화시킬 수 있다.In addition, since the μc-Si layer has low sensitivity to light, it is possible to effectively reduce the light leakage current, thereby eliminating the process for forming the light blocking layer in the conventional TFT LCD manufacturing process. Can be simplified.
게다가, 반도체층과 소오스/드레인 전극 사이에 개재되는 오믹층을 n+μc-Si층으로 형성하여 그들간의 접촉저항을 감소시킴으로써, 고이동도의 전자 흐름을 효과적으로 유도할 수 있다.In addition, an ohmic layer interposed between the semiconductor layer and the source / drain electrodes is formed as an n + μc-Si layer to reduce the contact resistance therebetween, thereby effectively inducing high mobility electron flow.
한편, 여기에서는 본 발명의 특정 실시예에 대하여 설명하고 도시하였지만, 당업자에 의하여 이에 대한 수정과 변형을 할 수 있다. 따라서, 이하, 특허청구의 범위는 본 발명의 진정한 사상과 범위에 속하는 한 모든 수정과 변형을 포함하는 것으로 이해할 수 있다.Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.
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