JP3139154B2 - Liquid crystal device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal device and a method for manufacturing the same.

[0002]

2. Description of the Related Art Toward the advanced information society, there is an increasing demand for realizing thin and lightweight displays and mass production. Among them, a liquid crystal display (hereinafter, referred to as LCD) is the most prominent display, and demands for higher definition and higher aperture ratio are increasing.

An LCD is roughly divided into an active matrix type LCD having a non-linear element such as a thin film transistor (hereinafter referred to as a TFT) as a switching element in each pixel.
(Hereinafter referred to as AM-LCD), and a simple matrix type LCD in which substrates having strip-shaped transparent electrodes formed in a row direction and a column direction are stuck together via a liquid crystal, and each intersection is a pixel. However, AM-L
Since CD is promising, AM-LCD, especially TF
Those having T will be described.

FIG. 2 shows a configuration of a pixel. FIG.
Reference numeral 201 denotes an equivalent circuit of a pixel, 201 denotes a TFT, 202 denotes a scanning line, 203 denotes a signal line, and 204 denotes a pixel capacitor. The pixel is disposed between a transparent electrode (206 in FIG. It is formed by sandwiching a liquid crystal. Reference numeral 205 denotes an additional capacitor which is formed on the substrate on which the TFT is formed. Here, an example is shown in which a dielectric is sandwiched between the drain electrode of the TFT and the preceding scanning line. However, a capacitance line may be newly provided and formed between the drain electrodes. However, the former is more preferable in consideration of the improvement of the aperture ratio. FIG. 4B is a plan view. The numbers in the figure are the same as those in FIG. FIG. 1C shows a cross-sectional structure taken along the line II of FIG. 1B. The same applies to the numbers.

The display on the LCD is as follows. After selecting a scanning line at a certain timing and turning on the TFT, the pixel capacitance and the additional capacitance of the pixel selected from the signal line are
The image information is written as a voltage. Then, this voltage is applied to the liquid crystal, so that the transmittance of the pixel capacitance region changes and display is performed.

At this time, since the written voltage is discharged by a time constant determined by the product of the capacitance formed in the pixel and the resistance value connected to the pixel, it is desirable that the capacitance value and the resistance value be as large as possible. It is technically difficult to increase the resistance value of the liquid crystal beyond the current level, so it is necessary to deal with the problem by increasing the capacitance value. Therefore, the capacity that is not sufficient only by the pixel capacity is compensated by the above-described additional capacity.

[0007]

However, the prior art has the following problems.

As described above, LCDs are required to have higher definition and higher aperture ratio. To meet these requirements, it is required to reduce the pixel pitch while maintaining the aperture ratio. . In terms of miniaturization of the pixel pitch, polycrystalline silicon (hereinafter referred to as “p”) mounted on a video camera or mounted on a liquid crystal projector at present.
described as poly-si. )).
This is particularly severe for siLCD. For example, a diagonal 0.7 inch size, ultra-small po of 100,000 pixels level
In the ly-siLCD, the pixel size is about 30 μm square, and the above-described TFT,
A pixel electrode, an additional capacitor, a scanning line, and a signal line are formed, and the decisive factor is how to make each component other than the pixel electrode compact. Unlike a polycrystalline silicon, a poly-SiLCD uses a TFT with a poly-si having a mobility as large as 10 times or more, so that an element having a driving capability can be formed in a small size. For the scanning lines and signal lines, it is possible to form ultra-fine lines by optimizing the materials used and applying the silicon processing device. However, the capacity formed in one pixel is not sufficient as the pixel area is reduced. Value cannot be obtained only by pixel capacity,
Dependence on additional capacity is increased. However, increasing the additional capacitance without darkness leads to increasing the occupied area. In addition, in the poly-Si LCD, the additional capacitance is made of poly-Si forming a TFT. On the other hand, ploy-si is poor in terms of light transmittance, particularly in the visible light region, and an increase in occupied area results in a substantial decrease in aperture ratio. Further, if the area occupied by the additional capacitance is reduced in consideration of the aperture ratio, the holding characteristics deteriorate, and this causes a serious problem in image display characteristics such as insufficient contrast in LCD display.

[0009]

According to another aspect of the present invention, there is provided a liquid crystal device having a thin film transistor on a substrate, a pixel electrode connected to the thin film transistor, and an additional capacitor. A first silicon layer serving as a drain region and a second silicon layer thicker than the first silicon layer serving as one electrode of an additional capacitor; an insulating film disposed on the first and second silicon layers; A gate electrode formed on the insulating film and the other electrode of the additional capacitor are arranged, and a surface of the second silicon layer on the insulating film side is made uneven. Further, the present invention is a method for manufacturing a liquid crystal device having a thin film transistor on a substrate, a pixel electrode connected to the thin film transistor, and an additional capacitor, wherein a source / drain region of the thin film transistor is formed on the flat substrate surface. Forming a first silicon layer and a second silicon layer having a thickness greater than the thickness of the first silicon layer and serving as one electrode of an additional capacitor; and selectively etching the second silicon layer into an uneven shape. A step of forming an insulating film on the first and second uneven silicon layers, and a step of forming a gate electrode of the thin film transistor and the other electrode of the additional capacitor on the insulating film. It is characterized by.

[0010]

FIG. 1 is a sectional view showing the structure of an embodiment of the present invention, and FIG. 3 is an explanatory view showing a manufacturing process for forming the same. An embodiment will be described below with reference to both drawings.

In FIG. 1, reference numeral 101 denotes a TFT unit;
Reference numeral 2 denotes an additional capacitance unit. TFT is poly-SiTF
T, and the source, drain and channel regions are po
The ly-Si layer 104 and the source and drain regions are doped with impurities to reduce the resistance. The gate insulating film 105 is formed of silicon dioxide (hereinafter referred to as Si).
Recorded as O ₂ . ), Silicon nitride or the like.
The formation method includes a thermal oxidation method, a chemical vapor deposition method using a silane-based gas (hereinafter, referred to as a CVD method), and the like. Here, the gate electrode 106 is made of poly doped with impurities.
Although the -Si layer is used, a low-resistance metal, a silicide film, or the like may be used if the subsequent thermal process is performed at a low temperature.
Reference numeral 107 denotes an interlayer insulating film. A contact hole is formed in the interlayer insulating film, a source region of the TFT 101 is contacted with a metal such as aluminum to form a signal line 108, and a drain region is a transparent conductive material such as ITO. A pixel electrode 109 is formed by making contact with the film. Additional capacity 1
Reference numeral 02 denotes poly-Si, which is drawn from the drain region of the TFT and doped with impurities, is used as the lower electrode of the capacitor, the gate insulating film 105 is used as a dielectric film of the capacitor, and the upper electrode is used as the gate electrode. It is formed by 106 and has a configuration in which the load is small in terms of both material and process. The upper electrode of the capacitor portion is formed by providing a signal line in the preceding stage or a new independent capacitor line. In the structure of the present invention, the upper and lower electrodes of the additional capacitor 102 are formed with irregularities in a direction perpendicular to the substrate for the purpose of increasing the bonding area. In general, the capacitance C is expressed as C = ε · ε ₀ · S / t, where ε is the dielectric constant of the dielectric, ε _{0 is the} vacuum dielectric constant, t is the thickness of the dielectric, and S is the junction area. By providing the irregularities as shown in the figure, S increases, and the additional capacitance increases.

Next, an embodiment of a manufacturing process for realizing the present invention will be described with reference to FIG.

FIGS. 1A to 1C show the manufacturing process of the TFT portion, and FIGS. 1D to 1F show the manufacturing process of the additional capacitor portion. Components common to both portions are indicated by the same reference numerals. .

First, p is placed on a transparent insulating film substrate 301 such as quartz.
An poly-Si layer 302 is formed. Thereafter, as described above, in the additional capacitance forming region, the region protruding at the lower electrode portion and T
The FT formation region is covered with a resist or the like, and the other portions are partially removed by etching. Further, the lower electrode region of the additional capacitance portion is doped with an impurity having the same conductivity type as the drain region of the TFT later for the purpose of lowering the resistance. [FIGS. (A) and (b)]. Here, since isotropic etching is desirable because it is effective to form a taper on the side wall portion of the uneven shape to increase the area, wet etching is used here.
The etching solution was of a nitric acid and hydrofluoric acid type. Naturally, if etching can be performed isotropically, dry etching can be used. In addition, regarding the doping of impurities, when the TFT of the pixel is of the N-channel type, doping is performed by ion implantation or thermal diffusion using phosphorus or arsenic as a doping impurity. Reference numeral 303 denotes an ion beam in the ion implantation method. In the case of a p-channel type, a Group 3 element such as boron is used. Here, phosphorus was used as an impurity.

Next, the poly shown in FIGS.
After patterning -Si into a predetermined shape, a gate insulating film 304 is formed. Here, in a dry oxygen atmosphere, 10
Although the SiO ₂ film is formed using a thermal oxidation method at a temperature of about 00 ° C., an insulating film such as SiO ₂ or SiN may be formed by various CVD methods. This gate insulating film 304
It is also used as a dielectric film of the additional capacitance section. At this time, since the lower electrode has irregularities, the SiO ₂ film has the same shape. Subsequently, a gate electrode 305 is formed on the gate insulating film. Here, as described above, the gate electrode 3
As the material 05, a poly-Si film whose resistance is reduced by doping phosphorus at 10 ²⁰ cm ⁻³ or more is used. In addition to using this gate electrode as a scanning line,
It is also used as the upper electrode of the additional capacitance section. Next, T
An FT source / drain region 307 is formed. Here, impurities are doped using the gate electrode as a mask for ion implantation. Reference numeral 306 denotes an ion beam at the time of ion implantation. Here, phosphorus used for lowering the resistance of the lower electrode of the additional capacitor was also doped.
Since the gate electrode is used as a mask, the TFT is formed in a self-aligned manner, which is advantageous for miniaturization of elements. [FIGS. (B) and (e)] Subsequently, after forming the interlayer insulating film 308, annealing for activating impurities in the source / drain regions is performed. Thereafter, a contact hole is formed, a signal line 309 is connected from the source region of the TFT, and a pixel electrode 310 is connected from the drain region.
To form Here, the signal line 309 is preferably made of a low-resistance material in order to accurately write information to be written to a pixel.
Materials such as Al, Al-Si, and Al-Si-Cu are desirable. Here, Al-Si-Cu was used. The pixel electrode 3
Reference numeral 10 denotes a transparent conductive material, which is ITO in this case, but other indium oxide, tin oxide, or the like can be used. [FIGS. (C) and (f)] The embodiment of the present invention is realized by the above steps. Therefore, as described above, the provision of the concavities and convexities in the additional capacitance portion provides the following increase in additional capacitance as compared with the flat case shown in the conventional example (FIG. 2). For example, as shown in FIG. 5, when the sawtooth blade is periodically formed with a pitch of 1, the surface area is 1 / cos θ times if the angle of the substrate is θ. Therefore θ = 4
When the angle is 5 °, the area becomes √2 times, and when θ = 60 °, the area becomes twice, and the additional capacitance increases. Therefore, since the additional capacitance Ca is built in parallel with the pixel capacitance Cp, the capacitance Ct of the entire pixel becomes Ca + Cp, and the unevenness increases the Ct, and contributes to the discharge of the potential charged in the capacitance. Time constant increases, and the potential written to the pixel is accurately held,
Improvement of the image quality displayed on the LCD is realized.

Next, another embodiment of the present invention will be described with reference to FIG. The difference from FIG. 1 is that the uneven shape in FIG. 1 is formed by etching poly-Si as the lower electrode, but in FIG. 4, it is formed below the poly-Si film. By forming irregularities on the underlying transparent insulating film 403, poly
-Si is formed on the upper layer, and consequently, the poly-Si has an uneven shape. The subsequent steps are shown in FIG.
Since the content is the same as that described in FIG. 3, the description is omitted here. Obviously, the same effect as described above can be obtained with respect to the increase in the surface area. In addition, in process, p
Since it is not the step of etching the poly-Si layer but the processing of the base film, the reproducibility and mass productivity are excellent. Further, by forming an insulating film below the TFT and the additional capacitor, there is an effect of blocking diffusion of impurities from the substrate, and the reliability of the element is also improved. Especially p
The poly-Si TFT process is more effective because it requires a process temperature of 400 ° C. or higher.

[0017]

As described above, the liquid crystal display of the present invention has the following effects.

1) The structure of the additional capacitance portion is poly-Si
Since the upper and lower electrodes made of are made uneven, the surface area is increased compared to the planar structure,
It is possible to increase the capacitance value of the additional capacitance.

2) Therefore, the total capacity of the pixel formed in one pixel increases.

3) Therefore, the retention characteristic of the signal voltage written from the signal line is improved by increasing the time constant for the discharge with the increase in the capacity.

4) From the above, an image display faithful to the image signal is obtained, and the image quality is improved.

5) Since the capacity can be increased even with a small occupation area, a high quality image can be obtained without sacrificing the aperture ratio.

6) In the process, the poly-Si film is merely made to have an uneven shape, so that it is excellent in reproducibility and mass productivity.

7) In addition, by forming the irregularities via the underlying transparent insulating film, the signal performance of the entire device is improved, and the yield and the cost are reduced.

[Brief description of the drawings]

FIG. 1 is a structural sectional view showing an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a conventional example.

FIG. 3 is a manufacturing process diagram of the embodiment of the present invention.

FIG. 4 is a structural sectional view showing another embodiment of the present invention.

FIG. 5 is a conceptual diagram of an uneven portion used in the present invention.

[Explanation of symbols]

 101, 201, 401 TFT section 102, 205, 402 Additional capacitance section 103, 301 Transparent insulating substrate 104, 302 poly-Si layer 105, 304 Gate insulating film 106, 305 Gate electrode 107, 308 Interlayer insulating film 108, 203, 309 Signal line 109, 206, 310 Pixel electrode 202 Scan line 204 Pixel capacitance 303, 306 Ion beam 307 Source / drain region 403 Underlying transparent insulating film

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-59-17581 (JP, A) JP-A-59-72479 (JP, A) JP-A-59-137981 (JP, A) JP-A-62 65375 (JP, A) JP-A-57-94779 (JP, A) JP-A-4-367828 (JP, A) JP-A-2-184823 (JP, A) JP-A-6-75248 (JP, A) Hikaru 5-4138 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) G02F 1/1362 H01L 29/78

Claims (2)

(57) [Claims] 1. A liquid crystal device having a thin film transistor on a substrate, a pixel electrode connected to the thin film transistor, and an additional capacitor, wherein a first silicon layer serving as a source / drain region of the thin film transistor and one electrode of the additional capacitor. A second silicon layer thicker than the first silicon layer, an insulating film disposed on the first and second silicon layers, and a gate electrode formed on the insulating film and the other of the additional capacitance. Wherein the surface of the second silicon layer on the side of the insulating film is made uneven. 2. A method for manufacturing a liquid crystal device having a thin film transistor on a substrate, a pixel electrode connected to the thin film transistor, and an additional capacitor, wherein the flat substrate surface serves as a source / drain region of the thin film transistor. Forming a first silicon layer and a second silicon layer that is thicker than the thickness of the first silicon layer and is one electrode of an additional capacitor; and selectively etching the second silicon layer into an uneven shape. Forming an insulating film on the first and second uneven silicon layers; and forming a gate electrode of the thin film transistor and the other electrode of the additional capacitor on the insulating film. Characteristic manufacturing method of a liquid crystal device.