TW265471B - Process of fork-type memory capacitor - Google Patents

Abstract

A process of fork-type dynamic access random memory capacitor comprised the steps of: 1. forming field oxide needed to separate active area; 2. forming field effect transistor consisting of gate dielectric, gate electrode, spacer and source/drain; 3. depositing poly-1, poly-2 and poly-3 layer; 4. in-situ etching the above poly-1, poly-2 and poly-3 layer by lithography and etching so as to form node contact of field effect transistor, later, storage node of capacitor will contact with electricity through the above node contact; 5. depositing one layer of doped polysilicon that will fill up the above node contact; 6. anisotropically performing etchback to the above poly-1 by plasma etching so as to remove doped poly-1 of the above poly-3 surface, and form polysilicon plug in the above node contact; 7. removing one portion of the above poly-3 to expose one portion of the above polysilicon plug; 8. depositing one very thin layer of doped poly-2; 9. forming poly-4; 10. anisotropically performing etchback to the above poly-4 by plasma etching and stopping in doped poly-2 so as to form insulator spacer on sides of the above exposed polysilicon plug; 11. depositing one layer of doped poly-3; 12. anisotropically performing etchback to the above poly-3 by plasma etching and stopping in doped poly-3 so as to form polysilicon spacer on sides of the above insulator spacer; 13. removing the above insulator spacer, completing storage node of capacitor; 14. forming one very thin layer of capacitor dielectric; 15. forming one layer of doped poly-4, and implementing top plate of capacitor by lithography and etching, completing capacitor of dynamic random access memory.