TW291600B - Improved process of stacked dynamic random access memory - Google Patents

Improved process of stacked dynamic random access memory

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Publication number
TW291600B
TW291600B TW84103200A TW84103200A TW291600B TW 291600 B TW291600 B TW 291600B TW 84103200 A TW84103200 A TW 84103200A TW 84103200 A TW84103200 A TW 84103200A TW 291600 B TW291600 B TW 291600B
Authority
TW
Taiwan
Prior art keywords
polysilicon
forming
capacitor
insulator
patterning
Prior art date
Application number
TW84103200A
Other languages
Chinese (zh)
Inventor
Horng-Huei Tzeng
Original Assignee
Vanguard Int Semiconduct Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Vanguard Int Semiconduct Corp filed Critical Vanguard Int Semiconduct Corp
Priority to TW84103200A priority Critical patent/TW291600B/en
Application granted granted Critical
Publication of TW291600B publication Critical patent/TW291600B/en

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Abstract

A manufacturing method of dynamic random access memory with stacked capacitor with high capacitance and high packing density comprises of: (1) on one semiconductor substrate selectively forming field oxide region, leaving active area for implementing transistor; (2) on the above semiconductor substrate forming one transistor gate dielectric; (3) on the above active area in the above field oxide region depositing one doped first polysilicon, removing partial first polysilicon, leaving portion as transistor gate on the above active area, portion as memory word line on the above filed oxide region; (4) on semiconductor substrate on two sides of the above transistor gate forming source/drain structure; (5) on the above active and field oxide area forming one first insulator, and patterning node contact pattern, preparing for electric contact with capacitor storage node; (6) depositing one doped second polysilicon, second insulator and third polysilicon, and by plasma etch on capacitor region patterning the above third polysilicon pattern, and with etching stop on the above second insulator; (7) in high temperature environment with oxygen thermally oxidizing the above third polysilicon to form polyoxide; (8) with the above polyoxide as etch mask, by plasma etch vertically and anisotropically etching the above second polysilicon to some depth so as to from one very narrow trench in the middle of the above second polysilicon; (9) with chemical solution selectively removing the above polyoxide; (10) with chemical solution selectively removing the remaining part of the above second insulator; (11) patterning the above doped second polysilicon with one very narrow trench, forming storage node of stacked capacitor; (12) on the above capacitor storage node surface forming one capacitor dielectric; (13) depositing third polysilicon, by plasma etch patterning the above third polysilicon pattern, forming top electrode of stacked capacitor.
TW84103200A 1995-04-01 1995-04-01 Improved process of stacked dynamic random access memory TW291600B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW84103200A TW291600B (en) 1995-04-01 1995-04-01 Improved process of stacked dynamic random access memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW84103200A TW291600B (en) 1995-04-01 1995-04-01 Improved process of stacked dynamic random access memory

Publications (1)

Publication Number Publication Date
TW291600B true TW291600B (en) 1996-11-21

Family

ID=51398337

Family Applications (1)

Application Number Title Priority Date Filing Date
TW84103200A TW291600B (en) 1995-04-01 1995-04-01 Improved process of stacked dynamic random access memory

Country Status (1)

Country Link
TW (1) TW291600B (en)

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