TW245832B - Process for flash memory cell with split-gate - Google Patents

Abstract

A process for flash memory cell with split-gate, which is applicable to split-gate flash memory cell implemented by semiconductor substrate, includes the following steps: 1. forming tunnel isolation and the first conductive layer on semiconductor substrate in sequence; 2. forming masking material on the destined position of the first conductive layer for defining channel length of split-gate flash memory cell; 3. with masking material as mask, etching the conductive layer to form the floating gate of split-gate flash memory cell, simultaneously forming space on the two sides of floating gate and under masking material; 4. with masking material as mask, doping dopant to semiconductor substrate, and separately forming heavily doped drain and source area of split-gate flash memory cell; 5. removing masking material; 6. with the floating gate as mask, doping dopant to drain area side to semiconductor substrate, and forming lightly doped area on semiconductor substrate between floating gate and drain area; 7. forming gate dielectric layer on semiconductor substrate and floating gate; 8. forming the second conductive layer on dielectric layer, and making the second conductive layer form control gate of split-gate flash memory cell.